root / hw / sun4m.c @ b3c7724c
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1 | 420557e8 | bellard | /*
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2 | ee76f82e | blueswir1 | * QEMU Sun4m & Sun4d & Sun4c System Emulator
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3 | 5fafdf24 | ths | *
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4 | b81b3b10 | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 420557e8 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 420557e8 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 420557e8 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 420557e8 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 420557e8 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 420557e8 | bellard | * furnished to do so, subject to the following conditions:
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12 | 420557e8 | bellard | *
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13 | 420557e8 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 420557e8 | bellard | * all copies or substantial portions of the Software.
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15 | 420557e8 | bellard | *
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16 | 420557e8 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 420557e8 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 420557e8 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 420557e8 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 420557e8 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 420557e8 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 420557e8 | bellard | * THE SOFTWARE.
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23 | 420557e8 | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "qemu-timer.h" |
26 | 87ecb68b | pbrook | #include "sun4m.h" |
27 | 87ecb68b | pbrook | #include "nvram.h" |
28 | 87ecb68b | pbrook | #include "sparc32_dma.h" |
29 | 87ecb68b | pbrook | #include "fdc.h" |
30 | 87ecb68b | pbrook | #include "sysemu.h" |
31 | 87ecb68b | pbrook | #include "net.h" |
32 | 87ecb68b | pbrook | #include "boards.h" |
33 | d2c63fc1 | blueswir1 | #include "firmware_abi.h" |
34 | 8b17de88 | blueswir1 | #include "scsi.h" |
35 | 22548760 | blueswir1 | #include "pc.h" |
36 | 22548760 | blueswir1 | #include "isa.h" |
37 | d2c63fc1 | blueswir1 | |
38 | b3a23197 | blueswir1 | //#define DEBUG_IRQ
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39 | 420557e8 | bellard | |
40 | 36cd9210 | blueswir1 | /*
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41 | 36cd9210 | blueswir1 | * Sun4m architecture was used in the following machines:
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42 | 36cd9210 | blueswir1 | *
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43 | 36cd9210 | blueswir1 | * SPARCserver 6xxMP/xx
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44 | 77f193da | blueswir1 | * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
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45 | 77f193da | blueswir1 | * SPARCclassic X (4/10)
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46 | 36cd9210 | blueswir1 | * SPARCstation LX/ZX (4/30)
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47 | 36cd9210 | blueswir1 | * SPARCstation Voyager
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48 | 36cd9210 | blueswir1 | * SPARCstation 10/xx, SPARCserver 10/xx
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49 | 36cd9210 | blueswir1 | * SPARCstation 5, SPARCserver 5
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50 | 36cd9210 | blueswir1 | * SPARCstation 20/xx, SPARCserver 20
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51 | 36cd9210 | blueswir1 | * SPARCstation 4
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52 | 36cd9210 | blueswir1 | *
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53 | 7d85892b | blueswir1 | * Sun4d architecture was used in the following machines:
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54 | 7d85892b | blueswir1 | *
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55 | 7d85892b | blueswir1 | * SPARCcenter 2000
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56 | 7d85892b | blueswir1 | * SPARCserver 1000
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57 | 7d85892b | blueswir1 | *
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58 | ee76f82e | blueswir1 | * Sun4c architecture was used in the following machines:
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59 | ee76f82e | blueswir1 | * SPARCstation 1/1+, SPARCserver 1/1+
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60 | ee76f82e | blueswir1 | * SPARCstation SLC
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61 | ee76f82e | blueswir1 | * SPARCstation IPC
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62 | ee76f82e | blueswir1 | * SPARCstation ELC
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63 | ee76f82e | blueswir1 | * SPARCstation IPX
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64 | ee76f82e | blueswir1 | *
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65 | 36cd9210 | blueswir1 | * See for example: http://www.sunhelp.org/faq/sunref1.html
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66 | 36cd9210 | blueswir1 | */
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67 | 36cd9210 | blueswir1 | |
68 | b3a23197 | blueswir1 | #ifdef DEBUG_IRQ
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69 | b3a23197 | blueswir1 | #define DPRINTF(fmt, args...) \
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70 | b3a23197 | blueswir1 | do { printf("CPUIRQ: " fmt , ##args); } while (0) |
71 | b3a23197 | blueswir1 | #else
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72 | b3a23197 | blueswir1 | #define DPRINTF(fmt, args...)
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73 | b3a23197 | blueswir1 | #endif
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74 | b3a23197 | blueswir1 | |
75 | 420557e8 | bellard | #define KERNEL_LOAD_ADDR 0x00004000 |
76 | b6f479d3 | bellard | #define CMDLINE_ADDR 0x007ff000 |
77 | 713c45fa | bellard | #define INITRD_LOAD_ADDR 0x00800000 |
78 | aa6ad6fe | blueswir1 | #define PROM_SIZE_MAX (512 * 1024) |
79 | 40ce0a9a | blueswir1 | #define PROM_VADDR 0xffd00000 |
80 | f930d07e | blueswir1 | #define PROM_FILENAME "openbios-sparc32" |
81 | b8174937 | bellard | |
82 | ac2e9d66 | blueswir1 | // Control plane, 8-bit and 24-bit planes
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83 | ac2e9d66 | blueswir1 | #define TCX_SIZE (9 * 1024 * 1024) |
84 | ac2e9d66 | blueswir1 | |
85 | ba3c64fb | bellard | #define MAX_CPUS 16 |
86 | b3a23197 | blueswir1 | #define MAX_PILS 16 |
87 | 420557e8 | bellard | |
88 | 36cd9210 | blueswir1 | struct hwdef {
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89 | 5dcb6b91 | blueswir1 | target_phys_addr_t iommu_base, slavio_base; |
90 | 5dcb6b91 | blueswir1 | target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; |
91 | 5dcb6b91 | blueswir1 | target_phys_addr_t serial_base, fd_base; |
92 | 4c2485de | blueswir1 | target_phys_addr_t idreg_base, dma_base, esp_base, le_base; |
93 | 0019ad53 | blueswir1 | target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base; |
94 | 7eb0c8e8 | blueswir1 | target_phys_addr_t ecc_base; |
95 | 7eb0c8e8 | blueswir1 | uint32_t ecc_version; |
96 | ee76f82e | blueswir1 | target_phys_addr_t sun4c_intctl_base, sun4c_counter_base; |
97 | 36cd9210 | blueswir1 | long vram_size, nvram_size;
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98 | 6341fdcb | blueswir1 | // IRQ numbers are not PIL ones, but master interrupt controller
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99 | e3a79bca | blueswir1 | // register bit numbers
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100 | d7edfd27 | blueswir1 | int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
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101 | e42c20b4 | blueswir1 | int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
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102 | 36cd9210 | blueswir1 | int machine_id; // For NVRAM |
103 | 7fbfb139 | blueswir1 | uint32_t iommu_version; |
104 | e0353fe2 | blueswir1 | uint32_t intbit_to_level[32];
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105 | 3ebf5aaf | blueswir1 | uint64_t max_mem; |
106 | 3ebf5aaf | blueswir1 | const char * const default_cpu_model; |
107 | 36cd9210 | blueswir1 | }; |
108 | 36cd9210 | blueswir1 | |
109 | 7d85892b | blueswir1 | #define MAX_IOUNITS 5 |
110 | 7d85892b | blueswir1 | |
111 | 7d85892b | blueswir1 | struct sun4d_hwdef {
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112 | 7d85892b | blueswir1 | target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base; |
113 | 7d85892b | blueswir1 | target_phys_addr_t counter_base, nvram_base, ms_kb_base; |
114 | 7d85892b | blueswir1 | target_phys_addr_t serial_base; |
115 | 7d85892b | blueswir1 | target_phys_addr_t espdma_base, esp_base; |
116 | 7d85892b | blueswir1 | target_phys_addr_t ledma_base, le_base; |
117 | 7d85892b | blueswir1 | target_phys_addr_t tcx_base; |
118 | 7d85892b | blueswir1 | target_phys_addr_t sbi_base; |
119 | 7d85892b | blueswir1 | unsigned long vram_size, nvram_size; |
120 | 7d85892b | blueswir1 | // IRQ numbers are not PIL ones, but SBI register bit numbers
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121 | 7d85892b | blueswir1 | int esp_irq, le_irq, clock_irq, clock1_irq;
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122 | 7d85892b | blueswir1 | int ser_irq, ms_kb_irq, me_irq;
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123 | 7d85892b | blueswir1 | int machine_id; // For NVRAM |
124 | 7d85892b | blueswir1 | uint32_t iounit_version; |
125 | 7d85892b | blueswir1 | uint64_t max_mem; |
126 | 7d85892b | blueswir1 | const char * const default_cpu_model; |
127 | 7d85892b | blueswir1 | }; |
128 | 7d85892b | blueswir1 | |
129 | 6f7e9aec | bellard | int DMA_get_channel_mode (int nchan) |
130 | 6f7e9aec | bellard | { |
131 | 6f7e9aec | bellard | return 0; |
132 | 6f7e9aec | bellard | } |
133 | 6f7e9aec | bellard | int DMA_read_memory (int nchan, void *buf, int pos, int size) |
134 | 6f7e9aec | bellard | { |
135 | 6f7e9aec | bellard | return 0; |
136 | 6f7e9aec | bellard | } |
137 | 6f7e9aec | bellard | int DMA_write_memory (int nchan, void *buf, int pos, int size) |
138 | 6f7e9aec | bellard | { |
139 | 6f7e9aec | bellard | return 0; |
140 | 6f7e9aec | bellard | } |
141 | 6f7e9aec | bellard | void DMA_hold_DREQ (int nchan) {} |
142 | 6f7e9aec | bellard | void DMA_release_DREQ (int nchan) {} |
143 | 6f7e9aec | bellard | void DMA_schedule(int nchan) {} |
144 | 6f7e9aec | bellard | void DMA_run (void) {} |
145 | 6f7e9aec | bellard | void DMA_init (int high_page_enable) {} |
146 | 6f7e9aec | bellard | void DMA_register_channel (int nchan, |
147 | 6f7e9aec | bellard | DMA_transfer_handler transfer_handler, |
148 | 6f7e9aec | bellard | void *opaque)
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149 | 6f7e9aec | bellard | { |
150 | 6f7e9aec | bellard | } |
151 | 6f7e9aec | bellard | |
152 | 81864572 | blueswir1 | static int nvram_boot_set(void *opaque, const char *boot_device) |
153 | 81864572 | blueswir1 | { |
154 | 81864572 | blueswir1 | unsigned int i; |
155 | 81864572 | blueswir1 | uint8_t image[sizeof(ohwcfg_v3_t)];
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156 | 81864572 | blueswir1 | ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ |
157 | 81864572 | blueswir1 | m48t59_t *nvram = (m48t59_t *)opaque; |
158 | 81864572 | blueswir1 | |
159 | 81864572 | blueswir1 | for (i = 0; i < sizeof(image); i++) |
160 | 81864572 | blueswir1 | image[i] = m48t59_read(nvram, i) & 0xff;
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161 | 81864572 | blueswir1 | |
162 | e7fb1406 | blueswir1 | strcpy((char *)header->boot_devices, boot_device);
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163 | 81864572 | blueswir1 | header->nboot_devices = strlen(boot_device) & 0xff;
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164 | 81864572 | blueswir1 | header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8)); |
165 | 81864572 | blueswir1 | |
166 | 81864572 | blueswir1 | for (i = 0; i < sizeof(image); i++) |
167 | 81864572 | blueswir1 | m48t59_write(nvram, i, image[i]); |
168 | 81864572 | blueswir1 | |
169 | 81864572 | blueswir1 | return 0; |
170 | 81864572 | blueswir1 | } |
171 | 81864572 | blueswir1 | |
172 | 6f7e9aec | bellard | extern int nographic; |
173 | 6f7e9aec | bellard | |
174 | 819385c5 | bellard | static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline, |
175 | 6ef05b95 | blueswir1 | const char *boot_devices, ram_addr_t RAM_size, |
176 | f930d07e | blueswir1 | uint32_t kernel_size, |
177 | f930d07e | blueswir1 | int width, int height, int depth, |
178 | 7d85892b | blueswir1 | int machine_id, const char *arch) |
179 | e80cfcfc | bellard | { |
180 | d2c63fc1 | blueswir1 | unsigned int i; |
181 | 66508601 | blueswir1 | uint32_t start, end; |
182 | d2c63fc1 | blueswir1 | uint8_t image[0x1ff0];
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183 | d2c63fc1 | blueswir1 | ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ |
184 | d2c63fc1 | blueswir1 | struct sparc_arch_cfg *sparc_header;
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185 | d2c63fc1 | blueswir1 | struct OpenBIOS_nvpart_v1 *part_header;
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186 | d2c63fc1 | blueswir1 | |
187 | d2c63fc1 | blueswir1 | memset(image, '\0', sizeof(image)); |
188 | e80cfcfc | bellard | |
189 | 6f7e9aec | bellard | // Try to match PPC NVRAM
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190 | e7fb1406 | blueswir1 | strcpy((char *)header->struct_ident, "QEMU_BIOS"); |
191 | d2c63fc1 | blueswir1 | header->struct_version = cpu_to_be32(3); /* structure v3 */ |
192 | d2c63fc1 | blueswir1 | |
193 | d2c63fc1 | blueswir1 | header->nvram_size = cpu_to_be16(0x2000);
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194 | d2c63fc1 | blueswir1 | header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
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195 | d2c63fc1 | blueswir1 | header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg)); |
196 | e7fb1406 | blueswir1 | strcpy((char *)header->arch, arch);
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197 | d2c63fc1 | blueswir1 | header->nb_cpus = smp_cpus & 0xff;
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198 | d2c63fc1 | blueswir1 | header->RAM0_base = 0;
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199 | d2c63fc1 | blueswir1 | header->RAM0_size = cpu_to_be64((uint64_t)RAM_size); |
200 | e7fb1406 | blueswir1 | strcpy((char *)header->boot_devices, boot_devices);
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201 | d2c63fc1 | blueswir1 | header->nboot_devices = strlen(boot_devices) & 0xff;
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202 | d2c63fc1 | blueswir1 | header->kernel_image = cpu_to_be64((uint64_t)KERNEL_LOAD_ADDR); |
203 | d2c63fc1 | blueswir1 | header->kernel_size = cpu_to_be64((uint64_t)kernel_size); |
204 | b6f479d3 | bellard | if (cmdline) {
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205 | 293f78bc | blueswir1 | pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline); |
206 | d2c63fc1 | blueswir1 | header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR); |
207 | d2c63fc1 | blueswir1 | header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline)); |
208 | b6f479d3 | bellard | } |
209 | d2c63fc1 | blueswir1 | // XXX add initrd_image, initrd_size
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210 | d2c63fc1 | blueswir1 | header->width = cpu_to_be16(width); |
211 | d2c63fc1 | blueswir1 | header->height = cpu_to_be16(height); |
212 | d2c63fc1 | blueswir1 | header->depth = cpu_to_be16(depth); |
213 | d2c63fc1 | blueswir1 | if (nographic)
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214 | d2c63fc1 | blueswir1 | header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS); |
215 | d2c63fc1 | blueswir1 | |
216 | d2c63fc1 | blueswir1 | header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8)); |
217 | d2c63fc1 | blueswir1 | |
218 | d2c63fc1 | blueswir1 | // Architecture specific header
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219 | d2c63fc1 | blueswir1 | start = sizeof(ohwcfg_v3_t);
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220 | d2c63fc1 | blueswir1 | sparc_header = (struct sparc_arch_cfg *)&image[start];
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221 | d2c63fc1 | blueswir1 | sparc_header->valid = 0;
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222 | d2c63fc1 | blueswir1 | start += sizeof(struct sparc_arch_cfg); |
223 | b6f479d3 | bellard | |
224 | 66508601 | blueswir1 | // OpenBIOS nvram variables
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225 | 66508601 | blueswir1 | // Variable partition
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226 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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227 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_SYSTEM; |
228 | d2c63fc1 | blueswir1 | strcpy(part_header->name, "system");
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229 | 66508601 | blueswir1 | |
230 | d2c63fc1 | blueswir1 | end = start + sizeof(struct OpenBIOS_nvpart_v1); |
231 | 66508601 | blueswir1 | for (i = 0; i < nb_prom_envs; i++) |
232 | d2c63fc1 | blueswir1 | end = OpenBIOS_set_var(image, end, prom_envs[i]); |
233 | d2c63fc1 | blueswir1 | |
234 | d2c63fc1 | blueswir1 | // End marker
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235 | d2c63fc1 | blueswir1 | image[end++] = '\0';
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236 | 66508601 | blueswir1 | |
237 | 66508601 | blueswir1 | end = start + ((end - start + 15) & ~15); |
238 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
239 | 66508601 | blueswir1 | |
240 | 66508601 | blueswir1 | // free partition
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241 | 66508601 | blueswir1 | start = end; |
242 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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243 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_FREE; |
244 | d2c63fc1 | blueswir1 | strcpy(part_header->name, "free");
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245 | 66508601 | blueswir1 | |
246 | 66508601 | blueswir1 | end = 0x1fd0;
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247 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
248 | d2c63fc1 | blueswir1 | |
249 | d2c63fc1 | blueswir1 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, machine_id); |
250 | d2c63fc1 | blueswir1 | |
251 | d2c63fc1 | blueswir1 | for (i = 0; i < sizeof(image); i++) |
252 | d2c63fc1 | blueswir1 | m48t59_write(nvram, i, image[i]); |
253 | 81864572 | blueswir1 | |
254 | 81864572 | blueswir1 | qemu_register_boot_set(nvram_boot_set, nvram); |
255 | e80cfcfc | bellard | } |
256 | e80cfcfc | bellard | |
257 | e80cfcfc | bellard | static void *slavio_intctl; |
258 | e80cfcfc | bellard | |
259 | 22548760 | blueswir1 | void pic_info(void) |
260 | e80cfcfc | bellard | { |
261 | 7d85892b | blueswir1 | if (slavio_intctl)
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262 | 7d85892b | blueswir1 | slavio_pic_info(slavio_intctl); |
263 | e80cfcfc | bellard | } |
264 | e80cfcfc | bellard | |
265 | 22548760 | blueswir1 | void irq_info(void) |
266 | e80cfcfc | bellard | { |
267 | 7d85892b | blueswir1 | if (slavio_intctl)
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268 | 7d85892b | blueswir1 | slavio_irq_info(slavio_intctl); |
269 | e80cfcfc | bellard | } |
270 | e80cfcfc | bellard | |
271 | 327ac2e7 | blueswir1 | void cpu_check_irqs(CPUState *env)
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272 | 327ac2e7 | blueswir1 | { |
273 | 327ac2e7 | blueswir1 | if (env->pil_in && (env->interrupt_index == 0 || |
274 | 327ac2e7 | blueswir1 | (env->interrupt_index & ~15) == TT_EXTINT)) {
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275 | 327ac2e7 | blueswir1 | unsigned int i; |
276 | 327ac2e7 | blueswir1 | |
277 | 327ac2e7 | blueswir1 | for (i = 15; i > 0; i--) { |
278 | 327ac2e7 | blueswir1 | if (env->pil_in & (1 << i)) { |
279 | 327ac2e7 | blueswir1 | int old_interrupt = env->interrupt_index;
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280 | 327ac2e7 | blueswir1 | |
281 | 327ac2e7 | blueswir1 | env->interrupt_index = TT_EXTINT | i; |
282 | f32d7ec5 | blueswir1 | if (old_interrupt != env->interrupt_index) {
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283 | f32d7ec5 | blueswir1 | DPRINTF("Set CPU IRQ %d\n", i);
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284 | 327ac2e7 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
285 | f32d7ec5 | blueswir1 | } |
286 | 327ac2e7 | blueswir1 | break;
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287 | 327ac2e7 | blueswir1 | } |
288 | 327ac2e7 | blueswir1 | } |
289 | 327ac2e7 | blueswir1 | } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { |
290 | f32d7ec5 | blueswir1 | DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15); |
291 | 327ac2e7 | blueswir1 | env->interrupt_index = 0;
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292 | 327ac2e7 | blueswir1 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
293 | 327ac2e7 | blueswir1 | } |
294 | 327ac2e7 | blueswir1 | } |
295 | 327ac2e7 | blueswir1 | |
296 | b3a23197 | blueswir1 | static void cpu_set_irq(void *opaque, int irq, int level) |
297 | b3a23197 | blueswir1 | { |
298 | b3a23197 | blueswir1 | CPUState *env = opaque; |
299 | b3a23197 | blueswir1 | |
300 | b3a23197 | blueswir1 | if (level) {
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301 | b3a23197 | blueswir1 | DPRINTF("Raise CPU IRQ %d\n", irq);
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302 | b3a23197 | blueswir1 | env->halted = 0;
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303 | 327ac2e7 | blueswir1 | env->pil_in |= 1 << irq;
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304 | 327ac2e7 | blueswir1 | cpu_check_irqs(env); |
305 | b3a23197 | blueswir1 | } else {
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306 | b3a23197 | blueswir1 | DPRINTF("Lower CPU IRQ %d\n", irq);
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307 | 327ac2e7 | blueswir1 | env->pil_in &= ~(1 << irq);
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308 | 327ac2e7 | blueswir1 | cpu_check_irqs(env); |
309 | b3a23197 | blueswir1 | } |
310 | b3a23197 | blueswir1 | } |
311 | b3a23197 | blueswir1 | |
312 | b3a23197 | blueswir1 | static void dummy_cpu_set_irq(void *opaque, int irq, int level) |
313 | b3a23197 | blueswir1 | { |
314 | b3a23197 | blueswir1 | } |
315 | b3a23197 | blueswir1 | |
316 | 3475187d | bellard | static void *slavio_misc; |
317 | 3475187d | bellard | |
318 | 3475187d | bellard | void qemu_system_powerdown(void) |
319 | 3475187d | bellard | { |
320 | 3475187d | bellard | slavio_set_power_fail(slavio_misc, 1);
|
321 | 3475187d | bellard | } |
322 | 3475187d | bellard | |
323 | c68ea704 | bellard | static void main_cpu_reset(void *opaque) |
324 | c68ea704 | bellard | { |
325 | c68ea704 | bellard | CPUState *env = opaque; |
326 | 3d29fbef | blueswir1 | |
327 | 3d29fbef | blueswir1 | cpu_reset(env); |
328 | 3d29fbef | blueswir1 | env->halted = 0;
|
329 | 3d29fbef | blueswir1 | } |
330 | 3d29fbef | blueswir1 | |
331 | 3d29fbef | blueswir1 | static void secondary_cpu_reset(void *opaque) |
332 | 3d29fbef | blueswir1 | { |
333 | 3d29fbef | blueswir1 | CPUState *env = opaque; |
334 | 3d29fbef | blueswir1 | |
335 | c68ea704 | bellard | cpu_reset(env); |
336 | 3d29fbef | blueswir1 | env->halted = 1;
|
337 | c68ea704 | bellard | } |
338 | c68ea704 | bellard | |
339 | 3ebf5aaf | blueswir1 | static unsigned long sun4m_load_kernel(const char *kernel_filename, |
340 | 293f78bc | blueswir1 | const char *initrd_filename, |
341 | 293f78bc | blueswir1 | ram_addr_t RAM_size) |
342 | 3ebf5aaf | blueswir1 | { |
343 | 3ebf5aaf | blueswir1 | int linux_boot;
|
344 | 3ebf5aaf | blueswir1 | unsigned int i; |
345 | 3ebf5aaf | blueswir1 | long initrd_size, kernel_size;
|
346 | 3ebf5aaf | blueswir1 | |
347 | 3ebf5aaf | blueswir1 | linux_boot = (kernel_filename != NULL);
|
348 | 3ebf5aaf | blueswir1 | |
349 | 3ebf5aaf | blueswir1 | kernel_size = 0;
|
350 | 3ebf5aaf | blueswir1 | if (linux_boot) {
|
351 | 3ebf5aaf | blueswir1 | kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL, |
352 | 3ebf5aaf | blueswir1 | NULL);
|
353 | 3ebf5aaf | blueswir1 | if (kernel_size < 0) |
354 | 293f78bc | blueswir1 | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
355 | 293f78bc | blueswir1 | RAM_size - KERNEL_LOAD_ADDR); |
356 | 3ebf5aaf | blueswir1 | if (kernel_size < 0) |
357 | 293f78bc | blueswir1 | kernel_size = load_image_targphys(kernel_filename, |
358 | 293f78bc | blueswir1 | KERNEL_LOAD_ADDR, |
359 | 293f78bc | blueswir1 | RAM_size - KERNEL_LOAD_ADDR); |
360 | 3ebf5aaf | blueswir1 | if (kernel_size < 0) { |
361 | 3ebf5aaf | blueswir1 | fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
362 | 3ebf5aaf | blueswir1 | kernel_filename); |
363 | 3ebf5aaf | blueswir1 | exit(1);
|
364 | 3ebf5aaf | blueswir1 | } |
365 | 3ebf5aaf | blueswir1 | |
366 | 3ebf5aaf | blueswir1 | /* load initrd */
|
367 | 3ebf5aaf | blueswir1 | initrd_size = 0;
|
368 | 3ebf5aaf | blueswir1 | if (initrd_filename) {
|
369 | 293f78bc | blueswir1 | initrd_size = load_image_targphys(initrd_filename, |
370 | 293f78bc | blueswir1 | INITRD_LOAD_ADDR, |
371 | 293f78bc | blueswir1 | RAM_size - INITRD_LOAD_ADDR); |
372 | 3ebf5aaf | blueswir1 | if (initrd_size < 0) { |
373 | 3ebf5aaf | blueswir1 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
374 | 3ebf5aaf | blueswir1 | initrd_filename); |
375 | 3ebf5aaf | blueswir1 | exit(1);
|
376 | 3ebf5aaf | blueswir1 | } |
377 | 3ebf5aaf | blueswir1 | } |
378 | 3ebf5aaf | blueswir1 | if (initrd_size > 0) { |
379 | 3ebf5aaf | blueswir1 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
380 | 293f78bc | blueswir1 | if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS |
381 | 293f78bc | blueswir1 | stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
|
382 | 293f78bc | blueswir1 | stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
|
383 | 3ebf5aaf | blueswir1 | break;
|
384 | 3ebf5aaf | blueswir1 | } |
385 | 3ebf5aaf | blueswir1 | } |
386 | 3ebf5aaf | blueswir1 | } |
387 | 3ebf5aaf | blueswir1 | } |
388 | 3ebf5aaf | blueswir1 | return kernel_size;
|
389 | 3ebf5aaf | blueswir1 | } |
390 | 3ebf5aaf | blueswir1 | |
391 | 6ef05b95 | blueswir1 | static void sun4m_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size, |
392 | 3ebf5aaf | blueswir1 | const char *boot_device, |
393 | 3ebf5aaf | blueswir1 | DisplayState *ds, const char *kernel_filename, |
394 | 3ebf5aaf | blueswir1 | const char *kernel_cmdline, |
395 | 3ebf5aaf | blueswir1 | const char *initrd_filename, const char *cpu_model) |
396 | 36cd9210 | blueswir1 | |
397 | 420557e8 | bellard | { |
398 | ba3c64fb | bellard | CPUState *env, *envs[MAX_CPUS]; |
399 | 713c45fa | bellard | unsigned int i; |
400 | b3ceef24 | blueswir1 | void *iommu, *espdma, *ledma, *main_esp, *nvram;
|
401 | b3a23197 | blueswir1 | qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq, |
402 | d7edfd27 | blueswir1 | *espdma_irq, *ledma_irq; |
403 | 2d069bab | blueswir1 | qemu_irq *esp_reset, *le_reset; |
404 | 2be17ebd | blueswir1 | qemu_irq *fdc_tc; |
405 | 3ebf5aaf | blueswir1 | unsigned long prom_offset, kernel_size; |
406 | 3ebf5aaf | blueswir1 | int ret;
|
407 | 3ebf5aaf | blueswir1 | char buf[1024]; |
408 | e4bcb14c | ths | BlockDriverState *fd[MAX_FD]; |
409 | 22548760 | blueswir1 | int drive_index;
|
410 | 420557e8 | bellard | |
411 | ba3c64fb | bellard | /* init CPUs */
|
412 | 3ebf5aaf | blueswir1 | if (!cpu_model)
|
413 | 3ebf5aaf | blueswir1 | cpu_model = hwdef->default_cpu_model; |
414 | b3a23197 | blueswir1 | |
415 | ba3c64fb | bellard | for(i = 0; i < smp_cpus; i++) { |
416 | aaed909a | bellard | env = cpu_init(cpu_model); |
417 | aaed909a | bellard | if (!env) {
|
418 | 8e82c6a8 | blueswir1 | fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
|
419 | aaed909a | bellard | exit(1);
|
420 | aaed909a | bellard | } |
421 | aaed909a | bellard | cpu_sparc_set_id(env, i); |
422 | ba3c64fb | bellard | envs[i] = env; |
423 | 3d29fbef | blueswir1 | if (i == 0) { |
424 | 3d29fbef | blueswir1 | qemu_register_reset(main_cpu_reset, env); |
425 | 3d29fbef | blueswir1 | } else {
|
426 | 3d29fbef | blueswir1 | qemu_register_reset(secondary_cpu_reset, env); |
427 | ba3c64fb | bellard | env->halted = 1;
|
428 | 3d29fbef | blueswir1 | } |
429 | b3a23197 | blueswir1 | cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS); |
430 | 3ebf5aaf | blueswir1 | env->prom_addr = hwdef->slavio_base; |
431 | ba3c64fb | bellard | } |
432 | b3a23197 | blueswir1 | |
433 | b3a23197 | blueswir1 | for (i = smp_cpus; i < MAX_CPUS; i++)
|
434 | b3a23197 | blueswir1 | cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
|
435 | b3a23197 | blueswir1 | |
436 | 3ebf5aaf | blueswir1 | |
437 | 420557e8 | bellard | /* allocate RAM */
|
438 | 3ebf5aaf | blueswir1 | if ((uint64_t)RAM_size > hwdef->max_mem) {
|
439 | 77f193da | blueswir1 | fprintf(stderr, |
440 | 77f193da | blueswir1 | "qemu: Too much memory for this machine: %d, maximum %d\n",
|
441 | 6ef05b95 | blueswir1 | (unsigned int)(RAM_size / (1024 * 1024)), |
442 | 3ebf5aaf | blueswir1 | (unsigned int)(hwdef->max_mem / (1024 * 1024))); |
443 | 3ebf5aaf | blueswir1 | exit(1);
|
444 | 3ebf5aaf | blueswir1 | } |
445 | b3ceef24 | blueswir1 | cpu_register_physical_memory(0, RAM_size, 0); |
446 | 420557e8 | bellard | |
447 | 3ebf5aaf | blueswir1 | /* load boot prom */
|
448 | 3ebf5aaf | blueswir1 | prom_offset = RAM_size + hwdef->vram_size; |
449 | 3ebf5aaf | blueswir1 | cpu_register_physical_memory(hwdef->slavio_base, |
450 | 3ebf5aaf | blueswir1 | (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
|
451 | 3ebf5aaf | blueswir1 | TARGET_PAGE_MASK, |
452 | 3ebf5aaf | blueswir1 | prom_offset | IO_MEM_ROM); |
453 | 3ebf5aaf | blueswir1 | |
454 | 3ebf5aaf | blueswir1 | if (bios_name == NULL) |
455 | 3ebf5aaf | blueswir1 | bios_name = PROM_FILENAME; |
456 | 3ebf5aaf | blueswir1 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
457 | 3ebf5aaf | blueswir1 | ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL); |
458 | 3ebf5aaf | blueswir1 | if (ret < 0 || ret > PROM_SIZE_MAX) |
459 | e01f4a1c | blueswir1 | ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX); |
460 | 3ebf5aaf | blueswir1 | if (ret < 0 || ret > PROM_SIZE_MAX) { |
461 | 3ebf5aaf | blueswir1 | fprintf(stderr, "qemu: could not load prom '%s'\n",
|
462 | 3ebf5aaf | blueswir1 | buf); |
463 | 3ebf5aaf | blueswir1 | exit(1);
|
464 | 3ebf5aaf | blueswir1 | } |
465 | 4c2485de | blueswir1 | prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
|
466 | 3ebf5aaf | blueswir1 | |
467 | 3ebf5aaf | blueswir1 | /* set up devices */
|
468 | 36cd9210 | blueswir1 | slavio_intctl = slavio_intctl_init(hwdef->intctl_base, |
469 | 5dcb6b91 | blueswir1 | hwdef->intctl_base + 0x10000ULL,
|
470 | d537cf6c | pbrook | &hwdef->intbit_to_level[0],
|
471 | d7edfd27 | blueswir1 | &slavio_irq, &slavio_cpu_irq, |
472 | b3a23197 | blueswir1 | cpu_irqs, |
473 | d7edfd27 | blueswir1 | hwdef->clock_irq); |
474 | b3a23197 | blueswir1 | |
475 | 4c2485de | blueswir1 | if (hwdef->idreg_base != (target_phys_addr_t)-1) { |
476 | 293f78bc | blueswir1 | static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; |
477 | 4c2485de | blueswir1 | |
478 | 293f78bc | blueswir1 | cpu_register_physical_memory(hwdef->idreg_base, sizeof(idreg_data),
|
479 | 4c2485de | blueswir1 | prom_offset | IO_MEM_ROM); |
480 | 293f78bc | blueswir1 | cpu_physical_memory_write_rom(hwdef->idreg_base, idreg_data, |
481 | 293f78bc | blueswir1 | sizeof(idreg_data));
|
482 | 4c2485de | blueswir1 | } |
483 | 4c2485de | blueswir1 | |
484 | ff403da6 | blueswir1 | iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
485 | ff403da6 | blueswir1 | slavio_irq[hwdef->me_irq]); |
486 | ff403da6 | blueswir1 | |
487 | 5aca8c3b | blueswir1 | espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq], |
488 | 2d069bab | blueswir1 | iommu, &espdma_irq, &esp_reset); |
489 | 2d069bab | blueswir1 | |
490 | 5aca8c3b | blueswir1 | ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
|
491 | 2d069bab | blueswir1 | slavio_irq[hwdef->le_irq], iommu, &ledma_irq, |
492 | 2d069bab | blueswir1 | &le_reset); |
493 | ba3c64fb | bellard | |
494 | eee0b836 | blueswir1 | if (graphic_depth != 8 && graphic_depth != 24) { |
495 | eee0b836 | blueswir1 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
496 | eee0b836 | blueswir1 | exit (1);
|
497 | eee0b836 | blueswir1 | } |
498 | b3ceef24 | blueswir1 | tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size, |
499 | eee0b836 | blueswir1 | hwdef->vram_size, graphic_width, graphic_height, graphic_depth); |
500 | dbe06e18 | blueswir1 | |
501 | dbe06e18 | blueswir1 | if (nd_table[0].model == NULL |
502 | dbe06e18 | blueswir1 | || strcmp(nd_table[0].model, "lance") == 0) { |
503 | 2d069bab | blueswir1 | lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
|
504 | c4a7060c | blueswir1 | } else if (strcmp(nd_table[0].model, "?") == 0) { |
505 | c4a7060c | blueswir1 | fprintf(stderr, "qemu: Supported NICs: lance\n");
|
506 | c4a7060c | blueswir1 | exit (1);
|
507 | dbe06e18 | blueswir1 | } else {
|
508 | dbe06e18 | blueswir1 | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
509 | dbe06e18 | blueswir1 | exit (1);
|
510 | a41b2ff2 | pbrook | } |
511 | dbe06e18 | blueswir1 | |
512 | d537cf6c | pbrook | nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, |
513 | d537cf6c | pbrook | hwdef->nvram_size, 8);
|
514 | 81732d19 | blueswir1 | |
515 | 81732d19 | blueswir1 | slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq], |
516 | 19f8e5dd | blueswir1 | slavio_cpu_irq, smp_cpus); |
517 | 81732d19 | blueswir1 | |
518 | 577390ff | blueswir1 | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq], |
519 | 577390ff | blueswir1 | nographic); |
520 | b81b3b10 | bellard | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
521 | b81b3b10 | bellard | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
522 | d537cf6c | pbrook | slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], |
523 | d537cf6c | pbrook | serial_hds[1], serial_hds[0]); |
524 | 741402f9 | blueswir1 | |
525 | 2be17ebd | blueswir1 | slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->apc_base, |
526 | 2be17ebd | blueswir1 | hwdef->aux1_base, hwdef->aux2_base, |
527 | 2be17ebd | blueswir1 | slavio_irq[hwdef->me_irq], envs[0],
|
528 | 2be17ebd | blueswir1 | &fdc_tc); |
529 | 2be17ebd | blueswir1 | |
530 | e4bcb14c | ths | if (hwdef->fd_base != (target_phys_addr_t)-1) { |
531 | e4bcb14c | ths | /* there is zero or one floppy drive */
|
532 | 309e60bd | blueswir1 | memset(fd, 0, sizeof(fd)); |
533 | 22548760 | blueswir1 | drive_index = drive_get_index(IF_FLOPPY, 0, 0); |
534 | 22548760 | blueswir1 | if (drive_index != -1) |
535 | 22548760 | blueswir1 | fd[0] = drives_table[drive_index].bdrv;
|
536 | 2d069bab | blueswir1 | |
537 | 2be17ebd | blueswir1 | sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd, |
538 | 2be17ebd | blueswir1 | fdc_tc); |
539 | e4bcb14c | ths | } |
540 | e4bcb14c | ths | |
541 | e4bcb14c | ths | if (drive_get_max_bus(IF_SCSI) > 0) { |
542 | e4bcb14c | ths | fprintf(stderr, "qemu: too many SCSI bus\n");
|
543 | e4bcb14c | ths | exit(1);
|
544 | e4bcb14c | ths | } |
545 | e4bcb14c | ths | |
546 | 5d20fa6b | blueswir1 | main_esp = esp_init(hwdef->esp_base, 2,
|
547 | 8b17de88 | blueswir1 | espdma_memory_read, espdma_memory_write, |
548 | 8b17de88 | blueswir1 | espdma, *espdma_irq, esp_reset); |
549 | f1587550 | ths | |
550 | e4bcb14c | ths | for (i = 0; i < ESP_MAX_DEVS; i++) { |
551 | 22548760 | blueswir1 | drive_index = drive_get_index(IF_SCSI, 0, i);
|
552 | 22548760 | blueswir1 | if (drive_index == -1) |
553 | e4bcb14c | ths | continue;
|
554 | 22548760 | blueswir1 | esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i); |
555 | f1587550 | ths | } |
556 | f1587550 | ths | |
557 | 5dcb6b91 | blueswir1 | if (hwdef->cs_base != (target_phys_addr_t)-1) |
558 | 803b3c7b | blueswir1 | cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl); |
559 | b3ceef24 | blueswir1 | |
560 | 293f78bc | blueswir1 | kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
561 | 293f78bc | blueswir1 | RAM_size); |
562 | 36cd9210 | blueswir1 | |
563 | 36cd9210 | blueswir1 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
564 | b3ceef24 | blueswir1 | boot_device, RAM_size, kernel_size, graphic_width, |
565 | 7d85892b | blueswir1 | graphic_height, graphic_depth, hwdef->machine_id, "Sun4m");
|
566 | 7eb0c8e8 | blueswir1 | |
567 | 7eb0c8e8 | blueswir1 | if (hwdef->ecc_base != (target_phys_addr_t)-1) |
568 | e42c20b4 | blueswir1 | ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq], |
569 | e42c20b4 | blueswir1 | hwdef->ecc_version); |
570 | 36cd9210 | blueswir1 | } |
571 | 36cd9210 | blueswir1 | |
572 | 6ef05b95 | blueswir1 | static void sun4c_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size, |
573 | ee76f82e | blueswir1 | const char *boot_device, |
574 | ee76f82e | blueswir1 | DisplayState *ds, const char *kernel_filename, |
575 | ee76f82e | blueswir1 | const char *kernel_cmdline, |
576 | ee76f82e | blueswir1 | const char *initrd_filename, const char *cpu_model) |
577 | ee76f82e | blueswir1 | { |
578 | ee76f82e | blueswir1 | CPUState *env; |
579 | ee76f82e | blueswir1 | unsigned int i; |
580 | ee76f82e | blueswir1 | void *iommu, *espdma, *ledma, *main_esp, *nvram;
|
581 | ee76f82e | blueswir1 | qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq; |
582 | ee76f82e | blueswir1 | qemu_irq *esp_reset, *le_reset; |
583 | 2be17ebd | blueswir1 | qemu_irq *fdc_tc; |
584 | ee76f82e | blueswir1 | unsigned long prom_offset, kernel_size; |
585 | ee76f82e | blueswir1 | int ret;
|
586 | ee76f82e | blueswir1 | char buf[1024]; |
587 | ee76f82e | blueswir1 | BlockDriverState *fd[MAX_FD]; |
588 | 22548760 | blueswir1 | int drive_index;
|
589 | ee76f82e | blueswir1 | |
590 | ee76f82e | blueswir1 | /* init CPU */
|
591 | ee76f82e | blueswir1 | if (!cpu_model)
|
592 | ee76f82e | blueswir1 | cpu_model = hwdef->default_cpu_model; |
593 | ee76f82e | blueswir1 | |
594 | ee76f82e | blueswir1 | env = cpu_init(cpu_model); |
595 | ee76f82e | blueswir1 | if (!env) {
|
596 | 8e82c6a8 | blueswir1 | fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
|
597 | ee76f82e | blueswir1 | exit(1);
|
598 | ee76f82e | blueswir1 | } |
599 | ee76f82e | blueswir1 | |
600 | ee76f82e | blueswir1 | cpu_sparc_set_id(env, 0);
|
601 | ee76f82e | blueswir1 | |
602 | ee76f82e | blueswir1 | qemu_register_reset(main_cpu_reset, env); |
603 | ee76f82e | blueswir1 | cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); |
604 | cebb73aa | blueswir1 | env->prom_addr = hwdef->slavio_base; |
605 | ee76f82e | blueswir1 | |
606 | ee76f82e | blueswir1 | /* allocate RAM */
|
607 | ee76f82e | blueswir1 | if ((uint64_t)RAM_size > hwdef->max_mem) {
|
608 | 77f193da | blueswir1 | fprintf(stderr, |
609 | 77f193da | blueswir1 | "qemu: Too much memory for this machine: %d, maximum %d\n",
|
610 | 6ef05b95 | blueswir1 | (unsigned int)(RAM_size / (1024 * 1024)), |
611 | 6ef05b95 | blueswir1 | (unsigned int)(hwdef->max_mem / (1024 * 1024))); |
612 | ee76f82e | blueswir1 | exit(1);
|
613 | ee76f82e | blueswir1 | } |
614 | ee76f82e | blueswir1 | cpu_register_physical_memory(0, RAM_size, 0); |
615 | ee76f82e | blueswir1 | |
616 | ee76f82e | blueswir1 | /* load boot prom */
|
617 | ee76f82e | blueswir1 | prom_offset = RAM_size + hwdef->vram_size; |
618 | ee76f82e | blueswir1 | cpu_register_physical_memory(hwdef->slavio_base, |
619 | ee76f82e | blueswir1 | (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
|
620 | ee76f82e | blueswir1 | TARGET_PAGE_MASK, |
621 | ee76f82e | blueswir1 | prom_offset | IO_MEM_ROM); |
622 | ee76f82e | blueswir1 | |
623 | ee76f82e | blueswir1 | if (bios_name == NULL) |
624 | ee76f82e | blueswir1 | bios_name = PROM_FILENAME; |
625 | ee76f82e | blueswir1 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
626 | ee76f82e | blueswir1 | ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL); |
627 | ee76f82e | blueswir1 | if (ret < 0 || ret > PROM_SIZE_MAX) |
628 | e01f4a1c | blueswir1 | ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX); |
629 | ee76f82e | blueswir1 | if (ret < 0 || ret > PROM_SIZE_MAX) { |
630 | ee76f82e | blueswir1 | fprintf(stderr, "qemu: could not load prom '%s'\n",
|
631 | ee76f82e | blueswir1 | buf); |
632 | ee76f82e | blueswir1 | exit(1);
|
633 | ee76f82e | blueswir1 | } |
634 | ee76f82e | blueswir1 | prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
|
635 | ee76f82e | blueswir1 | |
636 | ee76f82e | blueswir1 | /* set up devices */
|
637 | ee76f82e | blueswir1 | slavio_intctl = sun4c_intctl_init(hwdef->sun4c_intctl_base, |
638 | ee76f82e | blueswir1 | &slavio_irq, cpu_irqs); |
639 | ee76f82e | blueswir1 | |
640 | ff403da6 | blueswir1 | iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
641 | ff403da6 | blueswir1 | slavio_irq[hwdef->me_irq]); |
642 | ee76f82e | blueswir1 | |
643 | ee76f82e | blueswir1 | espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq], |
644 | ee76f82e | blueswir1 | iommu, &espdma_irq, &esp_reset); |
645 | ee76f82e | blueswir1 | |
646 | ee76f82e | blueswir1 | ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
|
647 | ee76f82e | blueswir1 | slavio_irq[hwdef->le_irq], iommu, &ledma_irq, |
648 | ee76f82e | blueswir1 | &le_reset); |
649 | ee76f82e | blueswir1 | |
650 | ee76f82e | blueswir1 | if (graphic_depth != 8 && graphic_depth != 24) { |
651 | ee76f82e | blueswir1 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
652 | ee76f82e | blueswir1 | exit (1);
|
653 | ee76f82e | blueswir1 | } |
654 | ee76f82e | blueswir1 | tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size, |
655 | ee76f82e | blueswir1 | hwdef->vram_size, graphic_width, graphic_height, graphic_depth); |
656 | ee76f82e | blueswir1 | |
657 | ee76f82e | blueswir1 | if (nd_table[0].model == NULL |
658 | ee76f82e | blueswir1 | || strcmp(nd_table[0].model, "lance") == 0) { |
659 | ee76f82e | blueswir1 | lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
|
660 | ee76f82e | blueswir1 | } else if (strcmp(nd_table[0].model, "?") == 0) { |
661 | ee76f82e | blueswir1 | fprintf(stderr, "qemu: Supported NICs: lance\n");
|
662 | ee76f82e | blueswir1 | exit (1);
|
663 | ee76f82e | blueswir1 | } else {
|
664 | ee76f82e | blueswir1 | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
665 | ee76f82e | blueswir1 | exit (1);
|
666 | ee76f82e | blueswir1 | } |
667 | ee76f82e | blueswir1 | |
668 | ee76f82e | blueswir1 | nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, |
669 | 4aed2c33 | blueswir1 | hwdef->nvram_size, 2);
|
670 | ee76f82e | blueswir1 | |
671 | ee76f82e | blueswir1 | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq], |
672 | ee76f82e | blueswir1 | nographic); |
673 | ee76f82e | blueswir1 | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
674 | ee76f82e | blueswir1 | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
675 | ee76f82e | blueswir1 | slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], |
676 | ee76f82e | blueswir1 | serial_hds[1], serial_hds[0]); |
677 | ee76f82e | blueswir1 | |
678 | 2be17ebd | blueswir1 | slavio_misc = slavio_misc_init(-1, hwdef->apc_base,
|
679 | 2be17ebd | blueswir1 | hwdef->aux1_base, hwdef->aux2_base, |
680 | 2be17ebd | blueswir1 | slavio_irq[hwdef->me_irq], env, &fdc_tc); |
681 | 2be17ebd | blueswir1 | |
682 | ee76f82e | blueswir1 | if (hwdef->fd_base != (target_phys_addr_t)-1) { |
683 | ee76f82e | blueswir1 | /* there is zero or one floppy drive */
|
684 | ee76f82e | blueswir1 | fd[1] = fd[0] = NULL; |
685 | 22548760 | blueswir1 | drive_index = drive_get_index(IF_FLOPPY, 0, 0); |
686 | 22548760 | blueswir1 | if (drive_index != -1) |
687 | 22548760 | blueswir1 | fd[0] = drives_table[drive_index].bdrv;
|
688 | ee76f82e | blueswir1 | |
689 | 2be17ebd | blueswir1 | sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd, |
690 | 2be17ebd | blueswir1 | fdc_tc); |
691 | ee76f82e | blueswir1 | } |
692 | ee76f82e | blueswir1 | |
693 | ee76f82e | blueswir1 | if (drive_get_max_bus(IF_SCSI) > 0) { |
694 | ee76f82e | blueswir1 | fprintf(stderr, "qemu: too many SCSI bus\n");
|
695 | ee76f82e | blueswir1 | exit(1);
|
696 | ee76f82e | blueswir1 | } |
697 | ee76f82e | blueswir1 | |
698 | 5d20fa6b | blueswir1 | main_esp = esp_init(hwdef->esp_base, 2,
|
699 | 8b17de88 | blueswir1 | espdma_memory_read, espdma_memory_write, |
700 | 8b17de88 | blueswir1 | espdma, *espdma_irq, esp_reset); |
701 | ee76f82e | blueswir1 | |
702 | ee76f82e | blueswir1 | for (i = 0; i < ESP_MAX_DEVS; i++) { |
703 | 22548760 | blueswir1 | drive_index = drive_get_index(IF_SCSI, 0, i);
|
704 | 22548760 | blueswir1 | if (drive_index == -1) |
705 | ee76f82e | blueswir1 | continue;
|
706 | 22548760 | blueswir1 | esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i); |
707 | ee76f82e | blueswir1 | } |
708 | ee76f82e | blueswir1 | |
709 | 293f78bc | blueswir1 | kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
710 | 293f78bc | blueswir1 | RAM_size); |
711 | ee76f82e | blueswir1 | |
712 | ee76f82e | blueswir1 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
713 | ee76f82e | blueswir1 | boot_device, RAM_size, kernel_size, graphic_width, |
714 | ee76f82e | blueswir1 | graphic_height, graphic_depth, hwdef->machine_id, "Sun4c");
|
715 | ee76f82e | blueswir1 | } |
716 | ee76f82e | blueswir1 | |
717 | 36cd9210 | blueswir1 | static const struct hwdef hwdefs[] = { |
718 | 36cd9210 | blueswir1 | /* SS-5 */
|
719 | 36cd9210 | blueswir1 | { |
720 | 36cd9210 | blueswir1 | .iommu_base = 0x10000000,
|
721 | 36cd9210 | blueswir1 | .tcx_base = 0x50000000,
|
722 | 36cd9210 | blueswir1 | .cs_base = 0x6c000000,
|
723 | 384ccb5d | blueswir1 | .slavio_base = 0x70000000,
|
724 | 36cd9210 | blueswir1 | .ms_kb_base = 0x71000000,
|
725 | 36cd9210 | blueswir1 | .serial_base = 0x71100000,
|
726 | 36cd9210 | blueswir1 | .nvram_base = 0x71200000,
|
727 | 36cd9210 | blueswir1 | .fd_base = 0x71400000,
|
728 | 36cd9210 | blueswir1 | .counter_base = 0x71d00000,
|
729 | 36cd9210 | blueswir1 | .intctl_base = 0x71e00000,
|
730 | 4c2485de | blueswir1 | .idreg_base = 0x78000000,
|
731 | 36cd9210 | blueswir1 | .dma_base = 0x78400000,
|
732 | 36cd9210 | blueswir1 | .esp_base = 0x78800000,
|
733 | 36cd9210 | blueswir1 | .le_base = 0x78c00000,
|
734 | 127fc407 | blueswir1 | .apc_base = 0x6a000000,
|
735 | 0019ad53 | blueswir1 | .aux1_base = 0x71900000,
|
736 | 0019ad53 | blueswir1 | .aux2_base = 0x71910000,
|
737 | 7eb0c8e8 | blueswir1 | .ecc_base = -1,
|
738 | ee76f82e | blueswir1 | .sun4c_intctl_base = -1,
|
739 | ee76f82e | blueswir1 | .sun4c_counter_base = -1,
|
740 | 36cd9210 | blueswir1 | .vram_size = 0x00100000,
|
741 | 36cd9210 | blueswir1 | .nvram_size = 0x2000,
|
742 | 36cd9210 | blueswir1 | .esp_irq = 18,
|
743 | 36cd9210 | blueswir1 | .le_irq = 16,
|
744 | e3a79bca | blueswir1 | .clock_irq = 7,
|
745 | 36cd9210 | blueswir1 | .clock1_irq = 19,
|
746 | 36cd9210 | blueswir1 | .ms_kb_irq = 14,
|
747 | 36cd9210 | blueswir1 | .ser_irq = 15,
|
748 | 36cd9210 | blueswir1 | .fd_irq = 22,
|
749 | 36cd9210 | blueswir1 | .me_irq = 30,
|
750 | 36cd9210 | blueswir1 | .cs_irq = 5,
|
751 | 36cd9210 | blueswir1 | .machine_id = 0x80,
|
752 | cf3102ac | blueswir1 | .iommu_version = 0x05000000,
|
753 | e0353fe2 | blueswir1 | .intbit_to_level = { |
754 | f930d07e | blueswir1 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
755 | f930d07e | blueswir1 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
756 | e0353fe2 | blueswir1 | }, |
757 | 3ebf5aaf | blueswir1 | .max_mem = 0x10000000,
|
758 | 3ebf5aaf | blueswir1 | .default_cpu_model = "Fujitsu MB86904",
|
759 | e0353fe2 | blueswir1 | }, |
760 | e0353fe2 | blueswir1 | /* SS-10 */
|
761 | e0353fe2 | blueswir1 | { |
762 | 5dcb6b91 | blueswir1 | .iommu_base = 0xfe0000000ULL,
|
763 | 5dcb6b91 | blueswir1 | .tcx_base = 0xe20000000ULL,
|
764 | 803b3c7b | blueswir1 | .cs_base = -1,
|
765 | 5dcb6b91 | blueswir1 | .slavio_base = 0xff0000000ULL,
|
766 | 5dcb6b91 | blueswir1 | .ms_kb_base = 0xff1000000ULL,
|
767 | 5dcb6b91 | blueswir1 | .serial_base = 0xff1100000ULL,
|
768 | 5dcb6b91 | blueswir1 | .nvram_base = 0xff1200000ULL,
|
769 | 5dcb6b91 | blueswir1 | .fd_base = 0xff1700000ULL,
|
770 | 5dcb6b91 | blueswir1 | .counter_base = 0xff1300000ULL,
|
771 | 5dcb6b91 | blueswir1 | .intctl_base = 0xff1400000ULL,
|
772 | 4c2485de | blueswir1 | .idreg_base = 0xef0000000ULL,
|
773 | 5dcb6b91 | blueswir1 | .dma_base = 0xef0400000ULL,
|
774 | 5dcb6b91 | blueswir1 | .esp_base = 0xef0800000ULL,
|
775 | 5dcb6b91 | blueswir1 | .le_base = 0xef0c00000ULL,
|
776 | 0019ad53 | blueswir1 | .apc_base = 0xefa000000ULL, // XXX should not exist |
777 | 127fc407 | blueswir1 | .aux1_base = 0xff1800000ULL,
|
778 | 127fc407 | blueswir1 | .aux2_base = 0xff1a01000ULL,
|
779 | 7eb0c8e8 | blueswir1 | .ecc_base = 0xf00000000ULL,
|
780 | 7eb0c8e8 | blueswir1 | .ecc_version = 0x10000000, // version 0, implementation 1 |
781 | ee76f82e | blueswir1 | .sun4c_intctl_base = -1,
|
782 | ee76f82e | blueswir1 | .sun4c_counter_base = -1,
|
783 | e0353fe2 | blueswir1 | .vram_size = 0x00100000,
|
784 | e0353fe2 | blueswir1 | .nvram_size = 0x2000,
|
785 | e0353fe2 | blueswir1 | .esp_irq = 18,
|
786 | e0353fe2 | blueswir1 | .le_irq = 16,
|
787 | e3a79bca | blueswir1 | .clock_irq = 7,
|
788 | e0353fe2 | blueswir1 | .clock1_irq = 19,
|
789 | e0353fe2 | blueswir1 | .ms_kb_irq = 14,
|
790 | e0353fe2 | blueswir1 | .ser_irq = 15,
|
791 | e0353fe2 | blueswir1 | .fd_irq = 22,
|
792 | e0353fe2 | blueswir1 | .me_irq = 30,
|
793 | 803b3c7b | blueswir1 | .cs_irq = -1,
|
794 | e42c20b4 | blueswir1 | .ecc_irq = 28,
|
795 | 803b3c7b | blueswir1 | .machine_id = 0x72,
|
796 | 7fbfb139 | blueswir1 | .iommu_version = 0x03000000,
|
797 | e0353fe2 | blueswir1 | .intbit_to_level = { |
798 | f930d07e | blueswir1 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
799 | f930d07e | blueswir1 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
800 | e0353fe2 | blueswir1 | }, |
801 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
802 | 3ebf5aaf | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
803 | 36cd9210 | blueswir1 | }, |
804 | 6a3b9cc9 | blueswir1 | /* SS-600MP */
|
805 | 6a3b9cc9 | blueswir1 | { |
806 | 6a3b9cc9 | blueswir1 | .iommu_base = 0xfe0000000ULL,
|
807 | 6a3b9cc9 | blueswir1 | .tcx_base = 0xe20000000ULL,
|
808 | 6a3b9cc9 | blueswir1 | .cs_base = -1,
|
809 | 6a3b9cc9 | blueswir1 | .slavio_base = 0xff0000000ULL,
|
810 | 6a3b9cc9 | blueswir1 | .ms_kb_base = 0xff1000000ULL,
|
811 | 6a3b9cc9 | blueswir1 | .serial_base = 0xff1100000ULL,
|
812 | 6a3b9cc9 | blueswir1 | .nvram_base = 0xff1200000ULL,
|
813 | 6a3b9cc9 | blueswir1 | .fd_base = -1,
|
814 | 6a3b9cc9 | blueswir1 | .counter_base = 0xff1300000ULL,
|
815 | 6a3b9cc9 | blueswir1 | .intctl_base = 0xff1400000ULL,
|
816 | 4c2485de | blueswir1 | .idreg_base = -1,
|
817 | 6a3b9cc9 | blueswir1 | .dma_base = 0xef0081000ULL,
|
818 | 6a3b9cc9 | blueswir1 | .esp_base = 0xef0080000ULL,
|
819 | 6a3b9cc9 | blueswir1 | .le_base = 0xef0060000ULL,
|
820 | 0019ad53 | blueswir1 | .apc_base = 0xefa000000ULL, // XXX should not exist |
821 | 127fc407 | blueswir1 | .aux1_base = 0xff1800000ULL,
|
822 | 127fc407 | blueswir1 | .aux2_base = 0xff1a01000ULL, // XXX should not exist |
823 | 7eb0c8e8 | blueswir1 | .ecc_base = 0xf00000000ULL,
|
824 | 7eb0c8e8 | blueswir1 | .ecc_version = 0x00000000, // version 0, implementation 0 |
825 | ee76f82e | blueswir1 | .sun4c_intctl_base = -1,
|
826 | ee76f82e | blueswir1 | .sun4c_counter_base = -1,
|
827 | 6a3b9cc9 | blueswir1 | .vram_size = 0x00100000,
|
828 | 6a3b9cc9 | blueswir1 | .nvram_size = 0x2000,
|
829 | 6a3b9cc9 | blueswir1 | .esp_irq = 18,
|
830 | 6a3b9cc9 | blueswir1 | .le_irq = 16,
|
831 | e3a79bca | blueswir1 | .clock_irq = 7,
|
832 | 6a3b9cc9 | blueswir1 | .clock1_irq = 19,
|
833 | 6a3b9cc9 | blueswir1 | .ms_kb_irq = 14,
|
834 | 6a3b9cc9 | blueswir1 | .ser_irq = 15,
|
835 | 6a3b9cc9 | blueswir1 | .fd_irq = 22,
|
836 | 6a3b9cc9 | blueswir1 | .me_irq = 30,
|
837 | 6a3b9cc9 | blueswir1 | .cs_irq = -1,
|
838 | e42c20b4 | blueswir1 | .ecc_irq = 28,
|
839 | 6a3b9cc9 | blueswir1 | .machine_id = 0x71,
|
840 | 7fbfb139 | blueswir1 | .iommu_version = 0x01000000,
|
841 | 6a3b9cc9 | blueswir1 | .intbit_to_level = { |
842 | 6a3b9cc9 | blueswir1 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
843 | 6a3b9cc9 | blueswir1 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
844 | 6a3b9cc9 | blueswir1 | }, |
845 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
846 | 3ebf5aaf | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
847 | 6a3b9cc9 | blueswir1 | }, |
848 | ae40972f | blueswir1 | /* SS-20 */
|
849 | ae40972f | blueswir1 | { |
850 | ae40972f | blueswir1 | .iommu_base = 0xfe0000000ULL,
|
851 | ae40972f | blueswir1 | .tcx_base = 0xe20000000ULL,
|
852 | ae40972f | blueswir1 | .cs_base = -1,
|
853 | ae40972f | blueswir1 | .slavio_base = 0xff0000000ULL,
|
854 | ae40972f | blueswir1 | .ms_kb_base = 0xff1000000ULL,
|
855 | ae40972f | blueswir1 | .serial_base = 0xff1100000ULL,
|
856 | ae40972f | blueswir1 | .nvram_base = 0xff1200000ULL,
|
857 | ae40972f | blueswir1 | .fd_base = 0xff1700000ULL,
|
858 | ae40972f | blueswir1 | .counter_base = 0xff1300000ULL,
|
859 | ae40972f | blueswir1 | .intctl_base = 0xff1400000ULL,
|
860 | 4c2485de | blueswir1 | .idreg_base = 0xef0000000ULL,
|
861 | ae40972f | blueswir1 | .dma_base = 0xef0400000ULL,
|
862 | ae40972f | blueswir1 | .esp_base = 0xef0800000ULL,
|
863 | ae40972f | blueswir1 | .le_base = 0xef0c00000ULL,
|
864 | 0019ad53 | blueswir1 | .apc_base = 0xefa000000ULL, // XXX should not exist |
865 | 577d8dd4 | blueswir1 | .aux1_base = 0xff1800000ULL,
|
866 | 577d8dd4 | blueswir1 | .aux2_base = 0xff1a01000ULL,
|
867 | ae40972f | blueswir1 | .ecc_base = 0xf00000000ULL,
|
868 | ae40972f | blueswir1 | .ecc_version = 0x20000000, // version 0, implementation 2 |
869 | ee76f82e | blueswir1 | .sun4c_intctl_base = -1,
|
870 | ee76f82e | blueswir1 | .sun4c_counter_base = -1,
|
871 | ae40972f | blueswir1 | .vram_size = 0x00100000,
|
872 | ae40972f | blueswir1 | .nvram_size = 0x2000,
|
873 | ae40972f | blueswir1 | .esp_irq = 18,
|
874 | ae40972f | blueswir1 | .le_irq = 16,
|
875 | e3a79bca | blueswir1 | .clock_irq = 7,
|
876 | ae40972f | blueswir1 | .clock1_irq = 19,
|
877 | ae40972f | blueswir1 | .ms_kb_irq = 14,
|
878 | ae40972f | blueswir1 | .ser_irq = 15,
|
879 | ae40972f | blueswir1 | .fd_irq = 22,
|
880 | ae40972f | blueswir1 | .me_irq = 30,
|
881 | ae40972f | blueswir1 | .cs_irq = -1,
|
882 | e42c20b4 | blueswir1 | .ecc_irq = 28,
|
883 | ae40972f | blueswir1 | .machine_id = 0x72,
|
884 | ae40972f | blueswir1 | .iommu_version = 0x13000000,
|
885 | ae40972f | blueswir1 | .intbit_to_level = { |
886 | ae40972f | blueswir1 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
887 | ae40972f | blueswir1 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
888 | ae40972f | blueswir1 | }, |
889 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
890 | ae40972f | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
891 | ae40972f | blueswir1 | }, |
892 | ee76f82e | blueswir1 | /* SS-2 */
|
893 | ee76f82e | blueswir1 | { |
894 | ee76f82e | blueswir1 | .iommu_base = 0xf8000000,
|
895 | ee76f82e | blueswir1 | .tcx_base = 0xfe000000,
|
896 | ee76f82e | blueswir1 | .cs_base = -1,
|
897 | ee76f82e | blueswir1 | .slavio_base = 0xf6000000,
|
898 | ee76f82e | blueswir1 | .ms_kb_base = 0xf0000000,
|
899 | ee76f82e | blueswir1 | .serial_base = 0xf1000000,
|
900 | ee76f82e | blueswir1 | .nvram_base = 0xf2000000,
|
901 | ee76f82e | blueswir1 | .fd_base = 0xf7200000,
|
902 | ee76f82e | blueswir1 | .counter_base = -1,
|
903 | ee76f82e | blueswir1 | .intctl_base = -1,
|
904 | ee76f82e | blueswir1 | .dma_base = 0xf8400000,
|
905 | ee76f82e | blueswir1 | .esp_base = 0xf8800000,
|
906 | ee76f82e | blueswir1 | .le_base = 0xf8c00000,
|
907 | 0019ad53 | blueswir1 | .apc_base = -1,
|
908 | 0019ad53 | blueswir1 | .aux1_base = 0xf7400003,
|
909 | 0019ad53 | blueswir1 | .aux2_base = -1,
|
910 | ee76f82e | blueswir1 | .sun4c_intctl_base = 0xf5000000,
|
911 | ee76f82e | blueswir1 | .sun4c_counter_base = 0xf3000000,
|
912 | ee76f82e | blueswir1 | .vram_size = 0x00100000,
|
913 | 4aed2c33 | blueswir1 | .nvram_size = 0x800,
|
914 | ee76f82e | blueswir1 | .esp_irq = 2,
|
915 | ee76f82e | blueswir1 | .le_irq = 3,
|
916 | ee76f82e | blueswir1 | .clock_irq = 5,
|
917 | ee76f82e | blueswir1 | .clock1_irq = 7,
|
918 | ee76f82e | blueswir1 | .ms_kb_irq = 1,
|
919 | ee76f82e | blueswir1 | .ser_irq = 1,
|
920 | ee76f82e | blueswir1 | .fd_irq = 1,
|
921 | ee76f82e | blueswir1 | .me_irq = 1,
|
922 | ee76f82e | blueswir1 | .cs_irq = -1,
|
923 | ee76f82e | blueswir1 | .machine_id = 0x55,
|
924 | ee76f82e | blueswir1 | .max_mem = 0x10000000,
|
925 | ee76f82e | blueswir1 | .default_cpu_model = "Cypress CY7C601",
|
926 | ee76f82e | blueswir1 | }, |
927 | a526a31c | blueswir1 | /* Voyager */
|
928 | a526a31c | blueswir1 | { |
929 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
930 | a526a31c | blueswir1 | .tcx_base = 0x50000000,
|
931 | a526a31c | blueswir1 | .cs_base = -1,
|
932 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
933 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
934 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
935 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
936 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
937 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
938 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
939 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
940 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
941 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
942 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
943 | a526a31c | blueswir1 | .apc_base = 0x71300000, // pmc |
944 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
945 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
946 | a526a31c | blueswir1 | .ecc_base = -1,
|
947 | a526a31c | blueswir1 | .sun4c_intctl_base = -1,
|
948 | a526a31c | blueswir1 | .sun4c_counter_base = -1,
|
949 | a526a31c | blueswir1 | .vram_size = 0x00100000,
|
950 | a526a31c | blueswir1 | .nvram_size = 0x2000,
|
951 | a526a31c | blueswir1 | .esp_irq = 18,
|
952 | a526a31c | blueswir1 | .le_irq = 16,
|
953 | a526a31c | blueswir1 | .clock_irq = 7,
|
954 | a526a31c | blueswir1 | .clock1_irq = 19,
|
955 | a526a31c | blueswir1 | .ms_kb_irq = 14,
|
956 | a526a31c | blueswir1 | .ser_irq = 15,
|
957 | a526a31c | blueswir1 | .fd_irq = 22,
|
958 | a526a31c | blueswir1 | .me_irq = 30,
|
959 | a526a31c | blueswir1 | .cs_irq = -1,
|
960 | a526a31c | blueswir1 | .machine_id = 0x80,
|
961 | a526a31c | blueswir1 | .iommu_version = 0x05000000,
|
962 | a526a31c | blueswir1 | .intbit_to_level = { |
963 | a526a31c | blueswir1 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
964 | a526a31c | blueswir1 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
965 | a526a31c | blueswir1 | }, |
966 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
967 | a526a31c | blueswir1 | .default_cpu_model = "Fujitsu MB86904",
|
968 | a526a31c | blueswir1 | }, |
969 | a526a31c | blueswir1 | /* LX */
|
970 | a526a31c | blueswir1 | { |
971 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
972 | a526a31c | blueswir1 | .tcx_base = 0x50000000,
|
973 | a526a31c | blueswir1 | .cs_base = -1,
|
974 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
975 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
976 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
977 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
978 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
979 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
980 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
981 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
982 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
983 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
984 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
985 | a526a31c | blueswir1 | .apc_base = -1,
|
986 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
987 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
988 | a526a31c | blueswir1 | .ecc_base = -1,
|
989 | a526a31c | blueswir1 | .sun4c_intctl_base = -1,
|
990 | a526a31c | blueswir1 | .sun4c_counter_base = -1,
|
991 | a526a31c | blueswir1 | .vram_size = 0x00100000,
|
992 | a526a31c | blueswir1 | .nvram_size = 0x2000,
|
993 | a526a31c | blueswir1 | .esp_irq = 18,
|
994 | a526a31c | blueswir1 | .le_irq = 16,
|
995 | a526a31c | blueswir1 | .clock_irq = 7,
|
996 | a526a31c | blueswir1 | .clock1_irq = 19,
|
997 | a526a31c | blueswir1 | .ms_kb_irq = 14,
|
998 | a526a31c | blueswir1 | .ser_irq = 15,
|
999 | a526a31c | blueswir1 | .fd_irq = 22,
|
1000 | a526a31c | blueswir1 | .me_irq = 30,
|
1001 | a526a31c | blueswir1 | .cs_irq = -1,
|
1002 | a526a31c | blueswir1 | .machine_id = 0x80,
|
1003 | a526a31c | blueswir1 | .iommu_version = 0x04000000,
|
1004 | a526a31c | blueswir1 | .intbit_to_level = { |
1005 | a526a31c | blueswir1 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
1006 | a526a31c | blueswir1 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
1007 | a526a31c | blueswir1 | }, |
1008 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
1009 | a526a31c | blueswir1 | .default_cpu_model = "TI MicroSparc I",
|
1010 | a526a31c | blueswir1 | }, |
1011 | a526a31c | blueswir1 | /* SS-4 */
|
1012 | a526a31c | blueswir1 | { |
1013 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
1014 | a526a31c | blueswir1 | .tcx_base = 0x50000000,
|
1015 | a526a31c | blueswir1 | .cs_base = 0x6c000000,
|
1016 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
1017 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
1018 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
1019 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
1020 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
1021 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
1022 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
1023 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
1024 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
1025 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
1026 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
1027 | a526a31c | blueswir1 | .apc_base = 0x6a000000,
|
1028 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
1029 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
1030 | a526a31c | blueswir1 | .ecc_base = -1,
|
1031 | a526a31c | blueswir1 | .sun4c_intctl_base = -1,
|
1032 | a526a31c | blueswir1 | .sun4c_counter_base = -1,
|
1033 | a526a31c | blueswir1 | .vram_size = 0x00100000,
|
1034 | a526a31c | blueswir1 | .nvram_size = 0x2000,
|
1035 | a526a31c | blueswir1 | .esp_irq = 18,
|
1036 | a526a31c | blueswir1 | .le_irq = 16,
|
1037 | a526a31c | blueswir1 | .clock_irq = 7,
|
1038 | a526a31c | blueswir1 | .clock1_irq = 19,
|
1039 | a526a31c | blueswir1 | .ms_kb_irq = 14,
|
1040 | a526a31c | blueswir1 | .ser_irq = 15,
|
1041 | a526a31c | blueswir1 | .fd_irq = 22,
|
1042 | a526a31c | blueswir1 | .me_irq = 30,
|
1043 | a526a31c | blueswir1 | .cs_irq = 5,
|
1044 | a526a31c | blueswir1 | .machine_id = 0x80,
|
1045 | a526a31c | blueswir1 | .iommu_version = 0x05000000,
|
1046 | a526a31c | blueswir1 | .intbit_to_level = { |
1047 | a526a31c | blueswir1 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
1048 | a526a31c | blueswir1 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
1049 | a526a31c | blueswir1 | }, |
1050 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
1051 | a526a31c | blueswir1 | .default_cpu_model = "Fujitsu MB86904",
|
1052 | a526a31c | blueswir1 | }, |
1053 | a526a31c | blueswir1 | /* SPARCClassic */
|
1054 | a526a31c | blueswir1 | { |
1055 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
1056 | a526a31c | blueswir1 | .tcx_base = 0x50000000,
|
1057 | a526a31c | blueswir1 | .cs_base = -1,
|
1058 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
1059 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
1060 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
1061 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
1062 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
1063 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
1064 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
1065 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
1066 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
1067 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
1068 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
1069 | a526a31c | blueswir1 | .apc_base = 0x6a000000,
|
1070 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
1071 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
1072 | a526a31c | blueswir1 | .ecc_base = -1,
|
1073 | a526a31c | blueswir1 | .sun4c_intctl_base = -1,
|
1074 | a526a31c | blueswir1 | .sun4c_counter_base = -1,
|
1075 | a526a31c | blueswir1 | .vram_size = 0x00100000,
|
1076 | a526a31c | blueswir1 | .nvram_size = 0x2000,
|
1077 | a526a31c | blueswir1 | .esp_irq = 18,
|
1078 | a526a31c | blueswir1 | .le_irq = 16,
|
1079 | a526a31c | blueswir1 | .clock_irq = 7,
|
1080 | a526a31c | blueswir1 | .clock1_irq = 19,
|
1081 | a526a31c | blueswir1 | .ms_kb_irq = 14,
|
1082 | a526a31c | blueswir1 | .ser_irq = 15,
|
1083 | a526a31c | blueswir1 | .fd_irq = 22,
|
1084 | a526a31c | blueswir1 | .me_irq = 30,
|
1085 | a526a31c | blueswir1 | .cs_irq = -1,
|
1086 | a526a31c | blueswir1 | .machine_id = 0x80,
|
1087 | a526a31c | blueswir1 | .iommu_version = 0x05000000,
|
1088 | a526a31c | blueswir1 | .intbit_to_level = { |
1089 | a526a31c | blueswir1 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
1090 | a526a31c | blueswir1 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
1091 | a526a31c | blueswir1 | }, |
1092 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
1093 | a526a31c | blueswir1 | .default_cpu_model = "TI MicroSparc I",
|
1094 | a526a31c | blueswir1 | }, |
1095 | a526a31c | blueswir1 | /* SPARCbook */
|
1096 | a526a31c | blueswir1 | { |
1097 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
1098 | a526a31c | blueswir1 | .tcx_base = 0x50000000, // XXX |
1099 | a526a31c | blueswir1 | .cs_base = -1,
|
1100 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
1101 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
1102 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
1103 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
1104 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
1105 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
1106 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
1107 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
1108 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
1109 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
1110 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
1111 | a526a31c | blueswir1 | .apc_base = 0x6a000000,
|
1112 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
1113 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
1114 | a526a31c | blueswir1 | .ecc_base = -1,
|
1115 | a526a31c | blueswir1 | .sun4c_intctl_base = -1,
|
1116 | a526a31c | blueswir1 | .sun4c_counter_base = -1,
|
1117 | a526a31c | blueswir1 | .vram_size = 0x00100000,
|
1118 | a526a31c | blueswir1 | .nvram_size = 0x2000,
|
1119 | a526a31c | blueswir1 | .esp_irq = 18,
|
1120 | a526a31c | blueswir1 | .le_irq = 16,
|
1121 | a526a31c | blueswir1 | .clock_irq = 7,
|
1122 | a526a31c | blueswir1 | .clock1_irq = 19,
|
1123 | a526a31c | blueswir1 | .ms_kb_irq = 14,
|
1124 | a526a31c | blueswir1 | .ser_irq = 15,
|
1125 | a526a31c | blueswir1 | .fd_irq = 22,
|
1126 | a526a31c | blueswir1 | .me_irq = 30,
|
1127 | a526a31c | blueswir1 | .cs_irq = -1,
|
1128 | a526a31c | blueswir1 | .machine_id = 0x80,
|
1129 | a526a31c | blueswir1 | .iommu_version = 0x05000000,
|
1130 | a526a31c | blueswir1 | .intbit_to_level = { |
1131 | a526a31c | blueswir1 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
1132 | a526a31c | blueswir1 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
1133 | a526a31c | blueswir1 | }, |
1134 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
1135 | a526a31c | blueswir1 | .default_cpu_model = "TI MicroSparc I",
|
1136 | a526a31c | blueswir1 | }, |
1137 | 36cd9210 | blueswir1 | }; |
1138 | 36cd9210 | blueswir1 | |
1139 | 36cd9210 | blueswir1 | /* SPARCstation 5 hardware initialisation */
|
1140 | 00f82b8a | aurel32 | static void ss5_init(ram_addr_t RAM_size, int vga_ram_size, |
1141 | b881c2c6 | blueswir1 | const char *boot_device, DisplayState *ds, |
1142 | b881c2c6 | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1143 | b881c2c6 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1144 | 36cd9210 | blueswir1 | { |
1145 | 3ebf5aaf | blueswir1 | sun4m_hw_init(&hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
|
1146 | 3ebf5aaf | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1147 | 420557e8 | bellard | } |
1148 | c0e564d5 | bellard | |
1149 | e0353fe2 | blueswir1 | /* SPARCstation 10 hardware initialisation */
|
1150 | 00f82b8a | aurel32 | static void ss10_init(ram_addr_t RAM_size, int vga_ram_size, |
1151 | b881c2c6 | blueswir1 | const char *boot_device, DisplayState *ds, |
1152 | b881c2c6 | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1153 | b881c2c6 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1154 | e0353fe2 | blueswir1 | { |
1155 | 3ebf5aaf | blueswir1 | sun4m_hw_init(&hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
|
1156 | 3ebf5aaf | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1157 | e0353fe2 | blueswir1 | } |
1158 | e0353fe2 | blueswir1 | |
1159 | 6a3b9cc9 | blueswir1 | /* SPARCserver 600MP hardware initialisation */
|
1160 | 00f82b8a | aurel32 | static void ss600mp_init(ram_addr_t RAM_size, int vga_ram_size, |
1161 | b881c2c6 | blueswir1 | const char *boot_device, DisplayState *ds, |
1162 | 77f193da | blueswir1 | const char *kernel_filename, |
1163 | 77f193da | blueswir1 | const char *kernel_cmdline, |
1164 | 6a3b9cc9 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1165 | 6a3b9cc9 | blueswir1 | { |
1166 | 3ebf5aaf | blueswir1 | sun4m_hw_init(&hwdefs[2], RAM_size, boot_device, ds, kernel_filename,
|
1167 | 3ebf5aaf | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1168 | 6a3b9cc9 | blueswir1 | } |
1169 | 6a3b9cc9 | blueswir1 | |
1170 | ae40972f | blueswir1 | /* SPARCstation 20 hardware initialisation */
|
1171 | 00f82b8a | aurel32 | static void ss20_init(ram_addr_t RAM_size, int vga_ram_size, |
1172 | ae40972f | blueswir1 | const char *boot_device, DisplayState *ds, |
1173 | ae40972f | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1174 | ae40972f | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1175 | ae40972f | blueswir1 | { |
1176 | ae40972f | blueswir1 | sun4m_hw_init(&hwdefs[3], RAM_size, boot_device, ds, kernel_filename,
|
1177 | ae40972f | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1178 | ae40972f | blueswir1 | } |
1179 | ae40972f | blueswir1 | |
1180 | ee76f82e | blueswir1 | /* SPARCstation 2 hardware initialisation */
|
1181 | 00f82b8a | aurel32 | static void ss2_init(ram_addr_t RAM_size, int vga_ram_size, |
1182 | ee76f82e | blueswir1 | const char *boot_device, DisplayState *ds, |
1183 | ee76f82e | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1184 | ee76f82e | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1185 | ee76f82e | blueswir1 | { |
1186 | ee76f82e | blueswir1 | sun4c_hw_init(&hwdefs[4], RAM_size, boot_device, ds, kernel_filename,
|
1187 | ee76f82e | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1188 | ee76f82e | blueswir1 | } |
1189 | ee76f82e | blueswir1 | |
1190 | a526a31c | blueswir1 | /* SPARCstation Voyager hardware initialisation */
|
1191 | 6ef05b95 | blueswir1 | static void vger_init(ram_addr_t RAM_size, int vga_ram_size, |
1192 | a526a31c | blueswir1 | const char *boot_device, DisplayState *ds, |
1193 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1194 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1195 | a526a31c | blueswir1 | { |
1196 | a526a31c | blueswir1 | sun4m_hw_init(&hwdefs[5], RAM_size, boot_device, ds, kernel_filename,
|
1197 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1198 | a526a31c | blueswir1 | } |
1199 | a526a31c | blueswir1 | |
1200 | a526a31c | blueswir1 | /* SPARCstation LX hardware initialisation */
|
1201 | 6ef05b95 | blueswir1 | static void ss_lx_init(ram_addr_t RAM_size, int vga_ram_size, |
1202 | a526a31c | blueswir1 | const char *boot_device, DisplayState *ds, |
1203 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1204 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1205 | a526a31c | blueswir1 | { |
1206 | a526a31c | blueswir1 | sun4m_hw_init(&hwdefs[6], RAM_size, boot_device, ds, kernel_filename,
|
1207 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1208 | a526a31c | blueswir1 | } |
1209 | a526a31c | blueswir1 | |
1210 | a526a31c | blueswir1 | /* SPARCstation 4 hardware initialisation */
|
1211 | 6ef05b95 | blueswir1 | static void ss4_init(ram_addr_t RAM_size, int vga_ram_size, |
1212 | a526a31c | blueswir1 | const char *boot_device, DisplayState *ds, |
1213 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1214 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1215 | a526a31c | blueswir1 | { |
1216 | a526a31c | blueswir1 | sun4m_hw_init(&hwdefs[7], RAM_size, boot_device, ds, kernel_filename,
|
1217 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1218 | a526a31c | blueswir1 | } |
1219 | a526a31c | blueswir1 | |
1220 | a526a31c | blueswir1 | /* SPARCClassic hardware initialisation */
|
1221 | 6ef05b95 | blueswir1 | static void scls_init(ram_addr_t RAM_size, int vga_ram_size, |
1222 | a526a31c | blueswir1 | const char *boot_device, DisplayState *ds, |
1223 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1224 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1225 | a526a31c | blueswir1 | { |
1226 | a526a31c | blueswir1 | sun4m_hw_init(&hwdefs[8], RAM_size, boot_device, ds, kernel_filename,
|
1227 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1228 | a526a31c | blueswir1 | } |
1229 | a526a31c | blueswir1 | |
1230 | a526a31c | blueswir1 | /* SPARCbook hardware initialisation */
|
1231 | 6ef05b95 | blueswir1 | static void sbook_init(ram_addr_t RAM_size, int vga_ram_size, |
1232 | a526a31c | blueswir1 | const char *boot_device, DisplayState *ds, |
1233 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1234 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1235 | a526a31c | blueswir1 | { |
1236 | a526a31c | blueswir1 | sun4m_hw_init(&hwdefs[9], RAM_size, boot_device, ds, kernel_filename,
|
1237 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1238 | a526a31c | blueswir1 | } |
1239 | a526a31c | blueswir1 | |
1240 | 36cd9210 | blueswir1 | QEMUMachine ss5_machine = { |
1241 | 36cd9210 | blueswir1 | "SS-5",
|
1242 | 36cd9210 | blueswir1 | "Sun4m platform, SPARCstation 5",
|
1243 | 36cd9210 | blueswir1 | ss5_init, |
1244 | ac2e9d66 | blueswir1 | PROM_SIZE_MAX + TCX_SIZE, |
1245 | c0e564d5 | bellard | }; |
1246 | e0353fe2 | blueswir1 | |
1247 | e0353fe2 | blueswir1 | QEMUMachine ss10_machine = { |
1248 | e0353fe2 | blueswir1 | "SS-10",
|
1249 | e0353fe2 | blueswir1 | "Sun4m platform, SPARCstation 10",
|
1250 | e0353fe2 | blueswir1 | ss10_init, |
1251 | ac2e9d66 | blueswir1 | PROM_SIZE_MAX + TCX_SIZE, |
1252 | e0353fe2 | blueswir1 | }; |
1253 | 6a3b9cc9 | blueswir1 | |
1254 | 6a3b9cc9 | blueswir1 | QEMUMachine ss600mp_machine = { |
1255 | 6a3b9cc9 | blueswir1 | "SS-600MP",
|
1256 | 6a3b9cc9 | blueswir1 | "Sun4m platform, SPARCserver 600MP",
|
1257 | 6a3b9cc9 | blueswir1 | ss600mp_init, |
1258 | ac2e9d66 | blueswir1 | PROM_SIZE_MAX + TCX_SIZE, |
1259 | 6a3b9cc9 | blueswir1 | }; |
1260 | ae40972f | blueswir1 | |
1261 | ae40972f | blueswir1 | QEMUMachine ss20_machine = { |
1262 | ae40972f | blueswir1 | "SS-20",
|
1263 | ae40972f | blueswir1 | "Sun4m platform, SPARCstation 20",
|
1264 | ae40972f | blueswir1 | ss20_init, |
1265 | ac2e9d66 | blueswir1 | PROM_SIZE_MAX + TCX_SIZE, |
1266 | ae40972f | blueswir1 | }; |
1267 | ae40972f | blueswir1 | |
1268 | ee76f82e | blueswir1 | QEMUMachine ss2_machine = { |
1269 | ee76f82e | blueswir1 | "SS-2",
|
1270 | ee76f82e | blueswir1 | "Sun4c platform, SPARCstation 2",
|
1271 | ee76f82e | blueswir1 | ss2_init, |
1272 | ac2e9d66 | blueswir1 | PROM_SIZE_MAX + TCX_SIZE, |
1273 | ee76f82e | blueswir1 | }; |
1274 | 7d85892b | blueswir1 | |
1275 | a526a31c | blueswir1 | QEMUMachine voyager_machine = { |
1276 | a526a31c | blueswir1 | "Voyager",
|
1277 | a526a31c | blueswir1 | "Sun4m platform, SPARCstation Voyager",
|
1278 | a526a31c | blueswir1 | vger_init, |
1279 | ac2e9d66 | blueswir1 | PROM_SIZE_MAX + TCX_SIZE, |
1280 | a526a31c | blueswir1 | }; |
1281 | a526a31c | blueswir1 | |
1282 | a526a31c | blueswir1 | QEMUMachine ss_lx_machine = { |
1283 | a526a31c | blueswir1 | "LX",
|
1284 | a526a31c | blueswir1 | "Sun4m platform, SPARCstation LX",
|
1285 | a526a31c | blueswir1 | ss_lx_init, |
1286 | ac2e9d66 | blueswir1 | PROM_SIZE_MAX + TCX_SIZE, |
1287 | a526a31c | blueswir1 | }; |
1288 | a526a31c | blueswir1 | |
1289 | a526a31c | blueswir1 | QEMUMachine ss4_machine = { |
1290 | a526a31c | blueswir1 | "SS-4",
|
1291 | a526a31c | blueswir1 | "Sun4m platform, SPARCstation 4",
|
1292 | a526a31c | blueswir1 | ss4_init, |
1293 | ac2e9d66 | blueswir1 | PROM_SIZE_MAX + TCX_SIZE, |
1294 | a526a31c | blueswir1 | }; |
1295 | a526a31c | blueswir1 | |
1296 | a526a31c | blueswir1 | QEMUMachine scls_machine = { |
1297 | a526a31c | blueswir1 | "SPARCClassic",
|
1298 | a526a31c | blueswir1 | "Sun4m platform, SPARCClassic",
|
1299 | a526a31c | blueswir1 | scls_init, |
1300 | ac2e9d66 | blueswir1 | PROM_SIZE_MAX + TCX_SIZE, |
1301 | a526a31c | blueswir1 | }; |
1302 | a526a31c | blueswir1 | |
1303 | a526a31c | blueswir1 | QEMUMachine sbook_machine = { |
1304 | a526a31c | blueswir1 | "SPARCbook",
|
1305 | a526a31c | blueswir1 | "Sun4m platform, SPARCbook",
|
1306 | a526a31c | blueswir1 | sbook_init, |
1307 | ac2e9d66 | blueswir1 | PROM_SIZE_MAX + TCX_SIZE, |
1308 | a526a31c | blueswir1 | }; |
1309 | a526a31c | blueswir1 | |
1310 | 7d85892b | blueswir1 | static const struct sun4d_hwdef sun4d_hwdefs[] = { |
1311 | 7d85892b | blueswir1 | /* SS-1000 */
|
1312 | 7d85892b | blueswir1 | { |
1313 | 7d85892b | blueswir1 | .iounit_bases = { |
1314 | 7d85892b | blueswir1 | 0xfe0200000ULL,
|
1315 | 7d85892b | blueswir1 | 0xfe1200000ULL,
|
1316 | 7d85892b | blueswir1 | 0xfe2200000ULL,
|
1317 | 7d85892b | blueswir1 | 0xfe3200000ULL,
|
1318 | 7d85892b | blueswir1 | -1,
|
1319 | 7d85892b | blueswir1 | }, |
1320 | 7d85892b | blueswir1 | .tcx_base = 0x820000000ULL,
|
1321 | 7d85892b | blueswir1 | .slavio_base = 0xf00000000ULL,
|
1322 | 7d85892b | blueswir1 | .ms_kb_base = 0xf00240000ULL,
|
1323 | 7d85892b | blueswir1 | .serial_base = 0xf00200000ULL,
|
1324 | 7d85892b | blueswir1 | .nvram_base = 0xf00280000ULL,
|
1325 | 7d85892b | blueswir1 | .counter_base = 0xf00300000ULL,
|
1326 | 7d85892b | blueswir1 | .espdma_base = 0x800081000ULL,
|
1327 | 7d85892b | blueswir1 | .esp_base = 0x800080000ULL,
|
1328 | 7d85892b | blueswir1 | .ledma_base = 0x800040000ULL,
|
1329 | 7d85892b | blueswir1 | .le_base = 0x800060000ULL,
|
1330 | 7d85892b | blueswir1 | .sbi_base = 0xf02800000ULL,
|
1331 | c1d00dc0 | blueswir1 | .vram_size = 0x00100000,
|
1332 | 7d85892b | blueswir1 | .nvram_size = 0x2000,
|
1333 | 7d85892b | blueswir1 | .esp_irq = 3,
|
1334 | 7d85892b | blueswir1 | .le_irq = 4,
|
1335 | 7d85892b | blueswir1 | .clock_irq = 14,
|
1336 | 7d85892b | blueswir1 | .clock1_irq = 10,
|
1337 | 7d85892b | blueswir1 | .ms_kb_irq = 12,
|
1338 | 7d85892b | blueswir1 | .ser_irq = 12,
|
1339 | 7d85892b | blueswir1 | .machine_id = 0x80,
|
1340 | 7d85892b | blueswir1 | .iounit_version = 0x03000000,
|
1341 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
1342 | 7d85892b | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
1343 | 7d85892b | blueswir1 | }, |
1344 | 7d85892b | blueswir1 | /* SS-2000 */
|
1345 | 7d85892b | blueswir1 | { |
1346 | 7d85892b | blueswir1 | .iounit_bases = { |
1347 | 7d85892b | blueswir1 | 0xfe0200000ULL,
|
1348 | 7d85892b | blueswir1 | 0xfe1200000ULL,
|
1349 | 7d85892b | blueswir1 | 0xfe2200000ULL,
|
1350 | 7d85892b | blueswir1 | 0xfe3200000ULL,
|
1351 | 7d85892b | blueswir1 | 0xfe4200000ULL,
|
1352 | 7d85892b | blueswir1 | }, |
1353 | 7d85892b | blueswir1 | .tcx_base = 0x820000000ULL,
|
1354 | 7d85892b | blueswir1 | .slavio_base = 0xf00000000ULL,
|
1355 | 7d85892b | blueswir1 | .ms_kb_base = 0xf00240000ULL,
|
1356 | 7d85892b | blueswir1 | .serial_base = 0xf00200000ULL,
|
1357 | 7d85892b | blueswir1 | .nvram_base = 0xf00280000ULL,
|
1358 | 7d85892b | blueswir1 | .counter_base = 0xf00300000ULL,
|
1359 | 7d85892b | blueswir1 | .espdma_base = 0x800081000ULL,
|
1360 | 7d85892b | blueswir1 | .esp_base = 0x800080000ULL,
|
1361 | 7d85892b | blueswir1 | .ledma_base = 0x800040000ULL,
|
1362 | 7d85892b | blueswir1 | .le_base = 0x800060000ULL,
|
1363 | 7d85892b | blueswir1 | .sbi_base = 0xf02800000ULL,
|
1364 | c1d00dc0 | blueswir1 | .vram_size = 0x00100000,
|
1365 | 7d85892b | blueswir1 | .nvram_size = 0x2000,
|
1366 | 7d85892b | blueswir1 | .esp_irq = 3,
|
1367 | 7d85892b | blueswir1 | .le_irq = 4,
|
1368 | 7d85892b | blueswir1 | .clock_irq = 14,
|
1369 | 7d85892b | blueswir1 | .clock1_irq = 10,
|
1370 | 7d85892b | blueswir1 | .ms_kb_irq = 12,
|
1371 | 7d85892b | blueswir1 | .ser_irq = 12,
|
1372 | 7d85892b | blueswir1 | .machine_id = 0x80,
|
1373 | 7d85892b | blueswir1 | .iounit_version = 0x03000000,
|
1374 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
1375 | 7d85892b | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
1376 | 7d85892b | blueswir1 | }, |
1377 | 7d85892b | blueswir1 | }; |
1378 | 7d85892b | blueswir1 | |
1379 | 6ef05b95 | blueswir1 | static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size, |
1380 | 7d85892b | blueswir1 | const char *boot_device, |
1381 | 7d85892b | blueswir1 | DisplayState *ds, const char *kernel_filename, |
1382 | 7d85892b | blueswir1 | const char *kernel_cmdline, |
1383 | 7d85892b | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1384 | 7d85892b | blueswir1 | { |
1385 | 7d85892b | blueswir1 | CPUState *env, *envs[MAX_CPUS]; |
1386 | 7d85892b | blueswir1 | unsigned int i; |
1387 | 7d85892b | blueswir1 | void *iounits[MAX_IOUNITS], *espdma, *ledma, *main_esp, *nvram, *sbi;
|
1388 | 7d85892b | blueswir1 | qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq, |
1389 | 7d85892b | blueswir1 | *espdma_irq, *ledma_irq; |
1390 | 7d85892b | blueswir1 | qemu_irq *esp_reset, *le_reset; |
1391 | 7d85892b | blueswir1 | unsigned long prom_offset, kernel_size; |
1392 | 7d85892b | blueswir1 | int ret;
|
1393 | 7d85892b | blueswir1 | char buf[1024]; |
1394 | 22548760 | blueswir1 | int drive_index;
|
1395 | 7d85892b | blueswir1 | |
1396 | 7d85892b | blueswir1 | /* init CPUs */
|
1397 | 7d85892b | blueswir1 | if (!cpu_model)
|
1398 | 7d85892b | blueswir1 | cpu_model = hwdef->default_cpu_model; |
1399 | 7d85892b | blueswir1 | |
1400 | 7d85892b | blueswir1 | for (i = 0; i < smp_cpus; i++) { |
1401 | 7d85892b | blueswir1 | env = cpu_init(cpu_model); |
1402 | 7d85892b | blueswir1 | if (!env) {
|
1403 | 8e82c6a8 | blueswir1 | fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
|
1404 | 7d85892b | blueswir1 | exit(1);
|
1405 | 7d85892b | blueswir1 | } |
1406 | 7d85892b | blueswir1 | cpu_sparc_set_id(env, i); |
1407 | 7d85892b | blueswir1 | envs[i] = env; |
1408 | 7d85892b | blueswir1 | if (i == 0) { |
1409 | 7d85892b | blueswir1 | qemu_register_reset(main_cpu_reset, env); |
1410 | 7d85892b | blueswir1 | } else {
|
1411 | 7d85892b | blueswir1 | qemu_register_reset(secondary_cpu_reset, env); |
1412 | 7d85892b | blueswir1 | env->halted = 1;
|
1413 | 7d85892b | blueswir1 | } |
1414 | 7d85892b | blueswir1 | cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS); |
1415 | 7d85892b | blueswir1 | env->prom_addr = hwdef->slavio_base; |
1416 | 7d85892b | blueswir1 | } |
1417 | 7d85892b | blueswir1 | |
1418 | 7d85892b | blueswir1 | for (i = smp_cpus; i < MAX_CPUS; i++)
|
1419 | 7d85892b | blueswir1 | cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
|
1420 | 7d85892b | blueswir1 | |
1421 | 7d85892b | blueswir1 | /* allocate RAM */
|
1422 | 7d85892b | blueswir1 | if ((uint64_t)RAM_size > hwdef->max_mem) {
|
1423 | 77f193da | blueswir1 | fprintf(stderr, |
1424 | 77f193da | blueswir1 | "qemu: Too much memory for this machine: %d, maximum %d\n",
|
1425 | 6ef05b95 | blueswir1 | (unsigned int)(RAM_size / (1024 * 1024)), |
1426 | 7d85892b | blueswir1 | (unsigned int)(hwdef->max_mem / (1024 * 1024))); |
1427 | 7d85892b | blueswir1 | exit(1);
|
1428 | 7d85892b | blueswir1 | } |
1429 | 7d85892b | blueswir1 | cpu_register_physical_memory(0, RAM_size, 0); |
1430 | 7d85892b | blueswir1 | |
1431 | 7d85892b | blueswir1 | /* load boot prom */
|
1432 | 7d85892b | blueswir1 | prom_offset = RAM_size + hwdef->vram_size; |
1433 | 7d85892b | blueswir1 | cpu_register_physical_memory(hwdef->slavio_base, |
1434 | 7d85892b | blueswir1 | (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
|
1435 | 7d85892b | blueswir1 | TARGET_PAGE_MASK, |
1436 | 7d85892b | blueswir1 | prom_offset | IO_MEM_ROM); |
1437 | 7d85892b | blueswir1 | |
1438 | 7d85892b | blueswir1 | if (bios_name == NULL) |
1439 | 7d85892b | blueswir1 | bios_name = PROM_FILENAME; |
1440 | 7d85892b | blueswir1 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
1441 | 7d85892b | blueswir1 | ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL); |
1442 | 7d85892b | blueswir1 | if (ret < 0 || ret > PROM_SIZE_MAX) |
1443 | e01f4a1c | blueswir1 | ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX); |
1444 | 7d85892b | blueswir1 | if (ret < 0 || ret > PROM_SIZE_MAX) { |
1445 | 7d85892b | blueswir1 | fprintf(stderr, "qemu: could not load prom '%s'\n",
|
1446 | 7d85892b | blueswir1 | buf); |
1447 | 7d85892b | blueswir1 | exit(1);
|
1448 | 7d85892b | blueswir1 | } |
1449 | 7d85892b | blueswir1 | |
1450 | 7d85892b | blueswir1 | /* set up devices */
|
1451 | 7d85892b | blueswir1 | sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs); |
1452 | 7d85892b | blueswir1 | |
1453 | 7d85892b | blueswir1 | for (i = 0; i < MAX_IOUNITS; i++) |
1454 | 7d85892b | blueswir1 | if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1) |
1455 | ff403da6 | blueswir1 | iounits[i] = iommu_init(hwdef->iounit_bases[i], |
1456 | ff403da6 | blueswir1 | hwdef->iounit_version, |
1457 | ff403da6 | blueswir1 | sbi_irq[hwdef->me_irq]); |
1458 | 7d85892b | blueswir1 | |
1459 | 7d85892b | blueswir1 | espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq], |
1460 | 7d85892b | blueswir1 | iounits[0], &espdma_irq, &esp_reset);
|
1461 | 7d85892b | blueswir1 | |
1462 | 7d85892b | blueswir1 | ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq], |
1463 | 7d85892b | blueswir1 | iounits[0], &ledma_irq, &le_reset);
|
1464 | 7d85892b | blueswir1 | |
1465 | 7d85892b | blueswir1 | if (graphic_depth != 8 && graphic_depth != 24) { |
1466 | 7d85892b | blueswir1 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
1467 | 7d85892b | blueswir1 | exit (1);
|
1468 | 7d85892b | blueswir1 | } |
1469 | 7d85892b | blueswir1 | tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size, |
1470 | 7d85892b | blueswir1 | hwdef->vram_size, graphic_width, graphic_height, graphic_depth); |
1471 | 7d85892b | blueswir1 | |
1472 | 7d85892b | blueswir1 | if (nd_table[0].model == NULL |
1473 | 7d85892b | blueswir1 | || strcmp(nd_table[0].model, "lance") == 0) { |
1474 | 7d85892b | blueswir1 | lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
|
1475 | 7d85892b | blueswir1 | } else if (strcmp(nd_table[0].model, "?") == 0) { |
1476 | 7d85892b | blueswir1 | fprintf(stderr, "qemu: Supported NICs: lance\n");
|
1477 | 7d85892b | blueswir1 | exit (1);
|
1478 | 7d85892b | blueswir1 | } else {
|
1479 | 7d85892b | blueswir1 | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
1480 | 7d85892b | blueswir1 | exit (1);
|
1481 | 7d85892b | blueswir1 | } |
1482 | 7d85892b | blueswir1 | |
1483 | 7d85892b | blueswir1 | nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, |
1484 | 7d85892b | blueswir1 | hwdef->nvram_size, 8);
|
1485 | 7d85892b | blueswir1 | |
1486 | 7d85892b | blueswir1 | slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq], |
1487 | 7d85892b | blueswir1 | sbi_cpu_irq, smp_cpus); |
1488 | 7d85892b | blueswir1 | |
1489 | 7d85892b | blueswir1 | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq], |
1490 | 7d85892b | blueswir1 | nographic); |
1491 | 7d85892b | blueswir1 | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
1492 | 7d85892b | blueswir1 | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
1493 | 7d85892b | blueswir1 | slavio_serial_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq], |
1494 | 7d85892b | blueswir1 | serial_hds[1], serial_hds[0]); |
1495 | 7d85892b | blueswir1 | |
1496 | 7d85892b | blueswir1 | if (drive_get_max_bus(IF_SCSI) > 0) { |
1497 | 7d85892b | blueswir1 | fprintf(stderr, "qemu: too many SCSI bus\n");
|
1498 | 7d85892b | blueswir1 | exit(1);
|
1499 | 7d85892b | blueswir1 | } |
1500 | 7d85892b | blueswir1 | |
1501 | 5d20fa6b | blueswir1 | main_esp = esp_init(hwdef->esp_base, 2,
|
1502 | 8b17de88 | blueswir1 | espdma_memory_read, espdma_memory_write, |
1503 | 8b17de88 | blueswir1 | espdma, *espdma_irq, esp_reset); |
1504 | 7d85892b | blueswir1 | |
1505 | 7d85892b | blueswir1 | for (i = 0; i < ESP_MAX_DEVS; i++) { |
1506 | 22548760 | blueswir1 | drive_index = drive_get_index(IF_SCSI, 0, i);
|
1507 | 22548760 | blueswir1 | if (drive_index == -1) |
1508 | 7d85892b | blueswir1 | continue;
|
1509 | 22548760 | blueswir1 | esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i); |
1510 | 7d85892b | blueswir1 | } |
1511 | 7d85892b | blueswir1 | |
1512 | 293f78bc | blueswir1 | kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
1513 | 293f78bc | blueswir1 | RAM_size); |
1514 | 7d85892b | blueswir1 | |
1515 | 7d85892b | blueswir1 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
1516 | 7d85892b | blueswir1 | boot_device, RAM_size, kernel_size, graphic_width, |
1517 | 7d85892b | blueswir1 | graphic_height, graphic_depth, hwdef->machine_id, "Sun4d");
|
1518 | 7d85892b | blueswir1 | } |
1519 | 7d85892b | blueswir1 | |
1520 | 7d85892b | blueswir1 | /* SPARCserver 1000 hardware initialisation */
|
1521 | 00f82b8a | aurel32 | static void ss1000_init(ram_addr_t RAM_size, int vga_ram_size, |
1522 | 7d85892b | blueswir1 | const char *boot_device, DisplayState *ds, |
1523 | 7d85892b | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1524 | 7d85892b | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1525 | 7d85892b | blueswir1 | { |
1526 | 7d85892b | blueswir1 | sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
|
1527 | 7d85892b | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1528 | 7d85892b | blueswir1 | } |
1529 | 7d85892b | blueswir1 | |
1530 | 7d85892b | blueswir1 | /* SPARCcenter 2000 hardware initialisation */
|
1531 | 00f82b8a | aurel32 | static void ss2000_init(ram_addr_t RAM_size, int vga_ram_size, |
1532 | 7d85892b | blueswir1 | const char *boot_device, DisplayState *ds, |
1533 | 7d85892b | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1534 | 7d85892b | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1535 | 7d85892b | blueswir1 | { |
1536 | 7d85892b | blueswir1 | sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
|
1537 | 7d85892b | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1538 | 7d85892b | blueswir1 | } |
1539 | 7d85892b | blueswir1 | |
1540 | 7d85892b | blueswir1 | QEMUMachine ss1000_machine = { |
1541 | 7d85892b | blueswir1 | "SS-1000",
|
1542 | 7d85892b | blueswir1 | "Sun4d platform, SPARCserver 1000",
|
1543 | 7d85892b | blueswir1 | ss1000_init, |
1544 | ac2e9d66 | blueswir1 | PROM_SIZE_MAX + TCX_SIZE, |
1545 | 7d85892b | blueswir1 | }; |
1546 | 7d85892b | blueswir1 | |
1547 | 7d85892b | blueswir1 | QEMUMachine ss2000_machine = { |
1548 | 7d85892b | blueswir1 | "SS-2000",
|
1549 | 7d85892b | blueswir1 | "Sun4d platform, SPARCcenter 2000",
|
1550 | 7d85892b | blueswir1 | ss2000_init, |
1551 | ac2e9d66 | blueswir1 | PROM_SIZE_MAX + TCX_SIZE, |
1552 | 7d85892b | blueswir1 | }; |