root / cpu-defs.h @ b3ce604e
History | View | Annotate | Download (9.9 kB)
1 | ab93bbe2 | bellard | /*
|
---|---|---|---|
2 | ab93bbe2 | bellard | * common defines for all CPUs
|
3 | 5fafdf24 | ths | *
|
4 | ab93bbe2 | bellard | * Copyright (c) 2003 Fabrice Bellard
|
5 | ab93bbe2 | bellard | *
|
6 | ab93bbe2 | bellard | * This library is free software; you can redistribute it and/or
|
7 | ab93bbe2 | bellard | * modify it under the terms of the GNU Lesser General Public
|
8 | ab93bbe2 | bellard | * License as published by the Free Software Foundation; either
|
9 | ab93bbe2 | bellard | * version 2 of the License, or (at your option) any later version.
|
10 | ab93bbe2 | bellard | *
|
11 | ab93bbe2 | bellard | * This library is distributed in the hope that it will be useful,
|
12 | ab93bbe2 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 | ab93bbe2 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
14 | ab93bbe2 | bellard | * Lesser General Public License for more details.
|
15 | ab93bbe2 | bellard | *
|
16 | ab93bbe2 | bellard | * You should have received a copy of the GNU Lesser General Public
|
17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
18 | ab93bbe2 | bellard | */
|
19 | ab93bbe2 | bellard | #ifndef CPU_DEFS_H
|
20 | ab93bbe2 | bellard | #define CPU_DEFS_H
|
21 | ab93bbe2 | bellard | |
22 | 87ecb68b | pbrook | #ifndef NEED_CPU_H
|
23 | 87ecb68b | pbrook | #error cpu.h included from common code
|
24 | 87ecb68b | pbrook | #endif
|
25 | 87ecb68b | pbrook | |
26 | ab93bbe2 | bellard | #include "config.h" |
27 | ab93bbe2 | bellard | #include <setjmp.h> |
28 | ed1c0bcb | bellard | #include <inttypes.h> |
29 | be214e6c | aurel32 | #include <signal.h> |
30 | ed1c0bcb | bellard | #include "osdep.h" |
31 | 72cf2d4f | Blue Swirl | #include "qemu-queue.h" |
32 | 1ad2134f | Paul Brook | #include "targphys.h" |
33 | ab93bbe2 | bellard | |
34 | 35b66fc4 | bellard | #ifndef TARGET_LONG_BITS
|
35 | 35b66fc4 | bellard | #error TARGET_LONG_BITS must be defined before including this header
|
36 | 35b66fc4 | bellard | #endif
|
37 | 35b66fc4 | bellard | |
38 | 35b66fc4 | bellard | #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8) |
39 | 35b66fc4 | bellard | |
40 | c2e3dee6 | Laurent Vivier | typedef int16_t target_short __attribute__ ((aligned(TARGET_SHORT_ALIGNMENT)));
|
41 | c2e3dee6 | Laurent Vivier | typedef uint16_t target_ushort __attribute__((aligned(TARGET_SHORT_ALIGNMENT)));
|
42 | c2e3dee6 | Laurent Vivier | typedef int32_t target_int __attribute__((aligned(TARGET_INT_ALIGNMENT)));
|
43 | c2e3dee6 | Laurent Vivier | typedef uint32_t target_uint __attribute__((aligned(TARGET_INT_ALIGNMENT)));
|
44 | c2e3dee6 | Laurent Vivier | typedef int64_t target_llong __attribute__((aligned(TARGET_LLONG_ALIGNMENT)));
|
45 | c2e3dee6 | Laurent Vivier | typedef uint64_t target_ullong __attribute__((aligned(TARGET_LLONG_ALIGNMENT)));
|
46 | ab6d960f | bellard | /* target_ulong is the type of a virtual address */
|
47 | 35b66fc4 | bellard | #if TARGET_LONG_SIZE == 4 |
48 | c2e3dee6 | Laurent Vivier | typedef int32_t target_long __attribute__((aligned(TARGET_LONG_ALIGNMENT)));
|
49 | c2e3dee6 | Laurent Vivier | typedef uint32_t target_ulong __attribute__((aligned(TARGET_LONG_ALIGNMENT)));
|
50 | c27004ec | bellard | #define TARGET_FMT_lx "%08x" |
51 | b62b461b | j_mayer | #define TARGET_FMT_ld "%d" |
52 | 71c8b8fd | j_mayer | #define TARGET_FMT_lu "%u" |
53 | 35b66fc4 | bellard | #elif TARGET_LONG_SIZE == 8 |
54 | c2e3dee6 | Laurent Vivier | typedef int64_t target_long __attribute__((aligned(TARGET_LONG_ALIGNMENT)));
|
55 | c2e3dee6 | Laurent Vivier | typedef uint64_t target_ulong __attribute__((aligned(TARGET_LONG_ALIGNMENT)));
|
56 | 26a76461 | bellard | #define TARGET_FMT_lx "%016" PRIx64 |
57 | b62b461b | j_mayer | #define TARGET_FMT_ld "%" PRId64 |
58 | 71c8b8fd | j_mayer | #define TARGET_FMT_lu "%" PRIu64 |
59 | 35b66fc4 | bellard | #else
|
60 | 35b66fc4 | bellard | #error TARGET_LONG_SIZE undefined
|
61 | 35b66fc4 | bellard | #endif
|
62 | 35b66fc4 | bellard | |
63 | 2be0071f | bellard | #define EXCP_INTERRUPT 0x10000 /* async interruption */ |
64 | 2be0071f | bellard | #define EXCP_HLT 0x10001 /* hlt instruction reached */ |
65 | 2be0071f | bellard | #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */ |
66 | 5a1e3cfc | bellard | #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ |
67 | ab93bbe2 | bellard | |
68 | a316d335 | bellard | #define TB_JMP_CACHE_BITS 12 |
69 | a316d335 | bellard | #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) |
70 | a316d335 | bellard | |
71 | b362e5e0 | pbrook | /* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
|
72 | b362e5e0 | pbrook | addresses on the same page. The top bits are the same. This allows
|
73 | b362e5e0 | pbrook | TLB invalidation to quickly clear a subset of the hash table. */
|
74 | b362e5e0 | pbrook | #define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2) |
75 | b362e5e0 | pbrook | #define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS) |
76 | b362e5e0 | pbrook | #define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1) |
77 | b362e5e0 | pbrook | #define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)
|
78 | b362e5e0 | pbrook | |
79 | 20cb400d | Paul Brook | #if !defined(CONFIG_USER_ONLY)
|
80 | 84b7b8e7 | bellard | #define CPU_TLB_BITS 8 |
81 | 84b7b8e7 | bellard | #define CPU_TLB_SIZE (1 << CPU_TLB_BITS) |
82 | ab93bbe2 | bellard | |
83 | 355b1943 | Paul Brook | #if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32 |
84 | d656469f | bellard | #define CPU_TLB_ENTRY_BITS 4 |
85 | d656469f | bellard | #else
|
86 | d656469f | bellard | #define CPU_TLB_ENTRY_BITS 5 |
87 | d656469f | bellard | #endif
|
88 | d656469f | bellard | |
89 | ab93bbe2 | bellard | typedef struct CPUTLBEntry { |
90 | 0f459d16 | pbrook | /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
|
91 | 0f459d16 | pbrook | bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not
|
92 | 0f459d16 | pbrook | go directly to ram.
|
93 | db8d7466 | bellard | bit 3 : indicates that the entry is invalid
|
94 | db8d7466 | bellard | bit 2..0 : zero
|
95 | db8d7466 | bellard | */
|
96 | 5fafdf24 | ths | target_ulong addr_read; |
97 | 5fafdf24 | ths | target_ulong addr_write; |
98 | 5fafdf24 | ths | target_ulong addr_code; |
99 | 355b1943 | Paul Brook | /* Addend to virtual address to get host address. IO accesses
|
100 | ee50add9 | pbrook | use the corresponding iotlb value. */
|
101 | 3b2992e4 | Stefan Weil | uintptr_t addend; |
102 | d656469f | bellard | /* padding to get a power of two size */
|
103 | 3b2992e4 | Stefan Weil | uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) -
|
104 | 3b2992e4 | Stefan Weil | (sizeof(target_ulong) * 3 + |
105 | 3b2992e4 | Stefan Weil | ((-sizeof(target_ulong) * 3) & (sizeof(uintptr_t) - 1)) + |
106 | 3b2992e4 | Stefan Weil | sizeof(uintptr_t))];
|
107 | ab93bbe2 | bellard | } CPUTLBEntry; |
108 | ab93bbe2 | bellard | |
109 | 355b1943 | Paul Brook | extern int CPUTLBEntry_wrong_size[sizeof(CPUTLBEntry) == (1 << CPU_TLB_ENTRY_BITS) ? 1 : -1]; |
110 | 355b1943 | Paul Brook | |
111 | 20cb400d | Paul Brook | #define CPU_COMMON_TLB \
|
112 | 20cb400d | Paul Brook | /* The meaning of the MMU modes is defined in the target code. */ \
|
113 | 20cb400d | Paul Brook | CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ |
114 | 20cb400d | Paul Brook | target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ |
115 | d4c430a8 | Paul Brook | target_ulong tlb_flush_addr; \ |
116 | d4c430a8 | Paul Brook | target_ulong tlb_flush_mask; |
117 | 20cb400d | Paul Brook | |
118 | 20cb400d | Paul Brook | #else
|
119 | 20cb400d | Paul Brook | |
120 | 20cb400d | Paul Brook | #define CPU_COMMON_TLB
|
121 | 20cb400d | Paul Brook | |
122 | 20cb400d | Paul Brook | #endif
|
123 | 20cb400d | Paul Brook | |
124 | 20cb400d | Paul Brook | |
125 | e2542fe2 | Juan Quintela | #ifdef HOST_WORDS_BIGENDIAN
|
126 | 2e70f6ef | pbrook | typedef struct icount_decr_u16 { |
127 | 2e70f6ef | pbrook | uint16_t high; |
128 | 2e70f6ef | pbrook | uint16_t low; |
129 | 2e70f6ef | pbrook | } icount_decr_u16; |
130 | 2e70f6ef | pbrook | #else
|
131 | 2e70f6ef | pbrook | typedef struct icount_decr_u16 { |
132 | 2e70f6ef | pbrook | uint16_t low; |
133 | 2e70f6ef | pbrook | uint16_t high; |
134 | 2e70f6ef | pbrook | } icount_decr_u16; |
135 | 2e70f6ef | pbrook | #endif
|
136 | 2e70f6ef | pbrook | |
137 | 7ba1e619 | aliguori | struct kvm_run;
|
138 | 7ba1e619 | aliguori | struct KVMState;
|
139 | e82bcec2 | Marcelo Tosatti | struct qemu_work_item;
|
140 | 7ba1e619 | aliguori | |
141 | a1d1bb31 | aliguori | typedef struct CPUBreakpoint { |
142 | a1d1bb31 | aliguori | target_ulong pc; |
143 | a1d1bb31 | aliguori | int flags; /* BP_* */ |
144 | 72cf2d4f | Blue Swirl | QTAILQ_ENTRY(CPUBreakpoint) entry; |
145 | a1d1bb31 | aliguori | } CPUBreakpoint; |
146 | a1d1bb31 | aliguori | |
147 | a1d1bb31 | aliguori | typedef struct CPUWatchpoint { |
148 | a1d1bb31 | aliguori | target_ulong vaddr; |
149 | a1d1bb31 | aliguori | target_ulong len_mask; |
150 | a1d1bb31 | aliguori | int flags; /* BP_* */ |
151 | 72cf2d4f | Blue Swirl | QTAILQ_ENTRY(CPUWatchpoint) entry; |
152 | a1d1bb31 | aliguori | } CPUWatchpoint; |
153 | a1d1bb31 | aliguori | |
154 | 1ecf47bf | Paolo Bonzini | #ifdef _WIN32
|
155 | 1ecf47bf | Paolo Bonzini | #define CPU_COMMON_THREAD \
|
156 | 1ecf47bf | Paolo Bonzini | void *hThread;
|
157 | 1ecf47bf | Paolo Bonzini | |
158 | 1ecf47bf | Paolo Bonzini | #else
|
159 | 1ecf47bf | Paolo Bonzini | #define CPU_COMMON_THREAD
|
160 | 1ecf47bf | Paolo Bonzini | #endif
|
161 | 1ecf47bf | Paolo Bonzini | |
162 | a20e31dc | blueswir1 | #define CPU_TEMP_BUF_NLONGS 128 |
163 | a316d335 | bellard | #define CPU_COMMON \
|
164 | a316d335 | bellard | struct TranslationBlock *current_tb; /* currently executing TB */ \ |
165 | a316d335 | bellard | /* soft mmu support */ \
|
166 | 2e70f6ef | pbrook | /* in order to avoid passing too many arguments to the MMIO \
|
167 | 2e70f6ef | pbrook | helpers, we store some rarely used information in the CPU \
|
168 | a316d335 | bellard | context) */ \
|
169 | 20503968 | Blue Swirl | uintptr_t mem_io_pc; /* host pc at which the memory was \
|
170 | 20503968 | Blue Swirl | accessed */ \
|
171 | 2e70f6ef | pbrook | target_ulong mem_io_vaddr; /* target virtual addr at which the \
|
172 | 2e70f6ef | pbrook | memory was accessed */ \
|
173 | 9656f324 | pbrook | uint32_t halted; /* Nonzero if the CPU is in suspend state */ \
|
174 | 9656f324 | pbrook | uint32_t interrupt_request; \ |
175 | be214e6c | aurel32 | volatile sig_atomic_t exit_request; \
|
176 | 20cb400d | Paul Brook | CPU_COMMON_TLB \ |
177 | a316d335 | bellard | struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \
|
178 | a20e31dc | blueswir1 | /* buffer for temporaries in the code generator */ \
|
179 | a20e31dc | blueswir1 | long temp_buf[CPU_TEMP_BUF_NLONGS]; \
|
180 | a316d335 | bellard | \ |
181 | 2e70f6ef | pbrook | int64_t icount_extra; /* Instructions until next timer event. */ \
|
182 | 2e70f6ef | pbrook | /* Number of cycles left, with interrupt flag in high bit. \
|
183 | 2e70f6ef | pbrook | This allows a single read-compare-cbranch-write sequence to test \
|
184 | 2e70f6ef | pbrook | for both decrementer underflow and exceptions. */ \
|
185 | 2e70f6ef | pbrook | union { \
|
186 | 2e70f6ef | pbrook | uint32_t u32; \ |
187 | 2e70f6ef | pbrook | icount_decr_u16 u16; \ |
188 | 2e70f6ef | pbrook | } icount_decr; \ |
189 | 2e70f6ef | pbrook | uint32_t can_do_io; /* nonzero if memory mapped IO is safe. */ \
|
190 | 2e70f6ef | pbrook | \ |
191 | a316d335 | bellard | /* from this point: preserved by CPU reset */ \
|
192 | a316d335 | bellard | /* ice debug support */ \
|
193 | 72cf2d4f | Blue Swirl | QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \ |
194 | a316d335 | bellard | int singlestep_enabled; \
|
195 | a316d335 | bellard | \ |
196 | 72cf2d4f | Blue Swirl | QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \ |
197 | a1d1bb31 | aliguori | CPUWatchpoint *watchpoint_hit; \ |
198 | 56aebc89 | pbrook | \ |
199 | 56aebc89 | pbrook | struct GDBRegisterState *gdb_regs; \
|
200 | 6658ffb8 | pbrook | \ |
201 | 9133e39b | bellard | /* Core interrupt code */ \
|
202 | 9133e39b | bellard | jmp_buf jmp_env; \ |
203 | acb6685f | Anthony Liguori | int exception_index; \
|
204 | 9133e39b | bellard | \ |
205 | 9349b4f9 | Andreas Färber | CPUArchState *next_cpu; /* next CPU sharing TB cache */ \
|
206 | 6a00d601 | bellard | int cpu_index; /* CPU index (informative) */ \ |
207 | 1e9fa730 | Nathan Froyd | uint32_t host_tid; /* host thread ID */ \
|
208 | 268a362c | aliguori | int numa_node; /* NUMA node this cpu is belonging to */ \ |
209 | dc6b1c09 | Andre Przywara | int nr_cores; /* number of cores within this CPU package */ \ |
210 | dc6b1c09 | Andre Przywara | int nr_threads;/* number of threads within this CPU */ \ |
211 | d5975363 | pbrook | int running; /* Nonzero if cpu is currently running(usermode). */ \ |
212 | dc7a09cf | Jan Kiszka | int thread_id; \
|
213 | a316d335 | bellard | /* user data */ \
|
214 | 01ba9816 | ths | void *opaque; \
|
215 | 01ba9816 | ths | \ |
216 | d6dc3d42 | aliguori | uint32_t created; \ |
217 | ced6c051 | Marcelo Tosatti | uint32_t stop; /* Stop request */ \
|
218 | ced6c051 | Marcelo Tosatti | uint32_t stopped; /* Artificially stopped */ \
|
219 | d6dc3d42 | aliguori | struct QemuThread *thread; \
|
220 | 1ecf47bf | Paolo Bonzini | CPU_COMMON_THREAD \ |
221 | d6dc3d42 | aliguori | struct QemuCond *halt_cond; \
|
222 | aa2c364b | Jan Kiszka | int thread_kicked; \
|
223 | e82bcec2 | Marcelo Tosatti | struct qemu_work_item *queued_work_first, *queued_work_last; \
|
224 | 7ba1e619 | aliguori | const char *cpu_model_str; \ |
225 | 7ba1e619 | aliguori | struct KVMState *kvm_state; \
|
226 | 7ba1e619 | aliguori | struct kvm_run *kvm_run; \
|
227 | 9ded2744 | Jan Kiszka | int kvm_fd; \
|
228 | 9ded2744 | Jan Kiszka | int kvm_vcpu_dirty;
|
229 | a316d335 | bellard | |
230 | ab93bbe2 | bellard | #endif |