target-xtensa: switch to AREG0-free mode
Add env parameter to every helper function that needs it, update'configure' script.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-xtensa: add attributes to helper functions
Mark exception generating functions 'noreturn' and pure constantfunctions as such.
target-xtensa: remove unnecessary include of dyngen-exec.h
Signed-off-by: Peter Portante <peter.portante@redhat.com>Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-xtensa: fix CCOUNT for conditional branches
Taken conditional branches fail to update CCOUNT register becauseaccumulated ccount_delta is reset during translation of non-takenbranch. To fix it only update CCOUNT once per conditional branchinstruction translation....
target-xtensa: flush TLB page for new MMU mapping
Both old and new mappings need flushing because their VPN may bedifferent in MMU case.
target-xtensa: update EXCVADDR in case of page table lookup
According to ISA, 4.4.2.6, EXCVADDR may be changed by any TLB miss, evenif the miss is handled entirely by processor hardware.
target-xtensa: extract TLB entry setting method
target-xtensa: update autorefill TLB entries conditionally
This is to avoid interference of internal QEMU helpers(cpu_get_phys_page_debug, tb_invalidate_virtual_addr) with guest-visibleTLB state.
target-xtensa: control page table lookup explicitly
Hardware pagetable walking may not be nested. Stop guessing and passexplicit flag to the get_physical_addr_mmu function that controls pagetable lookup.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>...
build: move other target-*/ objects to nested Makefile.objs
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
build: move libobj-y variable to nested Makefile.objs
build: move obj-TARGET-y variables to nested Makefile.objs
Also drop duplicate occurrence of device-hotplug.o.
Kill off cpu_state_reset()
In commit 1bba0dc932e8826a7d030df3767daf0bc339f9a2 cpu_reset()was renamed to cpu_state_reset(), to allow introducing a new cpu_reset()that would operate on QOM objects.
All callers have been updated except for one in target-mips, so drop all...
target-xtensa: Let cpu_xtensa_init() return XtensaCPU
Make the include paths for cpu-qom.h consistent to allow using XtensaCPUin cpu.h.
Turn cpu_init macro into a static inline function returningCPUXtensaState for backwards compatibility.
Signed-off-by: Andreas Färber <afaerber@suse.de>...
target-xtensa: fix LOOPNEZ/LOOPGTZ translation
Translation of LOOP instructions used to call LEND SR write handler toupdate LEND and invalidate relevant TBs. Now that LEND SR write handlerends TB, LOOPNEZ and LOOPGTZ generate wrong code (same as for simple...
target-xtensa: add license to core-fsf.c
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>Reviewed-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-xtensa: add license to core-dc232b.c
target-xtensa: add dc233c core
This is Diamond 233L Standard Core Rev.C (LE), implemented throughlinux/gdb overlay.
target-xtensa: fix tb invalidation for IBREAK and LOOP
Instruction breakpoint/zero overhead loop handling code is built intoTBs pointed to by IBREAKA/LEND SRs. When these or related SRs getchanged TBs at virtual addresses corresponding to their old and their...
Use uintptr_t for various op related functions
Use uintptr_t instead of void * or unsigned long inseveral op related functions, env->mem_io_pc andGETPC macro.
Reviewed-by: Stefan Weil <sw@weilnetz.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-xtensa: Move helpers.h to helper.h
Provides a file naming scheme consistent with other targets.
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
target-xtensa: QOM'ify CPU
Embed CPUXtensaState as first member of XtensaCPU.Let CPUClass::reset() call cpu_state_reset() for now.
Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
target-xtensa: QOM'ify CPU reset
Move code from cpu_state_reset() into QOM xtensa_cpu_reset().To avoid moving reset_mmu() and dependencies, make it non-static.
target-xtensa: Start QOM'ifying CPU init
Move XtensaConfig-independent code from cpu_xtensa_init() into aQOM initfn, as a start.
Rename CPUState -> CPUArchState
Scripted conversion: for file in .[hc] hw/.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do sed -i "s/CPUState/CPUArchState/g" $file done...
target-xtensa: Don't overuse CPUState
Scripted conversion: sed -i "s/CPUState/CPUXtensaState/g" target-xtensa/*.[hc] sed -i "s/#define CPUXtensaState/#define CPUState/" target-xtensa/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Anthony Liguori <aliguori@us.ibm.com>
Rename cpu_reset() to cpu_state_reset()
Frees the identifier cpu_reset for QOM CPUs (manual rename).
Don't hide the parameter type behind explicit casts, use staticfunctions with strongly typed argument to indirect.
Merge branch 'upstream' of git://qemu.weilnetz.de/qemu
target-xtensa: Clean includes
Remove some include statements which are not needed.
Acked-by: Max Filippov <jcmvbkbc@gmail.com>Signed-off-by: Stefan Weil <sw@weilnetz.de>
target-xtensa: add DBREAK data breakpoints
Add DBREAKA/DBREAKC SRs and implement DBREAK breakpoints as debugwatchpoints.
This implementation is not fully compliant to ISA: when a breakpoint isset to an unmapped/inaccessible memory address it generates TLB/memory...
target-xtensa: add DEBUG_SECTION to overlay tool
Fill debug configuration from overlay definitions in the DEBUG_SECTION.Add DEBUG_SECTION to DC232B and FSF cores.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
target-xtensa: add ICOUNT SR and debug exception
ICOUNT SR gets incremented on every instruction completion provided thatCINTLEVEL at the beginning of the instruction execution is lower thanICOUNTLEVEL.
When ICOUNT would increment to 0 a debug exception is raised if...
target-xtensa: add DEBUGCAUSE SR and configuration
DEBUGCAUSE SR holds information about the most recent debug exception.See ISA, 4.7.7 for more details.
target-xtensa: implement instruction breakpoints
Add IBREAKA/IBREAKENABLE SRs and implement debug exception, BREAK andBREAK.N instructions and IBREAK breakpoints.
IBREAK breakpoint address is considered constant for TB lifetime.On IBREAKA/IBREAKENABLE change corresponding TBs are invalidated....
target-xtensa: implement info tlb monitor command
Command dumps valid ITLB and DTLB entries.
target-xtensa: fetch 3rd opcode byte only when needed
According to ISA, 3.5.4, third opcode byte should not be fetched for2-byte instructions.
target-xtensa: define TLB_TEMPLATE for MMU-less cores
TLB_TEMPLATE macro specifies TLB geometry in the core configuration.Make TLB_TEMPLATE available for region protection core variants,defining 1 way ITLB and DTLB with 8 entries each.
target-xtensa: fix MMUv3 initialization
- ITLB/DTLB ways 5 and 6 have 4 and 8 entries respectively;- ITLB/DTLB way 6 attr field is set to 3 on reset.
target-xtensa: handle cache options in the overlay tool
Cache options must be enabled for the cores that have cache to avoidillegal instruction exceptions.
target-xtensa: raise an exception for invalid and reserved opcodes
This includes opcodes from disabled features and those marked reserved in the ISA.Also end TB on opcodes that definitely generate an exception: illegalinstructions, syscall and privileged instructions....
target-xtensa: mask out undefined bits of WINDOWSTART SR
According to ISA, table 5-156, bits 32:NAREG/4 of the WINDOWSTART SRmust be zero.
target-xtensa: add fsf core
This is FSF big endian core implemented through linux overlay.
target-xtensa: add dc232b core
This is Diamond 232L Standard Core Rev.B (LE), implemented throughlinux/gdb overlay.
target-xtensa: extract core configuration from overlay
Introduce overlay_tool.h that defines core configuration blocks fromdata available in the linux architecture variant overlay.
Overlay data is automatically generated in the core configurationprocess by Tensilica tools and can be directly converted to qemu xtensa...
target-xtensa: implement external interrupt mapping
Xtensa cores may have different mapping of external interrupt pins tointernal IRQ numers. Implement API to acquire core IRQ by its externalinterrupt number.
target-xtensa: remove hand-written xtensa cores implementations
target-xtensa: increase xtensa options accuracy
- add separate options for each operation in the MISC_OP;- add an option for MULSH/MULUH;- put S32C1I under conditional store option.
target-xtensa: implement MAC16 option
See ISA, 4.3.7 for the details.
- add ACC and MR special registers;- implement MAC16 and all inner MAC* opcode groups.
target-xtensa: fix guest hang on masked CCOMPARE interrupt
QEMU timer is used to post CCOMPARE interrupt when the core is halted.If that CCOMPARE interrupt is masked off then the timer must be rearmedin the callback, otherwise it will be rearmed next time the core goes to...
softmmu_header: pass CPUState to tlb_fill
Pass CPUState pointer to tlb_fill() instead of architecture localcpu_single_env hacks.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-xtensa: implement relocatable vectors
See ISA, 4.4.3 for details.
Vector addresses recorded in core configuration are absolute values thatcorrespond to default VECBASE value.
target-xtensa: add gdb support
Specific xtensa processor overlay for GDB contains register map inthe gdb/xtensa-config.c. This description is used by the GDB to e.g.parse 'g' response packets and it may be reused in the qemu's gdbstub(only XTREG definitions for non-pseudoregisters are needed)....
target-xtensa: implement memory protection options
- TLB opcode group;- region protection option (ISA, 4.6.3);- region translation option (ISA, 4.6.4);- MMU option (ISA, 4.6.5).
Cache control attribute bits are not used by this implementation.
target-xtensa: implement boolean option
See ISA, 4.3.9
target-xtensa: add dc232b core and board
This is Diamond 232L Standard Core Rev.B (LE).
target-xtensa: implement windowed registers
See ISA, 4.7.1 for details.
Physical registers and currently visible window are separate fields inCPUEnv. Only current window is accessible to TCG. On operations thatchange window base helpers copy current window to and from physical...
target-xtensa: implement loop option
See ISA, 4.3.2 for details.
Operations that change LEND SR value invalidate TBs at the old and atthe new LEND. LEND value at TB compilation time is considered constantand loop instruction is generated based on this value....
target-xtensa: implement extended L32R
See ISA, 4.3.3 for details.
TB flag XTENSA_TBFLAG_LITBASE is used to track enable bit of LITBASE SR.
target-xtensa: implement unaligned exception option
See ISA, 4.4.4 for details.
Correct (aligned as per ISA) address for unaligned access is generatedin case this option is not enabled.
target-xtensa: implement SIMCALL
Tensilica iss provides support for applications running in freestandingenvironment through SIMCALL command. It is used by Tensilica libc toaccess argc/argv, for file I/O, etc.
Note that simcalls that accept buffer addresses expect virtual addresses....
target-xtensa: implement interrupt option
See ISA, 4.4.6 (interrupt option), 4.4.7 (high priority interruptoption) and 4.4.8 (timer interrupt option) for details.
target-xtensa: implement accurate window check
See ISA, 4.7.1.3 for details.
Window check is inserted before commands that push "used registerwatermark" beyond its current level. Used register watermark is reset oninstructions that change WINDOW_BASE/WINDOW_START SRs....
target-xtensa: implement CPENABLE and PRID SRs
target-xtensa: implement RST3 group
- access to Special Registers (wsr, rsr);- access to User Registers (wur, rur);- misc. operations option (value clamp, sign extension, min, max);- conditional moves.
target-xtensa: implement shifts (ST1 and RST1 groups)
- ST1: SAR (shift amount special register) manipulation, NSA;- RST1: shifts, 16-bit multiplication.
target-xtensa: implement LSAI group
- base + offset load/store operations for 1/2/4 byte values;- cache operations (not implemented);- multiprocessor synchronization operations.
target-xtensa: mark reserved and TBD opcodes
Reserved opcodes must generate illegal instruction exception. Usuallythey signal emulation quality problems.Not implemented opcodes are good to see.
target-xtensa: implement SYNC group
All operations in this group are no-ops, because there are no delayedside effects.
target-xtensa: implement CACHE group
All operations in this group are no-ops, because cache ought to betransparent to applications. However cache may be abused, then we'llneed to actually implement these opcodes.
target-xtensa: add PS register and access control
target-xtensa: implement exceptions
- mark privileged opcodes with ring check;- make debug exception on exception handler entry.
target-xtensa: implement RST2 group (32 bit mul/div/rem)
target-xtensa: implement conditional jumps
- BZ (comparison to zero);- BI0 (comparison to signed immediate);- BI1 (comparison to unsigned immediate);- B (two registers comparison, bit sets comparison);- BEQZ.N/BNEZ.N (narrow comparison to zero).
target-xtensa: implement JX/RET0/CALLX
Group SNM0 (indirect jumps and calls).
target-xtensa: add special and user registers
Special Registers hold the majority of the state added to the processorby the options. See ISA, 5.3 for details.
User Registers hold state added in support of designer's TIE and in somecases of options that Tensilica provides. See ISA, 5.4 for details....
target-xtensa: add target stubs
target-xtensa: implement disas_xtensa_insn
Set up disas_xtensa_insn switch structure, mark required options on highlevel groups. Implement arithmetic/bit logic/jump/call0.
Implement code generation loop with single step/breakpoint checking.
target-xtensa: implement narrow instructions
Instructions with op0 >= 8 are 2 bytes long, others are 3 bytes long.
target-xtensa: implement RT0 group
NEG and ABS are the only members of RT0 group.