ZYNQ: Implement board MIDR control for Zynq
This patch uses the fact that the midr variable is now a propertyThis patch sets the midr variable to the boards custom midr
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>Message-id: a3754b10d150af72e4688a993e484fa2b9b8fa21.1390176489.git.alistair.francis@xilinx.com...
target-arm: A64: Add SIMD modified immediate group
This patch adds support for the AdvSIMD modified immediate group(C3.6.6) with all its suboperations (movi, orr, fmov, mvni, bic).
Signed-off-by: Alexander Graf <agraf@suse.de>[AJB: new decode struct, minor bug fixes, optimisation]...
target-arm: A64: Add SIMD scalar copy instructions
Add support for the SIMD scalar copy instruction group (C3.6.7),which consists of the single instruction DUP (element, scalar).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Richard Henderson <rth@twiddle.net>
hw/arm/boot: Don't set up ATAGS for autogenerated dtb booting
The code which decides whether to set up the ATAGS data structure onreset was using the wrong conditional, which meant we were creatingan ATAGS structure when doing a device-tree boot if the dtb was...
ARM: Convert MIDR to a property
Convert the MIDR register to a property. This allows boards to later seta custom MIDR value. This has been done in such a way to maintaincompatibility with all existing CPUs and boards
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>...
target-arm: A64: Add SIMD TBL/TBLX
Add support for the SIMD TBL/TBLX instructions (group C3.6.2).
Signed-off-by: Michael Matz <matz@suse.de>[PMM: rewritten to do more of the decode in translate-a64.c, and to do only one 64 bit pass at a time in the helper]...
target-arm: A64: Add SIMD ZIP/UZP/TRN
Add support for the SIMD ZIP/UZIP/TRN instruction group(C3.6.3).
Signed-off-by: Michael Matz <matz@suse.de>[PMM: use new do_vec_get/set etc functions and generally update to new codebase standards; refactor to pull per-element loop outside switch]...
target-arm: A64: Add SIMD across-lanes instructions
Add support for the SIMD "across lanes" instruction group (C3.6.4).
Signed-off-by: Michael Matz <matz@suse.de>[PMM: Updated to current codebase, added fp min/max ops, added unallocated encoding checks]...
target-arm: A64: Add SIMD copy operations
This adds support for the all the AdvSIMD vector copy operations(ARM ARM 3.6.5).
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Richard Henderson <rth@twiddle.net>
target-arm: A64: Add SIMD EXT
Add support for the SIMD EXT instruction (the only one in itsgroup, C3.6.1).
View all revisions | View revisions
Also available in: Atom