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1 | a541f297 | bellard | /*
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2 | 819385c5 | bellard | * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
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3 | 5fafdf24 | ths | *
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4 | 3ccacc4a | blueswir1 | * Copyright (c) 2003-2005, 2007 Jocelyn Mayer
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5 | 5fafdf24 | ths | *
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6 | a541f297 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | a541f297 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | a541f297 | bellard | * in the Software without restriction, including without limitation the rights
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9 | a541f297 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | a541f297 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | a541f297 | bellard | * furnished to do so, subject to the following conditions:
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12 | a541f297 | bellard | *
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13 | a541f297 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | a541f297 | bellard | * all copies or substantial portions of the Software.
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15 | a541f297 | bellard | *
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16 | a541f297 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | a541f297 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | a541f297 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | a541f297 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | a541f297 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | a541f297 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | a541f297 | bellard | * THE SOFTWARE.
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23 | a541f297 | bellard | */
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24 | a541f297 | bellard | #include "vl.h" |
25 | c5df018e | bellard | #include "m48t59.h" |
26 | a541f297 | bellard | |
27 | 13ab5daa | bellard | //#define DEBUG_NVRAM
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28 | a541f297 | bellard | |
29 | 13ab5daa | bellard | #if defined(DEBUG_NVRAM)
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30 | a541f297 | bellard | #define NVRAM_PRINTF(fmt, args...) do { printf(fmt , ##args); } while (0) |
31 | a541f297 | bellard | #else
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32 | a541f297 | bellard | #define NVRAM_PRINTF(fmt, args...) do { } while (0) |
33 | a541f297 | bellard | #endif
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34 | a541f297 | bellard | |
35 | 819385c5 | bellard | /*
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36 | 819385c5 | bellard | * The M48T08 and M48T59 chips are very similar. The newer '59 has
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37 | 819385c5 | bellard | * alarm and a watchdog timer and related control registers. In the
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38 | 819385c5 | bellard | * PPC platform there is also a nvram lock function.
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39 | 819385c5 | bellard | */
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40 | c5df018e | bellard | struct m48t59_t {
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41 | 819385c5 | bellard | /* Model parameters */
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42 | 819385c5 | bellard | int type; // 8 = m48t08, 59 = m48t59 |
43 | a541f297 | bellard | /* Hardware parameters */
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44 | d537cf6c | pbrook | qemu_irq IRQ; |
45 | e1bb04f7 | bellard | int mem_index;
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46 | 5dcb6b91 | blueswir1 | target_phys_addr_t mem_base; |
47 | a541f297 | bellard | uint32_t io_base; |
48 | a541f297 | bellard | uint16_t size; |
49 | a541f297 | bellard | /* RTC management */
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50 | a541f297 | bellard | time_t time_offset; |
51 | a541f297 | bellard | time_t stop_time; |
52 | a541f297 | bellard | /* Alarm & watchdog */
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53 | a541f297 | bellard | time_t alarm; |
54 | a541f297 | bellard | struct QEMUTimer *alrm_timer;
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55 | a541f297 | bellard | struct QEMUTimer *wd_timer;
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56 | a541f297 | bellard | /* NVRAM storage */
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57 | 13ab5daa | bellard | uint8_t lock; |
58 | a541f297 | bellard | uint16_t addr; |
59 | a541f297 | bellard | uint8_t *buffer; |
60 | c5df018e | bellard | }; |
61 | a541f297 | bellard | |
62 | a541f297 | bellard | /* Fake timer functions */
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63 | a541f297 | bellard | /* Generic helpers for BCD */
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64 | a541f297 | bellard | static inline uint8_t toBCD (uint8_t value) |
65 | a541f297 | bellard | { |
66 | a541f297 | bellard | return (((value / 10) % 10) << 4) | (value % 10); |
67 | a541f297 | bellard | } |
68 | a541f297 | bellard | |
69 | a541f297 | bellard | static inline uint8_t fromBCD (uint8_t BCD) |
70 | a541f297 | bellard | { |
71 | a541f297 | bellard | return ((BCD >> 4) * 10) + (BCD & 0x0F); |
72 | a541f297 | bellard | } |
73 | a541f297 | bellard | |
74 | a541f297 | bellard | /* RTC management helpers */
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75 | a541f297 | bellard | static void get_time (m48t59_t *NVRAM, struct tm *tm) |
76 | a541f297 | bellard | { |
77 | a541f297 | bellard | time_t t; |
78 | a541f297 | bellard | |
79 | a541f297 | bellard | t = time(NULL) + NVRAM->time_offset;
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80 | d157e205 | bellard | #ifdef _WIN32
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81 | d157e205 | bellard | memcpy(tm,localtime(&t),sizeof(*tm));
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82 | d157e205 | bellard | #else
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83 | 36cbaae5 | blueswir1 | if (rtc_utc)
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84 | 36cbaae5 | blueswir1 | gmtime_r (&t, tm); |
85 | 36cbaae5 | blueswir1 | else
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86 | 36cbaae5 | blueswir1 | localtime_r (&t, tm) ; |
87 | d157e205 | bellard | #endif
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88 | a541f297 | bellard | } |
89 | a541f297 | bellard | |
90 | a541f297 | bellard | static void set_time (m48t59_t *NVRAM, struct tm *tm) |
91 | a541f297 | bellard | { |
92 | a541f297 | bellard | time_t now, new_time; |
93 | 3b46e624 | ths | |
94 | a541f297 | bellard | new_time = mktime(tm); |
95 | a541f297 | bellard | now = time(NULL);
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96 | a541f297 | bellard | NVRAM->time_offset = new_time - now; |
97 | a541f297 | bellard | } |
98 | a541f297 | bellard | |
99 | a541f297 | bellard | /* Alarm management */
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100 | a541f297 | bellard | static void alarm_cb (void *opaque) |
101 | a541f297 | bellard | { |
102 | a541f297 | bellard | struct tm tm, tm_now;
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103 | a541f297 | bellard | uint64_t next_time; |
104 | a541f297 | bellard | m48t59_t *NVRAM = opaque; |
105 | a541f297 | bellard | |
106 | d537cf6c | pbrook | qemu_set_irq(NVRAM->IRQ, 1);
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107 | 5fafdf24 | ths | if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 && |
108 | a541f297 | bellard | (NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
109 | a541f297 | bellard | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
110 | a541f297 | bellard | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
111 | a541f297 | bellard | /* Repeat once a month */
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112 | a541f297 | bellard | get_time(NVRAM, &tm_now); |
113 | a541f297 | bellard | memcpy(&tm, &tm_now, sizeof(struct tm)); |
114 | a541f297 | bellard | tm.tm_mon++; |
115 | a541f297 | bellard | if (tm.tm_mon == 13) { |
116 | a541f297 | bellard | tm.tm_mon = 1;
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117 | a541f297 | bellard | tm.tm_year++; |
118 | a541f297 | bellard | } |
119 | a541f297 | bellard | next_time = mktime(&tm); |
120 | a541f297 | bellard | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
121 | a541f297 | bellard | (NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
122 | a541f297 | bellard | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
123 | a541f297 | bellard | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
124 | a541f297 | bellard | /* Repeat once a day */
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125 | a541f297 | bellard | next_time = 24 * 60 * 60 + mktime(&tm_now); |
126 | a541f297 | bellard | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
127 | a541f297 | bellard | (NVRAM->buffer[0x1FF4] & 0x80) != 0 && |
128 | a541f297 | bellard | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
129 | a541f297 | bellard | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
130 | a541f297 | bellard | /* Repeat once an hour */
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131 | a541f297 | bellard | next_time = 60 * 60 + mktime(&tm_now); |
132 | a541f297 | bellard | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
133 | a541f297 | bellard | (NVRAM->buffer[0x1FF4] & 0x80) != 0 && |
134 | a541f297 | bellard | (NVRAM->buffer[0x1FF3] & 0x80) != 0 && |
135 | a541f297 | bellard | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
136 | a541f297 | bellard | /* Repeat once a minute */
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137 | a541f297 | bellard | next_time = 60 + mktime(&tm_now);
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138 | a541f297 | bellard | } else {
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139 | a541f297 | bellard | /* Repeat once a second */
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140 | a541f297 | bellard | next_time = 1 + mktime(&tm_now);
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141 | a541f297 | bellard | } |
142 | a541f297 | bellard | qemu_mod_timer(NVRAM->alrm_timer, next_time * 1000);
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143 | d537cf6c | pbrook | qemu_set_irq(NVRAM->IRQ, 0);
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144 | a541f297 | bellard | } |
145 | a541f297 | bellard | |
146 | a541f297 | bellard | |
147 | a541f297 | bellard | static void get_alarm (m48t59_t *NVRAM, struct tm *tm) |
148 | a541f297 | bellard | { |
149 | d157e205 | bellard | #ifdef _WIN32
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150 | d157e205 | bellard | memcpy(tm,localtime(&NVRAM->alarm),sizeof(*tm));
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151 | d157e205 | bellard | #else
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152 | 36cbaae5 | blueswir1 | if (rtc_utc)
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153 | 36cbaae5 | blueswir1 | gmtime_r (&NVRAM->alarm, tm); |
154 | 36cbaae5 | blueswir1 | else
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155 | 36cbaae5 | blueswir1 | localtime_r (&NVRAM->alarm, tm); |
156 | d157e205 | bellard | #endif
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157 | a541f297 | bellard | } |
158 | a541f297 | bellard | |
159 | a541f297 | bellard | static void set_alarm (m48t59_t *NVRAM, struct tm *tm) |
160 | a541f297 | bellard | { |
161 | a541f297 | bellard | NVRAM->alarm = mktime(tm); |
162 | a541f297 | bellard | if (NVRAM->alrm_timer != NULL) { |
163 | a541f297 | bellard | qemu_del_timer(NVRAM->alrm_timer); |
164 | 868d585a | j_mayer | if (NVRAM->alarm - time(NULL) > 0) |
165 | 868d585a | j_mayer | qemu_mod_timer(NVRAM->alrm_timer, NVRAM->alarm * 1000);
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166 | a541f297 | bellard | } |
167 | a541f297 | bellard | } |
168 | a541f297 | bellard | |
169 | a541f297 | bellard | /* Watchdog management */
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170 | a541f297 | bellard | static void watchdog_cb (void *opaque) |
171 | a541f297 | bellard | { |
172 | a541f297 | bellard | m48t59_t *NVRAM = opaque; |
173 | a541f297 | bellard | |
174 | a541f297 | bellard | NVRAM->buffer[0x1FF0] |= 0x80; |
175 | a541f297 | bellard | if (NVRAM->buffer[0x1FF7] & 0x80) { |
176 | a541f297 | bellard | NVRAM->buffer[0x1FF7] = 0x00; |
177 | a541f297 | bellard | NVRAM->buffer[0x1FFC] &= ~0x40; |
178 | 13ab5daa | bellard | /* May it be a hw CPU Reset instead ? */
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179 | d7d02e3c | bellard | qemu_system_reset_request(); |
180 | a541f297 | bellard | } else {
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181 | d537cf6c | pbrook | qemu_set_irq(NVRAM->IRQ, 1);
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182 | d537cf6c | pbrook | qemu_set_irq(NVRAM->IRQ, 0);
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183 | a541f297 | bellard | } |
184 | a541f297 | bellard | } |
185 | a541f297 | bellard | |
186 | a541f297 | bellard | static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value) |
187 | a541f297 | bellard | { |
188 | a541f297 | bellard | uint64_t interval; /* in 1/16 seconds */
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189 | a541f297 | bellard | |
190 | 868d585a | j_mayer | NVRAM->buffer[0x1FF0] &= ~0x80; |
191 | a541f297 | bellard | if (NVRAM->wd_timer != NULL) { |
192 | a541f297 | bellard | qemu_del_timer(NVRAM->wd_timer); |
193 | 868d585a | j_mayer | if (value != 0) { |
194 | 868d585a | j_mayer | interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F); |
195 | 868d585a | j_mayer | qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) + |
196 | 868d585a | j_mayer | ((interval * 1000) >> 4)); |
197 | 868d585a | j_mayer | } |
198 | a541f297 | bellard | } |
199 | a541f297 | bellard | } |
200 | a541f297 | bellard | |
201 | a541f297 | bellard | /* Direct access to NVRAM */
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202 | 897b4c6c | j_mayer | void m48t59_write (void *opaque, uint32_t addr, uint32_t val) |
203 | a541f297 | bellard | { |
204 | 897b4c6c | j_mayer | m48t59_t *NVRAM = opaque; |
205 | a541f297 | bellard | struct tm tm;
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206 | a541f297 | bellard | int tmp;
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207 | a541f297 | bellard | |
208 | 819385c5 | bellard | if (addr > 0x1FF8 && addr < 0x2000) |
209 | 819385c5 | bellard | NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
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210 | 5fafdf24 | ths | if (NVRAM->type == 8 && |
211 | 819385c5 | bellard | (addr >= 0x1ff0 && addr <= 0x1ff7)) |
212 | 819385c5 | bellard | goto do_write;
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213 | 819385c5 | bellard | switch (addr) {
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214 | a541f297 | bellard | case 0x1FF0: |
215 | a541f297 | bellard | /* flags register : read-only */
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216 | a541f297 | bellard | break;
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217 | a541f297 | bellard | case 0x1FF1: |
218 | a541f297 | bellard | /* unused */
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219 | a541f297 | bellard | break;
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220 | a541f297 | bellard | case 0x1FF2: |
221 | a541f297 | bellard | /* alarm seconds */
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222 | 819385c5 | bellard | tmp = fromBCD(val & 0x7F);
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223 | 819385c5 | bellard | if (tmp >= 0 && tmp <= 59) { |
224 | 819385c5 | bellard | get_alarm(NVRAM, &tm); |
225 | 819385c5 | bellard | tm.tm_sec = tmp; |
226 | 819385c5 | bellard | NVRAM->buffer[0x1FF2] = val;
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227 | 819385c5 | bellard | set_alarm(NVRAM, &tm); |
228 | 819385c5 | bellard | } |
229 | a541f297 | bellard | break;
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230 | a541f297 | bellard | case 0x1FF3: |
231 | a541f297 | bellard | /* alarm minutes */
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232 | 819385c5 | bellard | tmp = fromBCD(val & 0x7F);
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233 | 819385c5 | bellard | if (tmp >= 0 && tmp <= 59) { |
234 | 819385c5 | bellard | get_alarm(NVRAM, &tm); |
235 | 819385c5 | bellard | tm.tm_min = tmp; |
236 | 819385c5 | bellard | NVRAM->buffer[0x1FF3] = val;
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237 | 819385c5 | bellard | set_alarm(NVRAM, &tm); |
238 | 819385c5 | bellard | } |
239 | a541f297 | bellard | break;
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240 | a541f297 | bellard | case 0x1FF4: |
241 | a541f297 | bellard | /* alarm hours */
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242 | 819385c5 | bellard | tmp = fromBCD(val & 0x3F);
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243 | 819385c5 | bellard | if (tmp >= 0 && tmp <= 23) { |
244 | 819385c5 | bellard | get_alarm(NVRAM, &tm); |
245 | 819385c5 | bellard | tm.tm_hour = tmp; |
246 | 819385c5 | bellard | NVRAM->buffer[0x1FF4] = val;
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247 | 819385c5 | bellard | set_alarm(NVRAM, &tm); |
248 | 819385c5 | bellard | } |
249 | a541f297 | bellard | break;
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250 | a541f297 | bellard | case 0x1FF5: |
251 | a541f297 | bellard | /* alarm date */
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252 | 819385c5 | bellard | tmp = fromBCD(val & 0x1F);
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253 | 819385c5 | bellard | if (tmp != 0) { |
254 | 819385c5 | bellard | get_alarm(NVRAM, &tm); |
255 | 819385c5 | bellard | tm.tm_mday = tmp; |
256 | 819385c5 | bellard | NVRAM->buffer[0x1FF5] = val;
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257 | 819385c5 | bellard | set_alarm(NVRAM, &tm); |
258 | 819385c5 | bellard | } |
259 | a541f297 | bellard | break;
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260 | a541f297 | bellard | case 0x1FF6: |
261 | a541f297 | bellard | /* interrupts */
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262 | 819385c5 | bellard | NVRAM->buffer[0x1FF6] = val;
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263 | a541f297 | bellard | break;
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264 | a541f297 | bellard | case 0x1FF7: |
265 | a541f297 | bellard | /* watchdog */
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266 | 819385c5 | bellard | NVRAM->buffer[0x1FF7] = val;
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267 | 819385c5 | bellard | set_up_watchdog(NVRAM, val); |
268 | a541f297 | bellard | break;
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269 | a541f297 | bellard | case 0x1FF8: |
270 | a541f297 | bellard | /* control */
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271 | a541f297 | bellard | NVRAM->buffer[0x1FF8] = (val & ~0xA0) | 0x90; |
272 | a541f297 | bellard | break;
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273 | a541f297 | bellard | case 0x1FF9: |
274 | a541f297 | bellard | /* seconds (BCD) */
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275 | a541f297 | bellard | tmp = fromBCD(val & 0x7F);
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276 | a541f297 | bellard | if (tmp >= 0 && tmp <= 59) { |
277 | a541f297 | bellard | get_time(NVRAM, &tm); |
278 | a541f297 | bellard | tm.tm_sec = tmp; |
279 | a541f297 | bellard | set_time(NVRAM, &tm); |
280 | a541f297 | bellard | } |
281 | a541f297 | bellard | if ((val & 0x80) ^ (NVRAM->buffer[0x1FF9] & 0x80)) { |
282 | a541f297 | bellard | if (val & 0x80) { |
283 | a541f297 | bellard | NVRAM->stop_time = time(NULL);
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284 | a541f297 | bellard | } else {
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285 | a541f297 | bellard | NVRAM->time_offset += NVRAM->stop_time - time(NULL);
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286 | a541f297 | bellard | NVRAM->stop_time = 0;
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287 | a541f297 | bellard | } |
288 | a541f297 | bellard | } |
289 | a541f297 | bellard | NVRAM->buffer[0x1FF9] = val & 0x80; |
290 | a541f297 | bellard | break;
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291 | a541f297 | bellard | case 0x1FFA: |
292 | a541f297 | bellard | /* minutes (BCD) */
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293 | a541f297 | bellard | tmp = fromBCD(val & 0x7F);
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294 | a541f297 | bellard | if (tmp >= 0 && tmp <= 59) { |
295 | a541f297 | bellard | get_time(NVRAM, &tm); |
296 | a541f297 | bellard | tm.tm_min = tmp; |
297 | a541f297 | bellard | set_time(NVRAM, &tm); |
298 | a541f297 | bellard | } |
299 | a541f297 | bellard | break;
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300 | a541f297 | bellard | case 0x1FFB: |
301 | a541f297 | bellard | /* hours (BCD) */
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302 | a541f297 | bellard | tmp = fromBCD(val & 0x3F);
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303 | a541f297 | bellard | if (tmp >= 0 && tmp <= 23) { |
304 | a541f297 | bellard | get_time(NVRAM, &tm); |
305 | a541f297 | bellard | tm.tm_hour = tmp; |
306 | a541f297 | bellard | set_time(NVRAM, &tm); |
307 | a541f297 | bellard | } |
308 | a541f297 | bellard | break;
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309 | a541f297 | bellard | case 0x1FFC: |
310 | a541f297 | bellard | /* day of the week / century */
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311 | a541f297 | bellard | tmp = fromBCD(val & 0x07);
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312 | a541f297 | bellard | get_time(NVRAM, &tm); |
313 | a541f297 | bellard | tm.tm_wday = tmp; |
314 | a541f297 | bellard | set_time(NVRAM, &tm); |
315 | a541f297 | bellard | NVRAM->buffer[0x1FFC] = val & 0x40; |
316 | a541f297 | bellard | break;
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317 | a541f297 | bellard | case 0x1FFD: |
318 | a541f297 | bellard | /* date */
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319 | a541f297 | bellard | tmp = fromBCD(val & 0x1F);
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320 | a541f297 | bellard | if (tmp != 0) { |
321 | a541f297 | bellard | get_time(NVRAM, &tm); |
322 | a541f297 | bellard | tm.tm_mday = tmp; |
323 | a541f297 | bellard | set_time(NVRAM, &tm); |
324 | a541f297 | bellard | } |
325 | a541f297 | bellard | break;
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326 | a541f297 | bellard | case 0x1FFE: |
327 | a541f297 | bellard | /* month */
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328 | a541f297 | bellard | tmp = fromBCD(val & 0x1F);
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329 | a541f297 | bellard | if (tmp >= 1 && tmp <= 12) { |
330 | a541f297 | bellard | get_time(NVRAM, &tm); |
331 | a541f297 | bellard | tm.tm_mon = tmp - 1;
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332 | a541f297 | bellard | set_time(NVRAM, &tm); |
333 | a541f297 | bellard | } |
334 | a541f297 | bellard | break;
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335 | a541f297 | bellard | case 0x1FFF: |
336 | a541f297 | bellard | /* year */
|
337 | a541f297 | bellard | tmp = fromBCD(val); |
338 | a541f297 | bellard | if (tmp >= 0 && tmp <= 99) { |
339 | a541f297 | bellard | get_time(NVRAM, &tm); |
340 | 180b700d | bellard | if (NVRAM->type == 8) |
341 | 180b700d | bellard | tm.tm_year = fromBCD(val) + 68; // Base year is 1968 |
342 | 180b700d | bellard | else
|
343 | 180b700d | bellard | tm.tm_year = fromBCD(val); |
344 | a541f297 | bellard | set_time(NVRAM, &tm); |
345 | a541f297 | bellard | } |
346 | a541f297 | bellard | break;
|
347 | a541f297 | bellard | default:
|
348 | 13ab5daa | bellard | /* Check lock registers state */
|
349 | 819385c5 | bellard | if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
350 | 13ab5daa | bellard | break;
|
351 | 819385c5 | bellard | if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
352 | 13ab5daa | bellard | break;
|
353 | 819385c5 | bellard | do_write:
|
354 | 819385c5 | bellard | if (addr < NVRAM->size) {
|
355 | 819385c5 | bellard | NVRAM->buffer[addr] = val & 0xFF;
|
356 | a541f297 | bellard | } |
357 | a541f297 | bellard | break;
|
358 | a541f297 | bellard | } |
359 | a541f297 | bellard | } |
360 | a541f297 | bellard | |
361 | 897b4c6c | j_mayer | uint32_t m48t59_read (void *opaque, uint32_t addr)
|
362 | a541f297 | bellard | { |
363 | 897b4c6c | j_mayer | m48t59_t *NVRAM = opaque; |
364 | a541f297 | bellard | struct tm tm;
|
365 | a541f297 | bellard | uint32_t retval = 0xFF;
|
366 | a541f297 | bellard | |
367 | 5fafdf24 | ths | if (NVRAM->type == 8 && |
368 | 819385c5 | bellard | (addr >= 0x1ff0 && addr <= 0x1ff7)) |
369 | 819385c5 | bellard | goto do_read;
|
370 | 819385c5 | bellard | switch (addr) {
|
371 | a541f297 | bellard | case 0x1FF0: |
372 | a541f297 | bellard | /* flags register */
|
373 | a541f297 | bellard | goto do_read;
|
374 | a541f297 | bellard | case 0x1FF1: |
375 | a541f297 | bellard | /* unused */
|
376 | a541f297 | bellard | retval = 0;
|
377 | a541f297 | bellard | break;
|
378 | a541f297 | bellard | case 0x1FF2: |
379 | a541f297 | bellard | /* alarm seconds */
|
380 | a541f297 | bellard | goto do_read;
|
381 | a541f297 | bellard | case 0x1FF3: |
382 | a541f297 | bellard | /* alarm minutes */
|
383 | a541f297 | bellard | goto do_read;
|
384 | a541f297 | bellard | case 0x1FF4: |
385 | a541f297 | bellard | /* alarm hours */
|
386 | a541f297 | bellard | goto do_read;
|
387 | a541f297 | bellard | case 0x1FF5: |
388 | a541f297 | bellard | /* alarm date */
|
389 | a541f297 | bellard | goto do_read;
|
390 | a541f297 | bellard | case 0x1FF6: |
391 | a541f297 | bellard | /* interrupts */
|
392 | a541f297 | bellard | goto do_read;
|
393 | a541f297 | bellard | case 0x1FF7: |
394 | a541f297 | bellard | /* A read resets the watchdog */
|
395 | a541f297 | bellard | set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
|
396 | a541f297 | bellard | goto do_read;
|
397 | a541f297 | bellard | case 0x1FF8: |
398 | a541f297 | bellard | /* control */
|
399 | a541f297 | bellard | goto do_read;
|
400 | a541f297 | bellard | case 0x1FF9: |
401 | a541f297 | bellard | /* seconds (BCD) */
|
402 | a541f297 | bellard | get_time(NVRAM, &tm); |
403 | a541f297 | bellard | retval = (NVRAM->buffer[0x1FF9] & 0x80) | toBCD(tm.tm_sec); |
404 | a541f297 | bellard | break;
|
405 | a541f297 | bellard | case 0x1FFA: |
406 | a541f297 | bellard | /* minutes (BCD) */
|
407 | a541f297 | bellard | get_time(NVRAM, &tm); |
408 | a541f297 | bellard | retval = toBCD(tm.tm_min); |
409 | a541f297 | bellard | break;
|
410 | a541f297 | bellard | case 0x1FFB: |
411 | a541f297 | bellard | /* hours (BCD) */
|
412 | a541f297 | bellard | get_time(NVRAM, &tm); |
413 | a541f297 | bellard | retval = toBCD(tm.tm_hour); |
414 | a541f297 | bellard | break;
|
415 | a541f297 | bellard | case 0x1FFC: |
416 | a541f297 | bellard | /* day of the week / century */
|
417 | a541f297 | bellard | get_time(NVRAM, &tm); |
418 | a541f297 | bellard | retval = NVRAM->buffer[0x1FFC] | tm.tm_wday;
|
419 | a541f297 | bellard | break;
|
420 | a541f297 | bellard | case 0x1FFD: |
421 | a541f297 | bellard | /* date */
|
422 | a541f297 | bellard | get_time(NVRAM, &tm); |
423 | a541f297 | bellard | retval = toBCD(tm.tm_mday); |
424 | a541f297 | bellard | break;
|
425 | a541f297 | bellard | case 0x1FFE: |
426 | a541f297 | bellard | /* month */
|
427 | a541f297 | bellard | get_time(NVRAM, &tm); |
428 | a541f297 | bellard | retval = toBCD(tm.tm_mon + 1);
|
429 | a541f297 | bellard | break;
|
430 | a541f297 | bellard | case 0x1FFF: |
431 | a541f297 | bellard | /* year */
|
432 | a541f297 | bellard | get_time(NVRAM, &tm); |
433 | 5fafdf24 | ths | if (NVRAM->type == 8) |
434 | 180b700d | bellard | retval = toBCD(tm.tm_year - 68); // Base year is 1968 |
435 | 180b700d | bellard | else
|
436 | 180b700d | bellard | retval = toBCD(tm.tm_year); |
437 | a541f297 | bellard | break;
|
438 | a541f297 | bellard | default:
|
439 | 13ab5daa | bellard | /* Check lock registers state */
|
440 | 819385c5 | bellard | if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
441 | 13ab5daa | bellard | break;
|
442 | 819385c5 | bellard | if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
443 | 13ab5daa | bellard | break;
|
444 | 819385c5 | bellard | do_read:
|
445 | 819385c5 | bellard | if (addr < NVRAM->size) {
|
446 | 819385c5 | bellard | retval = NVRAM->buffer[addr]; |
447 | a541f297 | bellard | } |
448 | a541f297 | bellard | break;
|
449 | a541f297 | bellard | } |
450 | 819385c5 | bellard | if (addr > 0x1FF9 && addr < 0x2000) |
451 | 819385c5 | bellard | NVRAM_PRINTF("0x%08x <= 0x%08x\n", addr, retval);
|
452 | a541f297 | bellard | |
453 | a541f297 | bellard | return retval;
|
454 | a541f297 | bellard | } |
455 | a541f297 | bellard | |
456 | 897b4c6c | j_mayer | void m48t59_set_addr (void *opaque, uint32_t addr) |
457 | a541f297 | bellard | { |
458 | 897b4c6c | j_mayer | m48t59_t *NVRAM = opaque; |
459 | 897b4c6c | j_mayer | |
460 | a541f297 | bellard | NVRAM->addr = addr; |
461 | a541f297 | bellard | } |
462 | a541f297 | bellard | |
463 | 897b4c6c | j_mayer | void m48t59_toggle_lock (void *opaque, int lock) |
464 | 13ab5daa | bellard | { |
465 | 897b4c6c | j_mayer | m48t59_t *NVRAM = opaque; |
466 | 897b4c6c | j_mayer | |
467 | 13ab5daa | bellard | NVRAM->lock ^= 1 << lock;
|
468 | 13ab5daa | bellard | } |
469 | 13ab5daa | bellard | |
470 | a541f297 | bellard | /* IO access to NVRAM */
|
471 | a541f297 | bellard | static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val) |
472 | a541f297 | bellard | { |
473 | a541f297 | bellard | m48t59_t *NVRAM = opaque; |
474 | a541f297 | bellard | |
475 | a541f297 | bellard | addr -= NVRAM->io_base; |
476 | 13ab5daa | bellard | NVRAM_PRINTF("0x%08x => 0x%08x\n", addr, val);
|
477 | a541f297 | bellard | switch (addr) {
|
478 | a541f297 | bellard | case 0: |
479 | a541f297 | bellard | NVRAM->addr &= ~0x00FF;
|
480 | a541f297 | bellard | NVRAM->addr |= val; |
481 | a541f297 | bellard | break;
|
482 | a541f297 | bellard | case 1: |
483 | a541f297 | bellard | NVRAM->addr &= ~0xFF00;
|
484 | a541f297 | bellard | NVRAM->addr |= val << 8;
|
485 | a541f297 | bellard | break;
|
486 | a541f297 | bellard | case 3: |
487 | 819385c5 | bellard | m48t59_write(NVRAM, val, NVRAM->addr); |
488 | a541f297 | bellard | NVRAM->addr = 0x0000;
|
489 | a541f297 | bellard | break;
|
490 | a541f297 | bellard | default:
|
491 | a541f297 | bellard | break;
|
492 | a541f297 | bellard | } |
493 | a541f297 | bellard | } |
494 | a541f297 | bellard | |
495 | a541f297 | bellard | static uint32_t NVRAM_readb (void *opaque, uint32_t addr) |
496 | a541f297 | bellard | { |
497 | a541f297 | bellard | m48t59_t *NVRAM = opaque; |
498 | 13ab5daa | bellard | uint32_t retval; |
499 | a541f297 | bellard | |
500 | 13ab5daa | bellard | addr -= NVRAM->io_base; |
501 | 13ab5daa | bellard | switch (addr) {
|
502 | 13ab5daa | bellard | case 3: |
503 | 819385c5 | bellard | retval = m48t59_read(NVRAM, NVRAM->addr); |
504 | 13ab5daa | bellard | break;
|
505 | 13ab5daa | bellard | default:
|
506 | 13ab5daa | bellard | retval = -1;
|
507 | 13ab5daa | bellard | break;
|
508 | 13ab5daa | bellard | } |
509 | 13ab5daa | bellard | NVRAM_PRINTF("0x%08x <= 0x%08x\n", addr, retval);
|
510 | a541f297 | bellard | |
511 | 13ab5daa | bellard | return retval;
|
512 | a541f297 | bellard | } |
513 | a541f297 | bellard | |
514 | e1bb04f7 | bellard | static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) |
515 | e1bb04f7 | bellard | { |
516 | e1bb04f7 | bellard | m48t59_t *NVRAM = opaque; |
517 | 3b46e624 | ths | |
518 | e1bb04f7 | bellard | addr -= NVRAM->mem_base; |
519 | 819385c5 | bellard | m48t59_write(NVRAM, addr, value & 0xff);
|
520 | e1bb04f7 | bellard | } |
521 | e1bb04f7 | bellard | |
522 | e1bb04f7 | bellard | static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
523 | e1bb04f7 | bellard | { |
524 | e1bb04f7 | bellard | m48t59_t *NVRAM = opaque; |
525 | 3b46e624 | ths | |
526 | e1bb04f7 | bellard | addr -= NVRAM->mem_base; |
527 | 819385c5 | bellard | m48t59_write(NVRAM, addr, (value >> 8) & 0xff); |
528 | 819385c5 | bellard | m48t59_write(NVRAM, addr + 1, value & 0xff); |
529 | e1bb04f7 | bellard | } |
530 | e1bb04f7 | bellard | |
531 | e1bb04f7 | bellard | static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
532 | e1bb04f7 | bellard | { |
533 | e1bb04f7 | bellard | m48t59_t *NVRAM = opaque; |
534 | 3b46e624 | ths | |
535 | e1bb04f7 | bellard | addr -= NVRAM->mem_base; |
536 | 819385c5 | bellard | m48t59_write(NVRAM, addr, (value >> 24) & 0xff); |
537 | 819385c5 | bellard | m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff); |
538 | 819385c5 | bellard | m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff); |
539 | 819385c5 | bellard | m48t59_write(NVRAM, addr + 3, value & 0xff); |
540 | e1bb04f7 | bellard | } |
541 | e1bb04f7 | bellard | |
542 | e1bb04f7 | bellard | static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr) |
543 | e1bb04f7 | bellard | { |
544 | e1bb04f7 | bellard | m48t59_t *NVRAM = opaque; |
545 | 819385c5 | bellard | uint32_t retval; |
546 | 3b46e624 | ths | |
547 | e1bb04f7 | bellard | addr -= NVRAM->mem_base; |
548 | 819385c5 | bellard | retval = m48t59_read(NVRAM, addr); |
549 | e1bb04f7 | bellard | return retval;
|
550 | e1bb04f7 | bellard | } |
551 | e1bb04f7 | bellard | |
552 | e1bb04f7 | bellard | static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr) |
553 | e1bb04f7 | bellard | { |
554 | e1bb04f7 | bellard | m48t59_t *NVRAM = opaque; |
555 | 819385c5 | bellard | uint32_t retval; |
556 | 3b46e624 | ths | |
557 | e1bb04f7 | bellard | addr -= NVRAM->mem_base; |
558 | 819385c5 | bellard | retval = m48t59_read(NVRAM, addr) << 8;
|
559 | 819385c5 | bellard | retval |= m48t59_read(NVRAM, addr + 1);
|
560 | e1bb04f7 | bellard | return retval;
|
561 | e1bb04f7 | bellard | } |
562 | e1bb04f7 | bellard | |
563 | e1bb04f7 | bellard | static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr) |
564 | e1bb04f7 | bellard | { |
565 | e1bb04f7 | bellard | m48t59_t *NVRAM = opaque; |
566 | 819385c5 | bellard | uint32_t retval; |
567 | e1bb04f7 | bellard | |
568 | 819385c5 | bellard | addr -= NVRAM->mem_base; |
569 | 819385c5 | bellard | retval = m48t59_read(NVRAM, addr) << 24;
|
570 | 819385c5 | bellard | retval |= m48t59_read(NVRAM, addr + 1) << 16; |
571 | 819385c5 | bellard | retval |= m48t59_read(NVRAM, addr + 2) << 8; |
572 | 819385c5 | bellard | retval |= m48t59_read(NVRAM, addr + 3);
|
573 | e1bb04f7 | bellard | return retval;
|
574 | e1bb04f7 | bellard | } |
575 | e1bb04f7 | bellard | |
576 | e1bb04f7 | bellard | static CPUWriteMemoryFunc *nvram_write[] = {
|
577 | e1bb04f7 | bellard | &nvram_writeb, |
578 | e1bb04f7 | bellard | &nvram_writew, |
579 | e1bb04f7 | bellard | &nvram_writel, |
580 | e1bb04f7 | bellard | }; |
581 | e1bb04f7 | bellard | |
582 | e1bb04f7 | bellard | static CPUReadMemoryFunc *nvram_read[] = {
|
583 | e1bb04f7 | bellard | &nvram_readb, |
584 | e1bb04f7 | bellard | &nvram_readw, |
585 | e1bb04f7 | bellard | &nvram_readl, |
586 | e1bb04f7 | bellard | }; |
587 | 819385c5 | bellard | |
588 | 3ccacc4a | blueswir1 | static void m48t59_save(QEMUFile *f, void *opaque) |
589 | 3ccacc4a | blueswir1 | { |
590 | 3ccacc4a | blueswir1 | m48t59_t *s = opaque; |
591 | 3ccacc4a | blueswir1 | |
592 | 3ccacc4a | blueswir1 | qemu_put_8s(f, &s->lock); |
593 | 3ccacc4a | blueswir1 | qemu_put_be16s(f, &s->addr); |
594 | 3ccacc4a | blueswir1 | qemu_put_buffer(f, s->buffer, s->size); |
595 | 3ccacc4a | blueswir1 | } |
596 | 3ccacc4a | blueswir1 | |
597 | 3ccacc4a | blueswir1 | static int m48t59_load(QEMUFile *f, void *opaque, int version_id) |
598 | 3ccacc4a | blueswir1 | { |
599 | 3ccacc4a | blueswir1 | m48t59_t *s = opaque; |
600 | 3ccacc4a | blueswir1 | |
601 | 3ccacc4a | blueswir1 | if (version_id != 1) |
602 | 3ccacc4a | blueswir1 | return -EINVAL;
|
603 | 3ccacc4a | blueswir1 | |
604 | 3ccacc4a | blueswir1 | qemu_get_8s(f, &s->lock); |
605 | 3ccacc4a | blueswir1 | qemu_get_be16s(f, &s->addr); |
606 | 3ccacc4a | blueswir1 | qemu_get_buffer(f, s->buffer, s->size); |
607 | 3ccacc4a | blueswir1 | |
608 | 3ccacc4a | blueswir1 | return 0; |
609 | 3ccacc4a | blueswir1 | } |
610 | 3ccacc4a | blueswir1 | |
611 | 3ccacc4a | blueswir1 | static void m48t59_reset(void *opaque) |
612 | 3ccacc4a | blueswir1 | { |
613 | 3ccacc4a | blueswir1 | m48t59_t *NVRAM = opaque; |
614 | 3ccacc4a | blueswir1 | |
615 | 3ccacc4a | blueswir1 | if (NVRAM->alrm_timer != NULL) |
616 | 3ccacc4a | blueswir1 | qemu_del_timer(NVRAM->alrm_timer); |
617 | 3ccacc4a | blueswir1 | |
618 | 3ccacc4a | blueswir1 | if (NVRAM->wd_timer != NULL) |
619 | 3ccacc4a | blueswir1 | qemu_del_timer(NVRAM->wd_timer); |
620 | 3ccacc4a | blueswir1 | } |
621 | 3ccacc4a | blueswir1 | |
622 | a541f297 | bellard | /* Initialisation routine */
|
623 | 5dcb6b91 | blueswir1 | m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base, |
624 | 819385c5 | bellard | uint32_t io_base, uint16_t size, |
625 | 819385c5 | bellard | int type)
|
626 | a541f297 | bellard | { |
627 | c5df018e | bellard | m48t59_t *s; |
628 | 5dcb6b91 | blueswir1 | target_phys_addr_t save_base; |
629 | a541f297 | bellard | |
630 | c5df018e | bellard | s = qemu_mallocz(sizeof(m48t59_t));
|
631 | c5df018e | bellard | if (!s)
|
632 | a541f297 | bellard | return NULL; |
633 | c5df018e | bellard | s->buffer = qemu_mallocz(size); |
634 | c5df018e | bellard | if (!s->buffer) {
|
635 | c5df018e | bellard | qemu_free(s); |
636 | c5df018e | bellard | return NULL; |
637 | c5df018e | bellard | } |
638 | c5df018e | bellard | s->IRQ = IRQ; |
639 | c5df018e | bellard | s->size = size; |
640 | e1bb04f7 | bellard | s->mem_base = mem_base; |
641 | c5df018e | bellard | s->io_base = io_base; |
642 | c5df018e | bellard | s->addr = 0;
|
643 | 819385c5 | bellard | s->type = type; |
644 | 819385c5 | bellard | if (io_base != 0) { |
645 | 819385c5 | bellard | register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s); |
646 | 819385c5 | bellard | register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s); |
647 | 819385c5 | bellard | } |
648 | e1bb04f7 | bellard | if (mem_base != 0) { |
649 | e1bb04f7 | bellard | s->mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s);
|
650 | e1bb04f7 | bellard | cpu_register_physical_memory(mem_base, 0x4000, s->mem_index);
|
651 | e1bb04f7 | bellard | } |
652 | 819385c5 | bellard | if (type == 59) { |
653 | 819385c5 | bellard | s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s); |
654 | 819385c5 | bellard | s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s); |
655 | 819385c5 | bellard | } |
656 | 13ab5daa | bellard | s->lock = 0;
|
657 | 13ab5daa | bellard | |
658 | 3ccacc4a | blueswir1 | qemu_register_reset(m48t59_reset, s); |
659 | 3ccacc4a | blueswir1 | save_base = mem_base ? mem_base : io_base; |
660 | 3ccacc4a | blueswir1 | register_savevm("m48t59", save_base, 1, m48t59_save, m48t59_load, s); |
661 | 3ccacc4a | blueswir1 | |
662 | c5df018e | bellard | return s;
|
663 | a541f297 | bellard | } |