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1 | 9a64fbe4 | bellard | /*
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2 | a541f297 | bellard | * QEMU PPC PREP hardware System Emulator
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3 | 5fafdf24 | ths | *
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4 | 47103572 | j_mayer | * Copyright (c) 2003-2007 Jocelyn Mayer
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5 | 5fafdf24 | ths | *
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6 | a541f297 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | a541f297 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | a541f297 | bellard | * in the Software without restriction, including without limitation the rights
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9 | a541f297 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | a541f297 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | a541f297 | bellard | * furnished to do so, subject to the following conditions:
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12 | a541f297 | bellard | *
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13 | a541f297 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | a541f297 | bellard | * all copies or substantial portions of the Software.
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15 | a541f297 | bellard | *
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16 | a541f297 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | a541f297 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | a541f297 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | a541f297 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | a541f297 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | a541f297 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | a541f297 | bellard | * THE SOFTWARE.
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23 | 9a64fbe4 | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "nvram.h" |
26 | 87ecb68b | pbrook | #include "pc.h" |
27 | 87ecb68b | pbrook | #include "fdc.h" |
28 | 87ecb68b | pbrook | #include "net.h" |
29 | 87ecb68b | pbrook | #include "sysemu.h" |
30 | 87ecb68b | pbrook | #include "isa.h" |
31 | 87ecb68b | pbrook | #include "pci.h" |
32 | 87ecb68b | pbrook | #include "ppc.h" |
33 | 87ecb68b | pbrook | #include "boards.h" |
34 | 3b3fb322 | blueswir1 | #include "qemu-log.h" |
35 | 9fddaa0c | bellard | |
36 | 9a64fbe4 | bellard | //#define HARD_DEBUG_PPC_IO
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37 | a541f297 | bellard | //#define DEBUG_PPC_IO
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38 | 9a64fbe4 | bellard | |
39 | fe33cc71 | j_mayer | /* SMP is not enabled, for now */
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40 | fe33cc71 | j_mayer | #define MAX_CPUS 1 |
41 | fe33cc71 | j_mayer | |
42 | e4bcb14c | ths | #define MAX_IDE_BUS 2 |
43 | e4bcb14c | ths | |
44 | b6b8bd18 | bellard | #define BIOS_FILENAME "ppc_rom.bin" |
45 | b6b8bd18 | bellard | #define KERNEL_LOAD_ADDR 0x01000000 |
46 | b6b8bd18 | bellard | #define INITRD_LOAD_ADDR 0x01800000 |
47 | 64201201 | bellard | |
48 | 9a64fbe4 | bellard | #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
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49 | 9a64fbe4 | bellard | #define DEBUG_PPC_IO
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50 | 9a64fbe4 | bellard | #endif
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51 | 9a64fbe4 | bellard | |
52 | 9a64fbe4 | bellard | #if defined (HARD_DEBUG_PPC_IO)
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53 | 9a64fbe4 | bellard | #define PPC_IO_DPRINTF(fmt, args...) \
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54 | 9a64fbe4 | bellard | do { \
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55 | 8fec2b8c | aliguori | if (qemu_loglevel_mask(CPU_LOG_IOPORT)) { \
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56 | 93fcfe39 | aliguori | qemu_log("%s: " fmt, __func__ , ##args); \ |
57 | 9a64fbe4 | bellard | } else { \
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58 | 9a64fbe4 | bellard | printf("%s : " fmt, __func__ , ##args); \ |
59 | 9a64fbe4 | bellard | } \ |
60 | 9a64fbe4 | bellard | } while (0) |
61 | 9a64fbe4 | bellard | #elif defined (DEBUG_PPC_IO)
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62 | 93fcfe39 | aliguori | #define PPC_IO_DPRINTF(fmt, args...) qemu_log_mask(CPU_LOG_IOPORT, ## __VA_ARGS__) |
63 | 9a64fbe4 | bellard | #else
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64 | 9a64fbe4 | bellard | #define PPC_IO_DPRINTF(fmt, args...) do { } while (0) |
65 | 9a64fbe4 | bellard | #endif
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66 | 9a64fbe4 | bellard | |
67 | 64201201 | bellard | /* Constants for devices init */
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68 | a541f297 | bellard | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
69 | a541f297 | bellard | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; |
70 | a541f297 | bellard | static const int ide_irq[2] = { 13, 13 }; |
71 | a541f297 | bellard | |
72 | a541f297 | bellard | #define NE2000_NB_MAX 6 |
73 | a541f297 | bellard | |
74 | a541f297 | bellard | static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; |
75 | a541f297 | bellard | static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; |
76 | 9a64fbe4 | bellard | |
77 | 64201201 | bellard | //static PITState *pit;
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78 | 64201201 | bellard | |
79 | 64201201 | bellard | /* ISA IO ports bridge */
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80 | 9a64fbe4 | bellard | #define PPC_IO_BASE 0x80000000 |
81 | 9a64fbe4 | bellard | |
82 | b1d8e52e | blueswir1 | #if 0
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83 | 64201201 | bellard | /* Speaker port 0x61 */
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84 | b1d8e52e | blueswir1 | static int speaker_data_on;
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85 | b1d8e52e | blueswir1 | static int dummy_refresh_clock;
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86 | b1d8e52e | blueswir1 | #endif
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87 | 64201201 | bellard | |
88 | 36081602 | j_mayer | static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val) |
89 | 9a64fbe4 | bellard | { |
90 | a541f297 | bellard | #if 0
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91 | 64201201 | bellard | speaker_data_on = (val >> 1) & 1;
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92 | 64201201 | bellard | pit_set_gate(pit, 2, val & 1);
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93 | a541f297 | bellard | #endif
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94 | 9a64fbe4 | bellard | } |
95 | 9a64fbe4 | bellard | |
96 | 47103572 | j_mayer | static uint32_t speaker_ioport_read (void *opaque, uint32_t addr) |
97 | 9a64fbe4 | bellard | { |
98 | a541f297 | bellard | #if 0
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99 | 64201201 | bellard | int out;
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100 | 64201201 | bellard | out = pit_get_out(pit, 2, qemu_get_clock(vm_clock));
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101 | 64201201 | bellard | dummy_refresh_clock ^= 1;
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102 | 64201201 | bellard | return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
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103 | 47103572 | j_mayer | (dummy_refresh_clock << 4);
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104 | a541f297 | bellard | #endif
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105 | 64201201 | bellard | return 0; |
106 | 9a64fbe4 | bellard | } |
107 | 9a64fbe4 | bellard | |
108 | 64201201 | bellard | /* PCI intack register */
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109 | 64201201 | bellard | /* Read-only register (?) */
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110 | 47103572 | j_mayer | static void _PPC_intack_write (void *opaque, |
111 | 47103572 | j_mayer | target_phys_addr_t addr, uint32_t value) |
112 | 64201201 | bellard | { |
113 | aae9366a | j_mayer | // printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
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114 | 64201201 | bellard | } |
115 | 64201201 | bellard | |
116 | b068d6a7 | j_mayer | static always_inline uint32_t _PPC_intack_read (target_phys_addr_t addr)
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117 | 64201201 | bellard | { |
118 | 64201201 | bellard | uint32_t retval = 0;
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119 | 64201201 | bellard | |
120 | 4dd8c138 | aurel32 | if ((addr & 0xf) == 0) |
121 | 3de388f6 | bellard | retval = pic_intack_read(isa_pic); |
122 | aae9366a | j_mayer | // printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
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123 | 64201201 | bellard | |
124 | 64201201 | bellard | return retval;
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125 | 64201201 | bellard | } |
126 | 64201201 | bellard | |
127 | a4193c8a | bellard | static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr) |
128 | 64201201 | bellard | { |
129 | 64201201 | bellard | return _PPC_intack_read(addr);
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130 | 64201201 | bellard | } |
131 | 64201201 | bellard | |
132 | a4193c8a | bellard | static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr) |
133 | 9a64fbe4 | bellard | { |
134 | f658b4db | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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135 | 64201201 | bellard | return bswap16(_PPC_intack_read(addr));
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136 | 64201201 | bellard | #else
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137 | 64201201 | bellard | return _PPC_intack_read(addr);
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138 | f658b4db | bellard | #endif
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139 | 9a64fbe4 | bellard | } |
140 | 9a64fbe4 | bellard | |
141 | a4193c8a | bellard | static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr) |
142 | 9a64fbe4 | bellard | { |
143 | f658b4db | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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144 | 64201201 | bellard | return bswap32(_PPC_intack_read(addr));
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145 | 64201201 | bellard | #else
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146 | 64201201 | bellard | return _PPC_intack_read(addr);
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147 | f658b4db | bellard | #endif
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148 | 9a64fbe4 | bellard | } |
149 | 9a64fbe4 | bellard | |
150 | 64201201 | bellard | static CPUWriteMemoryFunc *PPC_intack_write[] = {
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151 | 64201201 | bellard | &_PPC_intack_write, |
152 | 64201201 | bellard | &_PPC_intack_write, |
153 | 64201201 | bellard | &_PPC_intack_write, |
154 | 64201201 | bellard | }; |
155 | 64201201 | bellard | |
156 | 64201201 | bellard | static CPUReadMemoryFunc *PPC_intack_read[] = {
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157 | 64201201 | bellard | &PPC_intack_readb, |
158 | 64201201 | bellard | &PPC_intack_readw, |
159 | 64201201 | bellard | &PPC_intack_readl, |
160 | 64201201 | bellard | }; |
161 | 64201201 | bellard | |
162 | 64201201 | bellard | /* PowerPC control and status registers */
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163 | 64201201 | bellard | #if 0 // Not used
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164 | 64201201 | bellard | static struct {
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165 | 64201201 | bellard | /* IDs */
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166 | 64201201 | bellard | uint32_t veni_devi;
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167 | 64201201 | bellard | uint32_t revi;
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168 | 64201201 | bellard | /* Control and status */
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169 | 64201201 | bellard | uint32_t gcsr;
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170 | 64201201 | bellard | uint32_t xcfr;
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171 | 64201201 | bellard | uint32_t ct32;
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172 | 64201201 | bellard | uint32_t mcsr;
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173 | 64201201 | bellard | /* General purpose registers */
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174 | 64201201 | bellard | uint32_t gprg[6];
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175 | 64201201 | bellard | /* Exceptions */
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176 | 64201201 | bellard | uint32_t feen;
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177 | 64201201 | bellard | uint32_t fest;
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178 | 64201201 | bellard | uint32_t fema;
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179 | 64201201 | bellard | uint32_t fecl;
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180 | 64201201 | bellard | uint32_t eeen;
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181 | 64201201 | bellard | uint32_t eest;
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182 | 64201201 | bellard | uint32_t eecl;
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183 | 64201201 | bellard | uint32_t eeint;
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184 | 64201201 | bellard | uint32_t eemck0;
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185 | 64201201 | bellard | uint32_t eemck1;
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186 | 64201201 | bellard | /* Error diagnostic */
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187 | 64201201 | bellard | } XCSR;
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188 | 64201201 | bellard | |
189 | 36081602 | j_mayer | static void PPC_XCSR_writeb (void *opaque,
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190 | 36081602 | j_mayer | target_phys_addr_t addr, uint32_t value)
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191 | 64201201 | bellard | {
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192 | aae9366a | j_mayer | printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
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193 | 64201201 | bellard | }
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194 | 64201201 | bellard | |
195 | 36081602 | j_mayer | static void PPC_XCSR_writew (void *opaque,
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196 | 36081602 | j_mayer | target_phys_addr_t addr, uint32_t value)
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197 | 9a64fbe4 | bellard | {
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198 | f658b4db | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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199 | 64201201 | bellard | value = bswap16(value);
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200 | f658b4db | bellard | #endif
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201 | aae9366a | j_mayer | printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value); |
202 | 9a64fbe4 | bellard | } |
203 | 9a64fbe4 | bellard | |
204 | 36081602 | j_mayer | static void PPC_XCSR_writel (void *opaque, |
205 | 36081602 | j_mayer | target_phys_addr_t addr, uint32_t value) |
206 | 9a64fbe4 | bellard | { |
207 | f658b4db | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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208 | 64201201 | bellard | value = bswap32(value); |
209 | f658b4db | bellard | #endif
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210 | aae9366a | j_mayer | printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value); |
211 | 9a64fbe4 | bellard | } |
212 | 9a64fbe4 | bellard | |
213 | a4193c8a | bellard | static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr) |
214 | 64201201 | bellard | { |
215 | 64201201 | bellard | uint32_t retval = 0;
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216 | 9a64fbe4 | bellard | |
217 | aae9366a | j_mayer | printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval); |
218 | 9a64fbe4 | bellard | |
219 | 64201201 | bellard | return retval;
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220 | 64201201 | bellard | } |
221 | 64201201 | bellard | |
222 | a4193c8a | bellard | static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr) |
223 | 9a64fbe4 | bellard | { |
224 | 64201201 | bellard | uint32_t retval = 0;
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225 | 64201201 | bellard | |
226 | aae9366a | j_mayer | printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval); |
227 | 64201201 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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228 | 64201201 | bellard | retval = bswap16(retval); |
229 | 64201201 | bellard | #endif
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230 | 64201201 | bellard | |
231 | 64201201 | bellard | return retval;
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232 | 9a64fbe4 | bellard | } |
233 | 9a64fbe4 | bellard | |
234 | a4193c8a | bellard | static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr) |
235 | 9a64fbe4 | bellard | { |
236 | 9a64fbe4 | bellard | uint32_t retval = 0;
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237 | 9a64fbe4 | bellard | |
238 | aae9366a | j_mayer | printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval); |
239 | 64201201 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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240 | 64201201 | bellard | retval = bswap32(retval); |
241 | 64201201 | bellard | #endif
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242 | 9a64fbe4 | bellard | |
243 | 9a64fbe4 | bellard | return retval;
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244 | 9a64fbe4 | bellard | } |
245 | 9a64fbe4 | bellard | |
246 | 64201201 | bellard | static CPUWriteMemoryFunc *PPC_XCSR_write[] = {
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247 | 64201201 | bellard | &PPC_XCSR_writeb, |
248 | 64201201 | bellard | &PPC_XCSR_writew, |
249 | 64201201 | bellard | &PPC_XCSR_writel, |
250 | 9a64fbe4 | bellard | }; |
251 | 9a64fbe4 | bellard | |
252 | 64201201 | bellard | static CPUReadMemoryFunc *PPC_XCSR_read[] = {
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253 | 64201201 | bellard | &PPC_XCSR_readb, |
254 | 64201201 | bellard | &PPC_XCSR_readw, |
255 | 64201201 | bellard | &PPC_XCSR_readl, |
256 | 9a64fbe4 | bellard | }; |
257 | b6b8bd18 | bellard | #endif
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258 | 9a64fbe4 | bellard | |
259 | 64201201 | bellard | /* Fake super-io ports for PREP platform (Intel 82378ZB) */
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260 | 64201201 | bellard | typedef struct sysctrl_t { |
261 | c4781a51 | j_mayer | qemu_irq reset_irq; |
262 | 64201201 | bellard | m48t59_t *nvram; |
263 | 64201201 | bellard | uint8_t state; |
264 | 64201201 | bellard | uint8_t syscontrol; |
265 | 64201201 | bellard | uint8_t fake_io[2];
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266 | da9b266b | bellard | int contiguous_map;
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267 | fb3444b8 | bellard | int endian;
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268 | 64201201 | bellard | } sysctrl_t; |
269 | 9a64fbe4 | bellard | |
270 | 64201201 | bellard | enum {
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271 | 64201201 | bellard | STATE_HARDFILE = 0x01,
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272 | 9a64fbe4 | bellard | }; |
273 | 9a64fbe4 | bellard | |
274 | 64201201 | bellard | static sysctrl_t *sysctrl;
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275 | 9a64fbe4 | bellard | |
276 | a541f297 | bellard | static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val) |
277 | 9a64fbe4 | bellard | { |
278 | 64201201 | bellard | sysctrl_t *sysctrl = opaque; |
279 | 64201201 | bellard | |
280 | aae9366a | j_mayer | PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE, |
281 | aae9366a | j_mayer | val); |
282 | 64201201 | bellard | sysctrl->fake_io[addr - 0x0398] = val;
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283 | 9a64fbe4 | bellard | } |
284 | 9a64fbe4 | bellard | |
285 | a541f297 | bellard | static uint32_t PREP_io_read (void *opaque, uint32_t addr) |
286 | 9a64fbe4 | bellard | { |
287 | 64201201 | bellard | sysctrl_t *sysctrl = opaque; |
288 | 9a64fbe4 | bellard | |
289 | aae9366a | j_mayer | PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE, |
290 | 64201201 | bellard | sysctrl->fake_io[addr - 0x0398]);
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291 | 64201201 | bellard | return sysctrl->fake_io[addr - 0x0398]; |
292 | 64201201 | bellard | } |
293 | 9a64fbe4 | bellard | |
294 | a541f297 | bellard | static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) |
295 | 9a64fbe4 | bellard | { |
296 | 64201201 | bellard | sysctrl_t *sysctrl = opaque; |
297 | 64201201 | bellard | |
298 | aae9366a | j_mayer | PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", |
299 | aae9366a | j_mayer | addr - PPC_IO_BASE, val); |
300 | 9a64fbe4 | bellard | switch (addr) {
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301 | 9a64fbe4 | bellard | case 0x0092: |
302 | 9a64fbe4 | bellard | /* Special port 92 */
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303 | 9a64fbe4 | bellard | /* Check soft reset asked */
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304 | 64201201 | bellard | if (val & 0x01) { |
305 | c4781a51 | j_mayer | qemu_irq_raise(sysctrl->reset_irq); |
306 | c4781a51 | j_mayer | } else {
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307 | c4781a51 | j_mayer | qemu_irq_lower(sysctrl->reset_irq); |
308 | 9a64fbe4 | bellard | } |
309 | 9a64fbe4 | bellard | /* Check LE mode */
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310 | 64201201 | bellard | if (val & 0x02) { |
311 | fb3444b8 | bellard | sysctrl->endian = 1;
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312 | fb3444b8 | bellard | } else {
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313 | fb3444b8 | bellard | sysctrl->endian = 0;
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314 | 9a64fbe4 | bellard | } |
315 | 9a64fbe4 | bellard | break;
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316 | 64201201 | bellard | case 0x0800: |
317 | 64201201 | bellard | /* Motorola CPU configuration register : read-only */
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318 | 64201201 | bellard | break;
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319 | 64201201 | bellard | case 0x0802: |
320 | 64201201 | bellard | /* Motorola base module feature register : read-only */
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321 | 64201201 | bellard | break;
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322 | 64201201 | bellard | case 0x0803: |
323 | 64201201 | bellard | /* Motorola base module status register : read-only */
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324 | 64201201 | bellard | break;
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325 | 9a64fbe4 | bellard | case 0x0808: |
326 | 64201201 | bellard | /* Hardfile light register */
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327 | 64201201 | bellard | if (val & 1) |
328 | 64201201 | bellard | sysctrl->state |= STATE_HARDFILE; |
329 | 64201201 | bellard | else
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330 | 64201201 | bellard | sysctrl->state &= ~STATE_HARDFILE; |
331 | 9a64fbe4 | bellard | break;
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332 | 9a64fbe4 | bellard | case 0x0810: |
333 | 9a64fbe4 | bellard | /* Password protect 1 register */
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334 | 64201201 | bellard | if (sysctrl->nvram != NULL) |
335 | 64201201 | bellard | m48t59_toggle_lock(sysctrl->nvram, 1);
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336 | 9a64fbe4 | bellard | break;
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337 | 9a64fbe4 | bellard | case 0x0812: |
338 | 9a64fbe4 | bellard | /* Password protect 2 register */
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339 | 64201201 | bellard | if (sysctrl->nvram != NULL) |
340 | 64201201 | bellard | m48t59_toggle_lock(sysctrl->nvram, 2);
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341 | 9a64fbe4 | bellard | break;
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342 | 9a64fbe4 | bellard | case 0x0814: |
343 | 64201201 | bellard | /* L2 invalidate register */
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344 | c68ea704 | bellard | // tlb_flush(first_cpu, 1);
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345 | 9a64fbe4 | bellard | break;
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346 | 9a64fbe4 | bellard | case 0x081C: |
347 | 9a64fbe4 | bellard | /* system control register */
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348 | 64201201 | bellard | sysctrl->syscontrol = val & 0x0F;
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349 | 9a64fbe4 | bellard | break;
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350 | 9a64fbe4 | bellard | case 0x0850: |
351 | 9a64fbe4 | bellard | /* I/O map type register */
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352 | da9b266b | bellard | sysctrl->contiguous_map = val & 0x01;
|
353 | 9a64fbe4 | bellard | break;
|
354 | 9a64fbe4 | bellard | default:
|
355 | aae9366a | j_mayer | printf("ERROR: unaffected IO port write: %04" PRIx32
|
356 | aae9366a | j_mayer | " => %02" PRIx32"\n", addr, val); |
357 | 9a64fbe4 | bellard | break;
|
358 | 9a64fbe4 | bellard | } |
359 | 9a64fbe4 | bellard | } |
360 | 9a64fbe4 | bellard | |
361 | a541f297 | bellard | static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) |
362 | 9a64fbe4 | bellard | { |
363 | 64201201 | bellard | sysctrl_t *sysctrl = opaque; |
364 | 9a64fbe4 | bellard | uint32_t retval = 0xFF;
|
365 | 9a64fbe4 | bellard | |
366 | 9a64fbe4 | bellard | switch (addr) {
|
367 | 9a64fbe4 | bellard | case 0x0092: |
368 | 9a64fbe4 | bellard | /* Special port 92 */
|
369 | 64201201 | bellard | retval = 0x00;
|
370 | 64201201 | bellard | break;
|
371 | 64201201 | bellard | case 0x0800: |
372 | 64201201 | bellard | /* Motorola CPU configuration register */
|
373 | 64201201 | bellard | retval = 0xEF; /* MPC750 */ |
374 | 64201201 | bellard | break;
|
375 | 64201201 | bellard | case 0x0802: |
376 | 64201201 | bellard | /* Motorola Base module feature register */
|
377 | 64201201 | bellard | retval = 0xAD; /* No ESCC, PMC slot neither ethernet */ |
378 | 64201201 | bellard | break;
|
379 | 64201201 | bellard | case 0x0803: |
380 | 64201201 | bellard | /* Motorola base module status register */
|
381 | 64201201 | bellard | retval = 0xE0; /* Standard MPC750 */ |
382 | 9a64fbe4 | bellard | break;
|
383 | 9a64fbe4 | bellard | case 0x080C: |
384 | 9a64fbe4 | bellard | /* Equipment present register:
|
385 | 9a64fbe4 | bellard | * no L2 cache
|
386 | 9a64fbe4 | bellard | * no upgrade processor
|
387 | 9a64fbe4 | bellard | * no cards in PCI slots
|
388 | 9a64fbe4 | bellard | * SCSI fuse is bad
|
389 | 9a64fbe4 | bellard | */
|
390 | 64201201 | bellard | retval = 0x3C;
|
391 | 64201201 | bellard | break;
|
392 | 64201201 | bellard | case 0x0810: |
393 | 64201201 | bellard | /* Motorola base module extended feature register */
|
394 | 64201201 | bellard | retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */ |
395 | 9a64fbe4 | bellard | break;
|
396 | da9b266b | bellard | case 0x0814: |
397 | da9b266b | bellard | /* L2 invalidate: don't care */
|
398 | da9b266b | bellard | break;
|
399 | 9a64fbe4 | bellard | case 0x0818: |
400 | 9a64fbe4 | bellard | /* Keylock */
|
401 | 9a64fbe4 | bellard | retval = 0x00;
|
402 | 9a64fbe4 | bellard | break;
|
403 | 9a64fbe4 | bellard | case 0x081C: |
404 | 9a64fbe4 | bellard | /* system control register
|
405 | 9a64fbe4 | bellard | * 7 - 6 / 1 - 0: L2 cache enable
|
406 | 9a64fbe4 | bellard | */
|
407 | 64201201 | bellard | retval = sysctrl->syscontrol; |
408 | 9a64fbe4 | bellard | break;
|
409 | 9a64fbe4 | bellard | case 0x0823: |
410 | 9a64fbe4 | bellard | /* */
|
411 | 9a64fbe4 | bellard | retval = 0x03; /* no L2 cache */ |
412 | 9a64fbe4 | bellard | break;
|
413 | 9a64fbe4 | bellard | case 0x0850: |
414 | 9a64fbe4 | bellard | /* I/O map type register */
|
415 | da9b266b | bellard | retval = sysctrl->contiguous_map; |
416 | 9a64fbe4 | bellard | break;
|
417 | 9a64fbe4 | bellard | default:
|
418 | aae9366a | j_mayer | printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr); |
419 | 9a64fbe4 | bellard | break;
|
420 | 9a64fbe4 | bellard | } |
421 | aae9366a | j_mayer | PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", |
422 | aae9366a | j_mayer | addr - PPC_IO_BASE, retval); |
423 | 9a64fbe4 | bellard | |
424 | 9a64fbe4 | bellard | return retval;
|
425 | 9a64fbe4 | bellard | } |
426 | 9a64fbe4 | bellard | |
427 | b068d6a7 | j_mayer | static always_inline target_phys_addr_t prep_IO_address (sysctrl_t *sysctrl,
|
428 | b068d6a7 | j_mayer | target_phys_addr_t |
429 | b068d6a7 | j_mayer | addr) |
430 | da9b266b | bellard | { |
431 | da9b266b | bellard | if (sysctrl->contiguous_map == 0) { |
432 | da9b266b | bellard | /* 64 KB contiguous space for IOs */
|
433 | da9b266b | bellard | addr &= 0xFFFF;
|
434 | da9b266b | bellard | } else {
|
435 | da9b266b | bellard | /* 8 MB non-contiguous space for IOs */
|
436 | da9b266b | bellard | addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7); |
437 | da9b266b | bellard | } |
438 | da9b266b | bellard | |
439 | da9b266b | bellard | return addr;
|
440 | da9b266b | bellard | } |
441 | da9b266b | bellard | |
442 | da9b266b | bellard | static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr, |
443 | da9b266b | bellard | uint32_t value) |
444 | da9b266b | bellard | { |
445 | da9b266b | bellard | sysctrl_t *sysctrl = opaque; |
446 | da9b266b | bellard | |
447 | da9b266b | bellard | addr = prep_IO_address(sysctrl, addr); |
448 | da9b266b | bellard | cpu_outb(NULL, addr, value);
|
449 | da9b266b | bellard | } |
450 | da9b266b | bellard | |
451 | da9b266b | bellard | static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr) |
452 | da9b266b | bellard | { |
453 | da9b266b | bellard | sysctrl_t *sysctrl = opaque; |
454 | da9b266b | bellard | uint32_t ret; |
455 | da9b266b | bellard | |
456 | da9b266b | bellard | addr = prep_IO_address(sysctrl, addr); |
457 | da9b266b | bellard | ret = cpu_inb(NULL, addr);
|
458 | da9b266b | bellard | |
459 | da9b266b | bellard | return ret;
|
460 | da9b266b | bellard | } |
461 | da9b266b | bellard | |
462 | da9b266b | bellard | static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr, |
463 | da9b266b | bellard | uint32_t value) |
464 | da9b266b | bellard | { |
465 | da9b266b | bellard | sysctrl_t *sysctrl = opaque; |
466 | da9b266b | bellard | |
467 | da9b266b | bellard | addr = prep_IO_address(sysctrl, addr); |
468 | da9b266b | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
469 | da9b266b | bellard | value = bswap16(value); |
470 | da9b266b | bellard | #endif
|
471 | aae9366a | j_mayer | PPC_IO_DPRINTF("0x" PADDRX " => 0x%08" PRIx32 "\n", addr, value); |
472 | da9b266b | bellard | cpu_outw(NULL, addr, value);
|
473 | da9b266b | bellard | } |
474 | da9b266b | bellard | |
475 | da9b266b | bellard | static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr) |
476 | da9b266b | bellard | { |
477 | da9b266b | bellard | sysctrl_t *sysctrl = opaque; |
478 | da9b266b | bellard | uint32_t ret; |
479 | da9b266b | bellard | |
480 | da9b266b | bellard | addr = prep_IO_address(sysctrl, addr); |
481 | da9b266b | bellard | ret = cpu_inw(NULL, addr);
|
482 | da9b266b | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
483 | da9b266b | bellard | ret = bswap16(ret); |
484 | da9b266b | bellard | #endif
|
485 | aae9366a | j_mayer | PPC_IO_DPRINTF("0x" PADDRX " <= 0x%08" PRIx32 "\n", addr, ret); |
486 | da9b266b | bellard | |
487 | da9b266b | bellard | return ret;
|
488 | da9b266b | bellard | } |
489 | da9b266b | bellard | |
490 | da9b266b | bellard | static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr, |
491 | da9b266b | bellard | uint32_t value) |
492 | da9b266b | bellard | { |
493 | da9b266b | bellard | sysctrl_t *sysctrl = opaque; |
494 | da9b266b | bellard | |
495 | da9b266b | bellard | addr = prep_IO_address(sysctrl, addr); |
496 | da9b266b | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
497 | da9b266b | bellard | value = bswap32(value); |
498 | da9b266b | bellard | #endif
|
499 | aae9366a | j_mayer | PPC_IO_DPRINTF("0x" PADDRX " => 0x%08" PRIx32 "\n", addr, value); |
500 | da9b266b | bellard | cpu_outl(NULL, addr, value);
|
501 | da9b266b | bellard | } |
502 | da9b266b | bellard | |
503 | da9b266b | bellard | static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr) |
504 | da9b266b | bellard | { |
505 | da9b266b | bellard | sysctrl_t *sysctrl = opaque; |
506 | da9b266b | bellard | uint32_t ret; |
507 | da9b266b | bellard | |
508 | da9b266b | bellard | addr = prep_IO_address(sysctrl, addr); |
509 | da9b266b | bellard | ret = cpu_inl(NULL, addr);
|
510 | da9b266b | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
511 | da9b266b | bellard | ret = bswap32(ret); |
512 | da9b266b | bellard | #endif
|
513 | aae9366a | j_mayer | PPC_IO_DPRINTF("0x" PADDRX " <= 0x%08" PRIx32 "\n", addr, ret); |
514 | da9b266b | bellard | |
515 | da9b266b | bellard | return ret;
|
516 | da9b266b | bellard | } |
517 | da9b266b | bellard | |
518 | b1d8e52e | blueswir1 | static CPUWriteMemoryFunc *PPC_prep_io_write[] = {
|
519 | da9b266b | bellard | &PPC_prep_io_writeb, |
520 | da9b266b | bellard | &PPC_prep_io_writew, |
521 | da9b266b | bellard | &PPC_prep_io_writel, |
522 | da9b266b | bellard | }; |
523 | da9b266b | bellard | |
524 | b1d8e52e | blueswir1 | static CPUReadMemoryFunc *PPC_prep_io_read[] = {
|
525 | da9b266b | bellard | &PPC_prep_io_readb, |
526 | da9b266b | bellard | &PPC_prep_io_readw, |
527 | da9b266b | bellard | &PPC_prep_io_readl, |
528 | da9b266b | bellard | }; |
529 | da9b266b | bellard | |
530 | 64201201 | bellard | #define NVRAM_SIZE 0x2000 |
531 | a541f297 | bellard | |
532 | 26aa7d72 | bellard | /* PowerPC PREP hardware initialisation */
|
533 | 00f82b8a | aurel32 | static void ppc_prep_init (ram_addr_t ram_size, int vga_ram_size, |
534 | 3023f332 | aliguori | const char *boot_device, |
535 | b881c2c6 | blueswir1 | const char *kernel_filename, |
536 | 94fc95cd | j_mayer | const char *kernel_cmdline, |
537 | 94fc95cd | j_mayer | const char *initrd_filename, |
538 | 94fc95cd | j_mayer | const char *cpu_model) |
539 | a541f297 | bellard | { |
540 | 0d913fdb | j_mayer | CPUState *env = NULL, *envs[MAX_CPUS];
|
541 | a541f297 | bellard | char buf[1024]; |
542 | 3cbee15b | j_mayer | nvram_t nvram; |
543 | 3cbee15b | j_mayer | m48t59_t *m48t59; |
544 | a541f297 | bellard | int PPC_io_memory;
|
545 | 4157a662 | bellard | int linux_boot, i, nb_nics1, bios_size;
|
546 | cf9c147c | blueswir1 | ram_addr_t ram_offset, vga_ram_offset, bios_offset; |
547 | 64201201 | bellard | uint32_t kernel_base, kernel_size, initrd_base, initrd_size; |
548 | 46e50e9d | bellard | PCIBus *pci_bus; |
549 | d537cf6c | pbrook | qemu_irq *i8259; |
550 | 28c5af54 | j_mayer | int ppc_boot_device;
|
551 | e4bcb14c | ths | int index;
|
552 | e4bcb14c | ths | BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
553 | e4bcb14c | ths | BlockDriverState *fd[MAX_FD]; |
554 | 64201201 | bellard | |
555 | 64201201 | bellard | sysctrl = qemu_mallocz(sizeof(sysctrl_t));
|
556 | a541f297 | bellard | |
557 | a541f297 | bellard | linux_boot = (kernel_filename != NULL);
|
558 | 0a032cbe | j_mayer | |
559 | c68ea704 | bellard | /* init CPUs */
|
560 | 94fc95cd | j_mayer | if (cpu_model == NULL) |
561 | d12f4c38 | j_mayer | cpu_model = "default";
|
562 | fe33cc71 | j_mayer | for (i = 0; i < smp_cpus; i++) { |
563 | aaed909a | bellard | env = cpu_init(cpu_model); |
564 | aaed909a | bellard | if (!env) {
|
565 | aaed909a | bellard | fprintf(stderr, "Unable to find PowerPC CPU definition\n");
|
566 | aaed909a | bellard | exit(1);
|
567 | aaed909a | bellard | } |
568 | 4018bae9 | j_mayer | if (env->flags & POWERPC_FLAG_RTC_CLK) {
|
569 | 4018bae9 | j_mayer | /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
|
570 | 4018bae9 | j_mayer | cpu_ppc_tb_init(env, 7812500UL);
|
571 | 4018bae9 | j_mayer | } else {
|
572 | 4018bae9 | j_mayer | /* Set time-base frequency to 100 Mhz */
|
573 | 4018bae9 | j_mayer | cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); |
574 | 4018bae9 | j_mayer | } |
575 | fe33cc71 | j_mayer | qemu_register_reset(&cpu_ppc_reset, env); |
576 | fe33cc71 | j_mayer | envs[i] = env; |
577 | fe33cc71 | j_mayer | } |
578 | a541f297 | bellard | |
579 | a541f297 | bellard | /* allocate RAM */
|
580 | cf9c147c | blueswir1 | ram_offset = qemu_ram_alloc(ram_size); |
581 | cf9c147c | blueswir1 | cpu_register_physical_memory(0, ram_size, ram_offset);
|
582 | cf9c147c | blueswir1 | |
583 | cf9c147c | blueswir1 | /* allocate VGA RAM */
|
584 | cf9c147c | blueswir1 | vga_ram_offset = qemu_ram_alloc(vga_ram_size); |
585 | 64201201 | bellard | |
586 | 64201201 | bellard | /* allocate and load BIOS */
|
587 | cf9c147c | blueswir1 | bios_offset = qemu_ram_alloc(BIOS_SIZE); |
588 | 1192dad8 | j_mayer | if (bios_name == NULL) |
589 | 1192dad8 | j_mayer | bios_name = BIOS_FILENAME; |
590 | 1192dad8 | j_mayer | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
591 | 4157a662 | bellard | bios_size = load_image(buf, phys_ram_base + bios_offset); |
592 | 4157a662 | bellard | if (bios_size < 0 || bios_size > BIOS_SIZE) { |
593 | 4a057712 | j_mayer | cpu_abort(env, "qemu: could not load PPC PREP bios '%s'\n", buf);
|
594 | 64201201 | bellard | exit(1);
|
595 | 64201201 | bellard | } |
596 | 4c823cff | j_mayer | if (env->nip < 0xFFF80000 && bios_size < 0x00100000) { |
597 | 4c823cff | j_mayer | cpu_abort(env, "PowerPC 601 / 620 / 970 need a 1MB BIOS\n");
|
598 | 4c823cff | j_mayer | } |
599 | 4157a662 | bellard | bios_size = (bios_size + 0xfff) & ~0xfff; |
600 | 4a057712 | j_mayer | cpu_register_physical_memory((uint32_t)(-bios_size), |
601 | 4157a662 | bellard | bios_size, bios_offset | IO_MEM_ROM); |
602 | 26aa7d72 | bellard | |
603 | a541f297 | bellard | if (linux_boot) {
|
604 | 64201201 | bellard | kernel_base = KERNEL_LOAD_ADDR; |
605 | a541f297 | bellard | /* now we can load the kernel */
|
606 | 64201201 | bellard | kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base); |
607 | 64201201 | bellard | if (kernel_size < 0) { |
608 | 4a057712 | j_mayer | cpu_abort(env, "qemu: could not load kernel '%s'\n",
|
609 | 4a057712 | j_mayer | kernel_filename); |
610 | a541f297 | bellard | exit(1);
|
611 | a541f297 | bellard | } |
612 | a541f297 | bellard | /* load initrd */
|
613 | a541f297 | bellard | if (initrd_filename) {
|
614 | 64201201 | bellard | initrd_base = INITRD_LOAD_ADDR; |
615 | 64201201 | bellard | initrd_size = load_image(initrd_filename, |
616 | 64201201 | bellard | phys_ram_base + initrd_base); |
617 | a541f297 | bellard | if (initrd_size < 0) { |
618 | 4a057712 | j_mayer | cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
|
619 | 4a057712 | j_mayer | initrd_filename); |
620 | a541f297 | bellard | exit(1);
|
621 | a541f297 | bellard | } |
622 | 64201201 | bellard | } else {
|
623 | 64201201 | bellard | initrd_base = 0;
|
624 | 64201201 | bellard | initrd_size = 0;
|
625 | a541f297 | bellard | } |
626 | 6ac0e82d | balrog | ppc_boot_device = 'm';
|
627 | a541f297 | bellard | } else {
|
628 | 64201201 | bellard | kernel_base = 0;
|
629 | 64201201 | bellard | kernel_size = 0;
|
630 | 64201201 | bellard | initrd_base = 0;
|
631 | 64201201 | bellard | initrd_size = 0;
|
632 | 28c5af54 | j_mayer | ppc_boot_device = '\0';
|
633 | 28c5af54 | j_mayer | /* For now, OHW cannot boot from the network. */
|
634 | 0d913fdb | j_mayer | for (i = 0; boot_device[i] != '\0'; i++) { |
635 | 0d913fdb | j_mayer | if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { |
636 | 0d913fdb | j_mayer | ppc_boot_device = boot_device[i]; |
637 | 28c5af54 | j_mayer | break;
|
638 | 0d913fdb | j_mayer | } |
639 | 28c5af54 | j_mayer | } |
640 | 28c5af54 | j_mayer | if (ppc_boot_device == '\0') { |
641 | 28c5af54 | j_mayer | fprintf(stderr, "No valid boot device for Mac99 machine\n");
|
642 | 28c5af54 | j_mayer | exit(1);
|
643 | 28c5af54 | j_mayer | } |
644 | a541f297 | bellard | } |
645 | a541f297 | bellard | |
646 | 64201201 | bellard | isa_mem_base = 0xc0000000;
|
647 | dd37a5e4 | j_mayer | if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
|
648 | dd37a5e4 | j_mayer | cpu_abort(env, "Only 6xx bus is supported on PREP machine\n");
|
649 | dd37a5e4 | j_mayer | exit(1);
|
650 | dd37a5e4 | j_mayer | } |
651 | 24be5ae3 | j_mayer | i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]); |
652 | d537cf6c | pbrook | pci_bus = pci_prep_init(i8259); |
653 | da9b266b | bellard | // pci_bus = i440fx_init();
|
654 | da9b266b | bellard | /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
|
655 | da9b266b | bellard | PPC_io_memory = cpu_register_io_memory(0, PPC_prep_io_read,
|
656 | da9b266b | bellard | PPC_prep_io_write, sysctrl); |
657 | da9b266b | bellard | cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory); |
658 | 64201201 | bellard | |
659 | a541f297 | bellard | /* init basic PC hardware */
|
660 | cf9c147c | blueswir1 | pci_vga_init(pci_bus, phys_ram_base + vga_ram_offset, |
661 | cf9c147c | blueswir1 | vga_ram_offset, vga_ram_size, 0, 0); |
662 | 64201201 | bellard | // openpic = openpic_init(0x00000000, 0xF0000000, 1);
|
663 | d537cf6c | pbrook | // pit = pit_init(0x40, i8259[0]);
|
664 | 42fc73a1 | aurel32 | rtc_init(0x70, i8259[8], 2000); |
665 | a541f297 | bellard | |
666 | b6cd0ea1 | aurel32 | serial_init(0x3f8, i8259[4], 115200, serial_hds[0]); |
667 | a541f297 | bellard | nb_nics1 = nb_nics; |
668 | a541f297 | bellard | if (nb_nics1 > NE2000_NB_MAX)
|
669 | a541f297 | bellard | nb_nics1 = NE2000_NB_MAX; |
670 | a541f297 | bellard | for(i = 0; i < nb_nics1; i++) { |
671 | 5652ef78 | aurel32 | if (nd_table[i].model == NULL) { |
672 | 5652ef78 | aurel32 | nd_table[i].model = "ne2k_isa";
|
673 | 5652ef78 | aurel32 | } |
674 | 5652ef78 | aurel32 | if (strcmp(nd_table[i].model, "ne2k_isa") == 0) { |
675 | d537cf6c | pbrook | isa_ne2000_init(ne2000_io[i], i8259[ne2000_irq[i]], &nd_table[i]); |
676 | a41b2ff2 | pbrook | } else {
|
677 | cb457d76 | aliguori | pci_nic_init(pci_bus, &nd_table[i], -1, "ne2k_pci"); |
678 | a41b2ff2 | pbrook | } |
679 | a541f297 | bellard | } |
680 | a541f297 | bellard | |
681 | e4bcb14c | ths | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
|
682 | e4bcb14c | ths | fprintf(stderr, "qemu: too many IDE bus\n");
|
683 | e4bcb14c | ths | exit(1);
|
684 | e4bcb14c | ths | } |
685 | e4bcb14c | ths | |
686 | e4bcb14c | ths | for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { |
687 | e4bcb14c | ths | index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); |
688 | e4bcb14c | ths | if (index != -1) |
689 | e4bcb14c | ths | hd[i] = drives_table[index].bdrv; |
690 | e4bcb14c | ths | else
|
691 | e4bcb14c | ths | hd[i] = NULL;
|
692 | e4bcb14c | ths | } |
693 | e4bcb14c | ths | |
694 | e4bcb14c | ths | for(i = 0; i < MAX_IDE_BUS; i++) { |
695 | d537cf6c | pbrook | isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]], |
696 | e4bcb14c | ths | hd[2 * i],
|
697 | e4bcb14c | ths | hd[2 * i + 1]); |
698 | a541f297 | bellard | } |
699 | d537cf6c | pbrook | i8042_init(i8259[1], i8259[12], 0x60); |
700 | b6b8bd18 | bellard | DMA_init(1);
|
701 | 64201201 | bellard | // AUD_init();
|
702 | a541f297 | bellard | // SB16_init();
|
703 | a541f297 | bellard | |
704 | e4bcb14c | ths | for(i = 0; i < MAX_FD; i++) { |
705 | e4bcb14c | ths | index = drive_get_index(IF_FLOPPY, 0, i);
|
706 | e4bcb14c | ths | if (index != -1) |
707 | e4bcb14c | ths | fd[i] = drives_table[index].bdrv; |
708 | e4bcb14c | ths | else
|
709 | e4bcb14c | ths | fd[i] = NULL;
|
710 | e4bcb14c | ths | } |
711 | e4bcb14c | ths | fdctrl_init(i8259[6], 2, 0, 0x3f0, fd); |
712 | a541f297 | bellard | |
713 | 64201201 | bellard | /* Register speaker port */
|
714 | 64201201 | bellard | register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL); |
715 | 64201201 | bellard | register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL); |
716 | a541f297 | bellard | /* Register fake IO ports for PREP */
|
717 | c4781a51 | j_mayer | sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET]; |
718 | 64201201 | bellard | register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl); |
719 | 64201201 | bellard | register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl); |
720 | a541f297 | bellard | /* System control ports */
|
721 | 64201201 | bellard | register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl); |
722 | 64201201 | bellard | register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl); |
723 | 64201201 | bellard | register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl); |
724 | 64201201 | bellard | register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl); |
725 | 64201201 | bellard | /* PCI intack location */
|
726 | 64201201 | bellard | PPC_io_memory = cpu_register_io_memory(0, PPC_intack_read,
|
727 | a4193c8a | bellard | PPC_intack_write, NULL);
|
728 | a541f297 | bellard | cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory); |
729 | 64201201 | bellard | /* PowerPC control and status register group */
|
730 | b6b8bd18 | bellard | #if 0
|
731 | 36081602 | j_mayer | PPC_io_memory = cpu_register_io_memory(0, PPC_XCSR_read, PPC_XCSR_write,
|
732 | 36081602 | j_mayer | NULL);
|
733 | 64201201 | bellard | cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
|
734 | b6b8bd18 | bellard | #endif
|
735 | a541f297 | bellard | |
736 | 0d92ed30 | pbrook | if (usb_enabled) {
|
737 | e24ad6f1 | pbrook | usb_ohci_init_pci(pci_bus, 3, -1); |
738 | 0d92ed30 | pbrook | } |
739 | 0d92ed30 | pbrook | |
740 | 3cbee15b | j_mayer | m48t59 = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59); |
741 | 3cbee15b | j_mayer | if (m48t59 == NULL) |
742 | 64201201 | bellard | return;
|
743 | 3cbee15b | j_mayer | sysctrl->nvram = m48t59; |
744 | 64201201 | bellard | |
745 | 64201201 | bellard | /* Initialise NVRAM */
|
746 | 3cbee15b | j_mayer | nvram.opaque = m48t59; |
747 | 3cbee15b | j_mayer | nvram.read_fn = &m48t59_read; |
748 | 3cbee15b | j_mayer | nvram.write_fn = &m48t59_write; |
749 | 6ac0e82d | balrog | PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device,
|
750 | 64201201 | bellard | kernel_base, kernel_size, |
751 | b6b8bd18 | bellard | kernel_cmdline, |
752 | 64201201 | bellard | initrd_base, initrd_size, |
753 | 64201201 | bellard | /* XXX: need an option to load a NVRAM image */
|
754 | b6b8bd18 | bellard | 0,
|
755 | b6b8bd18 | bellard | graphic_width, graphic_height, graphic_depth); |
756 | c0e564d5 | bellard | |
757 | c0e564d5 | bellard | /* Special port to get debug messages from Open-Firmware */
|
758 | c0e564d5 | bellard | register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL); |
759 | a541f297 | bellard | } |
760 | c0e564d5 | bellard | |
761 | c0e564d5 | bellard | QEMUMachine prep_machine = { |
762 | 4b32e168 | aliguori | .name = "prep",
|
763 | 4b32e168 | aliguori | .desc = "PowerPC PREP platform",
|
764 | 4b32e168 | aliguori | .init = ppc_prep_init, |
765 | 4b32e168 | aliguori | .ram_require = BIOS_SIZE + VGA_RAM_SIZE, |
766 | 3d878caa | balrog | .max_cpus = MAX_CPUS, |
767 | c0e564d5 | bellard | }; |