root / target-ppc / kvm.c @ ba5e5090
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1 | d76d1650 | aurel32 | /*
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2 | d76d1650 | aurel32 | * PowerPC implementation of KVM hooks
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3 | d76d1650 | aurel32 | *
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4 | d76d1650 | aurel32 | * Copyright IBM Corp. 2007
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5 | d76d1650 | aurel32 | *
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6 | d76d1650 | aurel32 | * Authors:
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7 | d76d1650 | aurel32 | * Jerone Young <jyoung5@us.ibm.com>
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8 | d76d1650 | aurel32 | * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
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9 | d76d1650 | aurel32 | * Hollis Blanchard <hollisb@us.ibm.com>
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10 | d76d1650 | aurel32 | *
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11 | d76d1650 | aurel32 | * This work is licensed under the terms of the GNU GPL, version 2 or later.
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12 | d76d1650 | aurel32 | * See the COPYING file in the top-level directory.
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13 | d76d1650 | aurel32 | *
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14 | d76d1650 | aurel32 | */
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15 | d76d1650 | aurel32 | |
16 | d76d1650 | aurel32 | #include <sys/types.h> |
17 | d76d1650 | aurel32 | #include <sys/ioctl.h> |
18 | d76d1650 | aurel32 | #include <sys/mman.h> |
19 | d76d1650 | aurel32 | |
20 | d76d1650 | aurel32 | #include <linux/kvm.h> |
21 | d76d1650 | aurel32 | |
22 | d76d1650 | aurel32 | #include "qemu-common.h" |
23 | d76d1650 | aurel32 | #include "qemu-timer.h" |
24 | d76d1650 | aurel32 | #include "sysemu.h" |
25 | d76d1650 | aurel32 | #include "kvm.h" |
26 | d76d1650 | aurel32 | #include "kvm_ppc.h" |
27 | d76d1650 | aurel32 | #include "cpu.h" |
28 | d76d1650 | aurel32 | #include "device_tree.h" |
29 | d76d1650 | aurel32 | |
30 | d76d1650 | aurel32 | //#define DEBUG_KVM
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31 | d76d1650 | aurel32 | |
32 | d76d1650 | aurel32 | #ifdef DEBUG_KVM
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33 | d76d1650 | aurel32 | #define dprintf(fmt, ...) \
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34 | d76d1650 | aurel32 | do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) |
35 | d76d1650 | aurel32 | #else
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36 | d76d1650 | aurel32 | #define dprintf(fmt, ...) \
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37 | d76d1650 | aurel32 | do { } while (0) |
38 | d76d1650 | aurel32 | #endif
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39 | d76d1650 | aurel32 | |
40 | d76d1650 | aurel32 | int kvm_arch_init(KVMState *s, int smp_cpus) |
41 | d76d1650 | aurel32 | { |
42 | d76d1650 | aurel32 | return 0; |
43 | d76d1650 | aurel32 | } |
44 | d76d1650 | aurel32 | |
45 | d76d1650 | aurel32 | int kvm_arch_init_vcpu(CPUState *cenv)
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46 | d76d1650 | aurel32 | { |
47 | 861bbc80 | Alexander Graf | int ret = 0; |
48 | 861bbc80 | Alexander Graf | struct kvm_sregs sregs;
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49 | 861bbc80 | Alexander Graf | |
50 | 861bbc80 | Alexander Graf | sregs.pvr = cenv->spr[SPR_PVR]; |
51 | 861bbc80 | Alexander Graf | ret = kvm_vcpu_ioctl(cenv, KVM_SET_SREGS, &sregs); |
52 | 861bbc80 | Alexander Graf | |
53 | 861bbc80 | Alexander Graf | return ret;
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54 | d76d1650 | aurel32 | } |
55 | d76d1650 | aurel32 | |
56 | caa5af0f | Jan Kiszka | void kvm_arch_reset_vcpu(CPUState *env)
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57 | caa5af0f | Jan Kiszka | { |
58 | caa5af0f | Jan Kiszka | } |
59 | caa5af0f | Jan Kiszka | |
60 | d76d1650 | aurel32 | int kvm_arch_put_registers(CPUState *env)
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61 | d76d1650 | aurel32 | { |
62 | d76d1650 | aurel32 | struct kvm_regs regs;
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63 | d76d1650 | aurel32 | int ret;
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64 | d76d1650 | aurel32 | int i;
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65 | d76d1650 | aurel32 | |
66 | d76d1650 | aurel32 | ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s); |
67 | d76d1650 | aurel32 | if (ret < 0) |
68 | d76d1650 | aurel32 | return ret;
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69 | d76d1650 | aurel32 | |
70 | d76d1650 | aurel32 | regs.ctr = env->ctr; |
71 | d76d1650 | aurel32 | regs.lr = env->lr; |
72 | d76d1650 | aurel32 | regs.xer = env->xer; |
73 | d76d1650 | aurel32 | regs.msr = env->msr; |
74 | d76d1650 | aurel32 | regs.pc = env->nip; |
75 | d76d1650 | aurel32 | |
76 | d76d1650 | aurel32 | regs.srr0 = env->spr[SPR_SRR0]; |
77 | d76d1650 | aurel32 | regs.srr1 = env->spr[SPR_SRR1]; |
78 | d76d1650 | aurel32 | |
79 | d76d1650 | aurel32 | regs.sprg0 = env->spr[SPR_SPRG0]; |
80 | d76d1650 | aurel32 | regs.sprg1 = env->spr[SPR_SPRG1]; |
81 | d76d1650 | aurel32 | regs.sprg2 = env->spr[SPR_SPRG2]; |
82 | d76d1650 | aurel32 | regs.sprg3 = env->spr[SPR_SPRG3]; |
83 | d76d1650 | aurel32 | regs.sprg4 = env->spr[SPR_SPRG4]; |
84 | d76d1650 | aurel32 | regs.sprg5 = env->spr[SPR_SPRG5]; |
85 | d76d1650 | aurel32 | regs.sprg6 = env->spr[SPR_SPRG6]; |
86 | d76d1650 | aurel32 | regs.sprg7 = env->spr[SPR_SPRG7]; |
87 | d76d1650 | aurel32 | |
88 | d76d1650 | aurel32 | for (i = 0;i < 32; i++) |
89 | d76d1650 | aurel32 | regs.gpr[i] = env->gpr[i]; |
90 | d76d1650 | aurel32 | |
91 | d76d1650 | aurel32 | ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, ®s); |
92 | d76d1650 | aurel32 | if (ret < 0) |
93 | d76d1650 | aurel32 | return ret;
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94 | d76d1650 | aurel32 | |
95 | d76d1650 | aurel32 | return ret;
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96 | d76d1650 | aurel32 | } |
97 | d76d1650 | aurel32 | |
98 | d76d1650 | aurel32 | int kvm_arch_get_registers(CPUState *env)
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99 | d76d1650 | aurel32 | { |
100 | d76d1650 | aurel32 | struct kvm_regs regs;
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101 | ba5e5090 | Alexander Graf | struct kvm_sregs sregs;
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102 | d76d1650 | aurel32 | uint32_t i, ret; |
103 | d76d1650 | aurel32 | |
104 | d76d1650 | aurel32 | ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s); |
105 | d76d1650 | aurel32 | if (ret < 0) |
106 | d76d1650 | aurel32 | return ret;
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107 | d76d1650 | aurel32 | |
108 | ba5e5090 | Alexander Graf | ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs); |
109 | ba5e5090 | Alexander Graf | if (ret < 0) |
110 | ba5e5090 | Alexander Graf | return ret;
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111 | ba5e5090 | Alexander Graf | |
112 | d76d1650 | aurel32 | env->ctr = regs.ctr; |
113 | d76d1650 | aurel32 | env->lr = regs.lr; |
114 | d76d1650 | aurel32 | env->xer = regs.xer; |
115 | d76d1650 | aurel32 | env->msr = regs.msr; |
116 | d76d1650 | aurel32 | env->nip = regs.pc; |
117 | d76d1650 | aurel32 | |
118 | d76d1650 | aurel32 | env->spr[SPR_SRR0] = regs.srr0; |
119 | d76d1650 | aurel32 | env->spr[SPR_SRR1] = regs.srr1; |
120 | d76d1650 | aurel32 | |
121 | d76d1650 | aurel32 | env->spr[SPR_SPRG0] = regs.sprg0; |
122 | d76d1650 | aurel32 | env->spr[SPR_SPRG1] = regs.sprg1; |
123 | d76d1650 | aurel32 | env->spr[SPR_SPRG2] = regs.sprg2; |
124 | d76d1650 | aurel32 | env->spr[SPR_SPRG3] = regs.sprg3; |
125 | d76d1650 | aurel32 | env->spr[SPR_SPRG4] = regs.sprg4; |
126 | d76d1650 | aurel32 | env->spr[SPR_SPRG5] = regs.sprg5; |
127 | d76d1650 | aurel32 | env->spr[SPR_SPRG6] = regs.sprg6; |
128 | d76d1650 | aurel32 | env->spr[SPR_SPRG7] = regs.sprg7; |
129 | d76d1650 | aurel32 | |
130 | d76d1650 | aurel32 | for (i = 0;i < 32; i++) |
131 | d76d1650 | aurel32 | env->gpr[i] = regs.gpr[i]; |
132 | d76d1650 | aurel32 | |
133 | ba5e5090 | Alexander Graf | #ifdef KVM_CAP_PPC_SEGSTATE
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134 | ba5e5090 | Alexander Graf | if (kvm_check_extension(env->kvm_state, KVM_CAP_PPC_SEGSTATE)) {
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135 | ba5e5090 | Alexander Graf | env->sdr1 = sregs.u.s.sdr1; |
136 | ba5e5090 | Alexander Graf | |
137 | ba5e5090 | Alexander Graf | /* Sync SLB */
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138 | ba5e5090 | Alexander Graf | for (i = 0; i < 64; i++) { |
139 | ba5e5090 | Alexander Graf | ppc_store_slb(env, sregs.u.s.ppc64.slb[i].slbe, |
140 | ba5e5090 | Alexander Graf | sregs.u.s.ppc64.slb[i].slbv); |
141 | ba5e5090 | Alexander Graf | } |
142 | ba5e5090 | Alexander Graf | |
143 | ba5e5090 | Alexander Graf | /* Sync SRs */
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144 | ba5e5090 | Alexander Graf | for (i = 0; i < 16; i++) { |
145 | ba5e5090 | Alexander Graf | env->sr[i] = sregs.u.s.ppc32.sr[i]; |
146 | ba5e5090 | Alexander Graf | } |
147 | ba5e5090 | Alexander Graf | |
148 | ba5e5090 | Alexander Graf | /* Sync BATs */
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149 | ba5e5090 | Alexander Graf | for (i = 0; i < 8; i++) { |
150 | ba5e5090 | Alexander Graf | env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff; |
151 | ba5e5090 | Alexander Graf | env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32; |
152 | ba5e5090 | Alexander Graf | env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff; |
153 | ba5e5090 | Alexander Graf | env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32; |
154 | ba5e5090 | Alexander Graf | } |
155 | ba5e5090 | Alexander Graf | } |
156 | ba5e5090 | Alexander Graf | #endif
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157 | ba5e5090 | Alexander Graf | |
158 | d76d1650 | aurel32 | return 0; |
159 | d76d1650 | aurel32 | } |
160 | d76d1650 | aurel32 | |
161 | 16415335 | Alexander Graf | #if defined(TARGET_PPCEMB)
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162 | 16415335 | Alexander Graf | #define PPC_INPUT_INT PPC40x_INPUT_INT
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163 | 16415335 | Alexander Graf | #elif defined(TARGET_PPC64)
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164 | 16415335 | Alexander Graf | #define PPC_INPUT_INT PPC970_INPUT_INT
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165 | 16415335 | Alexander Graf | #else
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166 | 16415335 | Alexander Graf | #define PPC_INPUT_INT PPC6xx_INPUT_INT
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167 | 16415335 | Alexander Graf | #endif
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168 | 16415335 | Alexander Graf | |
169 | d76d1650 | aurel32 | int kvm_arch_pre_run(CPUState *env, struct kvm_run *run) |
170 | d76d1650 | aurel32 | { |
171 | d76d1650 | aurel32 | int r;
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172 | d76d1650 | aurel32 | unsigned irq;
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173 | d76d1650 | aurel32 | |
174 | d76d1650 | aurel32 | /* PowerPC Qemu tracks the various core input pins (interrupt, critical
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175 | d76d1650 | aurel32 | * interrupt, reset, etc) in PPC-specific env->irq_input_state. */
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176 | d76d1650 | aurel32 | if (run->ready_for_interrupt_injection &&
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177 | d76d1650 | aurel32 | (env->interrupt_request & CPU_INTERRUPT_HARD) && |
178 | 16415335 | Alexander Graf | (env->irq_input_state & (1<<PPC_INPUT_INT)))
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179 | d76d1650 | aurel32 | { |
180 | d76d1650 | aurel32 | /* For now KVM disregards the 'irq' argument. However, in the
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181 | d76d1650 | aurel32 | * future KVM could cache it in-kernel to avoid a heavyweight exit
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182 | d76d1650 | aurel32 | * when reading the UIC.
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183 | d76d1650 | aurel32 | */
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184 | d76d1650 | aurel32 | irq = -1U;
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185 | d76d1650 | aurel32 | |
186 | d76d1650 | aurel32 | dprintf("injected interrupt %d\n", irq);
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187 | d76d1650 | aurel32 | r = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &irq); |
188 | d76d1650 | aurel32 | if (r < 0) |
189 | d76d1650 | aurel32 | printf("cpu %d fail inject %x\n", env->cpu_index, irq);
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190 | d76d1650 | aurel32 | } |
191 | d76d1650 | aurel32 | |
192 | d76d1650 | aurel32 | /* We don't know if there are more interrupts pending after this. However,
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193 | d76d1650 | aurel32 | * the guest will return to userspace in the course of handling this one
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194 | d76d1650 | aurel32 | * anyways, so we will get a chance to deliver the rest. */
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195 | d76d1650 | aurel32 | return 0; |
196 | d76d1650 | aurel32 | } |
197 | d76d1650 | aurel32 | |
198 | d76d1650 | aurel32 | int kvm_arch_post_run(CPUState *env, struct kvm_run *run) |
199 | d76d1650 | aurel32 | { |
200 | d76d1650 | aurel32 | return 0; |
201 | d76d1650 | aurel32 | } |
202 | d76d1650 | aurel32 | |
203 | d76d1650 | aurel32 | static int kvmppc_handle_halt(CPUState *env) |
204 | d76d1650 | aurel32 | { |
205 | d76d1650 | aurel32 | if (!(env->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) {
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206 | d76d1650 | aurel32 | env->halted = 1;
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207 | d76d1650 | aurel32 | env->exception_index = EXCP_HLT; |
208 | d76d1650 | aurel32 | } |
209 | d76d1650 | aurel32 | |
210 | d76d1650 | aurel32 | return 1; |
211 | d76d1650 | aurel32 | } |
212 | d76d1650 | aurel32 | |
213 | d76d1650 | aurel32 | /* map dcr access to existing qemu dcr emulation */
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214 | d76d1650 | aurel32 | static int kvmppc_handle_dcr_read(CPUState *env, uint32_t dcrn, uint32_t *data) |
215 | d76d1650 | aurel32 | { |
216 | d76d1650 | aurel32 | if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0) |
217 | d76d1650 | aurel32 | fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn);
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218 | d76d1650 | aurel32 | |
219 | d76d1650 | aurel32 | return 1; |
220 | d76d1650 | aurel32 | } |
221 | d76d1650 | aurel32 | |
222 | d76d1650 | aurel32 | static int kvmppc_handle_dcr_write(CPUState *env, uint32_t dcrn, uint32_t data) |
223 | d76d1650 | aurel32 | { |
224 | d76d1650 | aurel32 | if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0) |
225 | d76d1650 | aurel32 | fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn);
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226 | d76d1650 | aurel32 | |
227 | d76d1650 | aurel32 | return 1; |
228 | d76d1650 | aurel32 | } |
229 | d76d1650 | aurel32 | |
230 | d76d1650 | aurel32 | int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run) |
231 | d76d1650 | aurel32 | { |
232 | d76d1650 | aurel32 | int ret = 0; |
233 | d76d1650 | aurel32 | |
234 | d76d1650 | aurel32 | switch (run->exit_reason) {
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235 | d76d1650 | aurel32 | case KVM_EXIT_DCR:
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236 | d76d1650 | aurel32 | if (run->dcr.is_write) {
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237 | d76d1650 | aurel32 | dprintf("handle dcr write\n");
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238 | d76d1650 | aurel32 | ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data); |
239 | d76d1650 | aurel32 | } else {
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240 | d76d1650 | aurel32 | dprintf("handle dcr read\n");
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241 | d76d1650 | aurel32 | ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data); |
242 | d76d1650 | aurel32 | } |
243 | d76d1650 | aurel32 | break;
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244 | d76d1650 | aurel32 | case KVM_EXIT_HLT:
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245 | d76d1650 | aurel32 | dprintf("handle halt\n");
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246 | d76d1650 | aurel32 | ret = kvmppc_handle_halt(env); |
247 | d76d1650 | aurel32 | break;
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248 | d76d1650 | aurel32 | } |
249 | d76d1650 | aurel32 | |
250 | d76d1650 | aurel32 | return ret;
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251 | d76d1650 | aurel32 | } |