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root / target-sh4 @ bacc637a

Name Size
README.sh4 4.8 kB
cpu.h 9.4 kB
exec.h 1.6 kB
helper.c 16.3 kB
helper.h 1.4 kB
machine.c 159 Bytes
op_helper.c 10.8 kB
translate.c 57.9 kB

Latest revisions

# Date Author Comment
bacc637a 12/13/2008 08:57 pm aurel32

target-sh4: disable debug code

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6014 c046a42c-6fe2-441c-8c8c-71466251a162
71968fa6 12/13/2008 08:57 pm aurel32

target-sh4: add prefi, icbi, synco

(Vladimir Prus)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6013 c046a42c-6fe2-441c-8c8c-71466251a162
a9c43f8e 12/13/2008 08:57 pm aurel32

target-sh4: add SH7785 as CPU option

(Vladimir Prus)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6012 c046a42c-6fe2-441c-8c8c-71466251a162
42083220 12/12/2008 12:42 am aurel32

target-sh4: remove 2 warnings

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5993 c046a42c-6fe2-441c-8c8c-71466251a162
eeda6778 12/10/2008 07:31 pm aurel32

target-sh4: Add SH bit handling to TLB

This patch adds SH bit handling to sh4's TLB, which is a part of MMU
functionality that had not been implemented in qemu.

Additionally, increment_urc() call in cpu_load_tlb() is deleted, because
the specification explicitly says that URC is not incremented by an LDTLB...
f6198371 12/10/2008 07:31 pm aurel32

target-sh4: check FD bit for FP instructions

Based on a patch from Vladimir Prus <>

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5970 c046a42c-6fe2-441c-8c8c-71466251a162
b79e1752 12/08/2008 12:46 am aurel32

SH4: kill a few warnings

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5938 c046a42c-6fe2-441c-8c8c-71466251a162
d8299bcc 12/08/2008 12:46 am aurel32

SH4: Implement FD bit

SH4 manual say that if a floating point instruction is executed while
FD bit in the status register is 1, an exception should be raised. QEMU
presently does not do that, so the kernel does not initialize FP state
for any thread, nor does it save/restore FP state. The most apparent...
5c16736a 12/07/2008 09:39 pm balrog

SH4: Eliminate P4 to A7 mangling (Takashi YOSHII).

Main purpose of this is to delete
*physical = address & 0x1fffffff;
at target-sh4/helper.c:449, using new mmio rule introduced by #5849
This masking is a nice trick to realize P4/A7 duality of SH registers....
1e5459a3 12/07/2008 09:08 pm balrog

SH: On-chip PCI controller support (Takashi YOSHII).

This patch adds SuperH on-chip PCI controller(PCIC) support.

Signed-off-by: Takashi YOSHII <>
Signed-off-by: Andrzej Zaborowski <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5927 c046a42c-6fe2-441c-8c8c-71466251a162

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