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1 | 0cac1b66 | Blue Swirl | /*
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2 | 0cac1b66 | Blue Swirl | * Common CPU TLB handling
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3 | 0cac1b66 | Blue Swirl | *
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4 | 0cac1b66 | Blue Swirl | * Copyright (c) 2003 Fabrice Bellard
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5 | 0cac1b66 | Blue Swirl | *
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6 | 0cac1b66 | Blue Swirl | * This library is free software; you can redistribute it and/or
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7 | 0cac1b66 | Blue Swirl | * modify it under the terms of the GNU Lesser General Public
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8 | 0cac1b66 | Blue Swirl | * License as published by the Free Software Foundation; either
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9 | 0cac1b66 | Blue Swirl | * version 2 of the License, or (at your option) any later version.
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10 | 0cac1b66 | Blue Swirl | *
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11 | 0cac1b66 | Blue Swirl | * This library is distributed in the hope that it will be useful,
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12 | 0cac1b66 | Blue Swirl | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 0cac1b66 | Blue Swirl | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 0cac1b66 | Blue Swirl | * Lesser General Public License for more details.
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15 | 0cac1b66 | Blue Swirl | *
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16 | 0cac1b66 | Blue Swirl | * You should have received a copy of the GNU Lesser General Public
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17 | 0cac1b66 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | 0cac1b66 | Blue Swirl | */
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19 | 0cac1b66 | Blue Swirl | |
20 | 0cac1b66 | Blue Swirl | #include "config.h" |
21 | 0cac1b66 | Blue Swirl | #include "cpu.h" |
22 | 022c62cb | Paolo Bonzini | #include "exec/exec-all.h" |
23 | 022c62cb | Paolo Bonzini | #include "exec/memory.h" |
24 | 022c62cb | Paolo Bonzini | #include "exec/address-spaces.h" |
25 | 0cac1b66 | Blue Swirl | |
26 | 022c62cb | Paolo Bonzini | #include "exec/cputlb.h" |
27 | 0cac1b66 | Blue Swirl | |
28 | 022c62cb | Paolo Bonzini | #include "exec/memory-internal.h" |
29 | 0cac1b66 | Blue Swirl | |
30 | 0cac1b66 | Blue Swirl | //#define DEBUG_TLB
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31 | 0cac1b66 | Blue Swirl | //#define DEBUG_TLB_CHECK
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32 | 0cac1b66 | Blue Swirl | |
33 | 0cac1b66 | Blue Swirl | /* statistics */
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34 | 0cac1b66 | Blue Swirl | int tlb_flush_count;
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35 | 0cac1b66 | Blue Swirl | |
36 | 0cac1b66 | Blue Swirl | static const CPUTLBEntry s_cputlb_empty_entry = { |
37 | 0cac1b66 | Blue Swirl | .addr_read = -1,
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38 | 0cac1b66 | Blue Swirl | .addr_write = -1,
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39 | 0cac1b66 | Blue Swirl | .addr_code = -1,
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40 | 0cac1b66 | Blue Swirl | .addend = -1,
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41 | 0cac1b66 | Blue Swirl | }; |
42 | 0cac1b66 | Blue Swirl | |
43 | 0cac1b66 | Blue Swirl | /* NOTE:
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44 | 0cac1b66 | Blue Swirl | * If flush_global is true (the usual case), flush all tlb entries.
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45 | 0cac1b66 | Blue Swirl | * If flush_global is false, flush (at least) all tlb entries not
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46 | 0cac1b66 | Blue Swirl | * marked global.
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47 | 0cac1b66 | Blue Swirl | *
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48 | 0cac1b66 | Blue Swirl | * Since QEMU doesn't currently implement a global/not-global flag
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49 | 0cac1b66 | Blue Swirl | * for tlb entries, at the moment tlb_flush() will also flush all
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50 | 0cac1b66 | Blue Swirl | * tlb entries in the flush_global == false case. This is OK because
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51 | 0cac1b66 | Blue Swirl | * CPU architectures generally permit an implementation to drop
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52 | 0cac1b66 | Blue Swirl | * entries from the TLB at any time, so flushing more entries than
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53 | 0cac1b66 | Blue Swirl | * required is only an efficiency issue, not a correctness issue.
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54 | 0cac1b66 | Blue Swirl | */
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55 | 0cac1b66 | Blue Swirl | void tlb_flush(CPUArchState *env, int flush_global) |
56 | 0cac1b66 | Blue Swirl | { |
57 | d77953b9 | Andreas Färber | CPUState *cpu = ENV_GET_CPU(env); |
58 | 0cac1b66 | Blue Swirl | int i;
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59 | 0cac1b66 | Blue Swirl | |
60 | 0cac1b66 | Blue Swirl | #if defined(DEBUG_TLB)
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61 | 0cac1b66 | Blue Swirl | printf("tlb_flush:\n");
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62 | 0cac1b66 | Blue Swirl | #endif
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63 | 0cac1b66 | Blue Swirl | /* must reset current TB so that interrupts cannot modify the
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64 | 0cac1b66 | Blue Swirl | links while we are modifying them */
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65 | d77953b9 | Andreas Färber | cpu->current_tb = NULL;
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66 | 0cac1b66 | Blue Swirl | |
67 | 0cac1b66 | Blue Swirl | for (i = 0; i < CPU_TLB_SIZE; i++) { |
68 | 0cac1b66 | Blue Swirl | int mmu_idx;
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69 | 0cac1b66 | Blue Swirl | |
70 | 0cac1b66 | Blue Swirl | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { |
71 | 0cac1b66 | Blue Swirl | env->tlb_table[mmu_idx][i] = s_cputlb_empty_entry; |
72 | 0cac1b66 | Blue Swirl | } |
73 | 0cac1b66 | Blue Swirl | } |
74 | 0cac1b66 | Blue Swirl | |
75 | 0cac1b66 | Blue Swirl | memset(env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); |
76 | 0cac1b66 | Blue Swirl | |
77 | 0cac1b66 | Blue Swirl | env->tlb_flush_addr = -1;
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78 | 0cac1b66 | Blue Swirl | env->tlb_flush_mask = 0;
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79 | 0cac1b66 | Blue Swirl | tlb_flush_count++; |
80 | 0cac1b66 | Blue Swirl | } |
81 | 0cac1b66 | Blue Swirl | |
82 | 0cac1b66 | Blue Swirl | static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr) |
83 | 0cac1b66 | Blue Swirl | { |
84 | 0cac1b66 | Blue Swirl | if (addr == (tlb_entry->addr_read &
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85 | 0cac1b66 | Blue Swirl | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || |
86 | 0cac1b66 | Blue Swirl | addr == (tlb_entry->addr_write & |
87 | 0cac1b66 | Blue Swirl | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || |
88 | 0cac1b66 | Blue Swirl | addr == (tlb_entry->addr_code & |
89 | 0cac1b66 | Blue Swirl | (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { |
90 | 0cac1b66 | Blue Swirl | *tlb_entry = s_cputlb_empty_entry; |
91 | 0cac1b66 | Blue Swirl | } |
92 | 0cac1b66 | Blue Swirl | } |
93 | 0cac1b66 | Blue Swirl | |
94 | 0cac1b66 | Blue Swirl | void tlb_flush_page(CPUArchState *env, target_ulong addr)
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95 | 0cac1b66 | Blue Swirl | { |
96 | d77953b9 | Andreas Färber | CPUState *cpu = ENV_GET_CPU(env); |
97 | 0cac1b66 | Blue Swirl | int i;
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98 | 0cac1b66 | Blue Swirl | int mmu_idx;
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99 | 0cac1b66 | Blue Swirl | |
100 | 0cac1b66 | Blue Swirl | #if defined(DEBUG_TLB)
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101 | 0cac1b66 | Blue Swirl | printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr); |
102 | 0cac1b66 | Blue Swirl | #endif
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103 | 0cac1b66 | Blue Swirl | /* Check if we need to flush due to large pages. */
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104 | 0cac1b66 | Blue Swirl | if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) {
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105 | 0cac1b66 | Blue Swirl | #if defined(DEBUG_TLB)
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106 | 0cac1b66 | Blue Swirl | printf("tlb_flush_page: forced full flush ("
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107 | 0cac1b66 | Blue Swirl | TARGET_FMT_lx "/" TARGET_FMT_lx ")\n", |
108 | 0cac1b66 | Blue Swirl | env->tlb_flush_addr, env->tlb_flush_mask); |
109 | 0cac1b66 | Blue Swirl | #endif
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110 | 0cac1b66 | Blue Swirl | tlb_flush(env, 1);
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111 | 0cac1b66 | Blue Swirl | return;
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112 | 0cac1b66 | Blue Swirl | } |
113 | 0cac1b66 | Blue Swirl | /* must reset current TB so that interrupts cannot modify the
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114 | 0cac1b66 | Blue Swirl | links while we are modifying them */
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115 | d77953b9 | Andreas Färber | cpu->current_tb = NULL;
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116 | 0cac1b66 | Blue Swirl | |
117 | 0cac1b66 | Blue Swirl | addr &= TARGET_PAGE_MASK; |
118 | 0cac1b66 | Blue Swirl | i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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119 | 0cac1b66 | Blue Swirl | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { |
120 | 0cac1b66 | Blue Swirl | tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr); |
121 | 0cac1b66 | Blue Swirl | } |
122 | 0cac1b66 | Blue Swirl | |
123 | 0cac1b66 | Blue Swirl | tb_flush_jmp_cache(env, addr); |
124 | 0cac1b66 | Blue Swirl | } |
125 | 0cac1b66 | Blue Swirl | |
126 | 0cac1b66 | Blue Swirl | /* update the TLBs so that writes to code in the virtual page 'addr'
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127 | 0cac1b66 | Blue Swirl | can be detected */
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128 | 0cac1b66 | Blue Swirl | void tlb_protect_code(ram_addr_t ram_addr)
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129 | 0cac1b66 | Blue Swirl | { |
130 | 0cac1b66 | Blue Swirl | cpu_physical_memory_reset_dirty(ram_addr, |
131 | 0cac1b66 | Blue Swirl | ram_addr + TARGET_PAGE_SIZE, |
132 | 0cac1b66 | Blue Swirl | CODE_DIRTY_FLAG); |
133 | 0cac1b66 | Blue Swirl | } |
134 | 0cac1b66 | Blue Swirl | |
135 | 0cac1b66 | Blue Swirl | /* update the TLB so that writes in physical page 'phys_addr' are no longer
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136 | 0cac1b66 | Blue Swirl | tested for self modifying code */
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137 | 0cac1b66 | Blue Swirl | void tlb_unprotect_code_phys(CPUArchState *env, ram_addr_t ram_addr,
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138 | 0cac1b66 | Blue Swirl | target_ulong vaddr) |
139 | 0cac1b66 | Blue Swirl | { |
140 | 0cac1b66 | Blue Swirl | cpu_physical_memory_set_dirty_flags(ram_addr, CODE_DIRTY_FLAG); |
141 | 0cac1b66 | Blue Swirl | } |
142 | 0cac1b66 | Blue Swirl | |
143 | 0cac1b66 | Blue Swirl | static bool tlb_is_dirty_ram(CPUTLBEntry *tlbe) |
144 | 0cac1b66 | Blue Swirl | { |
145 | 0cac1b66 | Blue Swirl | return (tlbe->addr_write & (TLB_INVALID_MASK|TLB_MMIO|TLB_NOTDIRTY)) == 0; |
146 | 0cac1b66 | Blue Swirl | } |
147 | 0cac1b66 | Blue Swirl | |
148 | 0cac1b66 | Blue Swirl | void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, uintptr_t start,
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149 | 0cac1b66 | Blue Swirl | uintptr_t length) |
150 | 0cac1b66 | Blue Swirl | { |
151 | 0cac1b66 | Blue Swirl | uintptr_t addr; |
152 | 0cac1b66 | Blue Swirl | |
153 | 0cac1b66 | Blue Swirl | if (tlb_is_dirty_ram(tlb_entry)) {
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154 | 0cac1b66 | Blue Swirl | addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend; |
155 | 0cac1b66 | Blue Swirl | if ((addr - start) < length) {
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156 | 0cac1b66 | Blue Swirl | tlb_entry->addr_write |= TLB_NOTDIRTY; |
157 | 0cac1b66 | Blue Swirl | } |
158 | 0cac1b66 | Blue Swirl | } |
159 | 0cac1b66 | Blue Swirl | } |
160 | 0cac1b66 | Blue Swirl | |
161 | 7443b437 | Paolo Bonzini | static inline ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr) |
162 | 7443b437 | Paolo Bonzini | { |
163 | 7443b437 | Paolo Bonzini | ram_addr_t ram_addr; |
164 | 7443b437 | Paolo Bonzini | |
165 | 1b5ec234 | Paolo Bonzini | if (qemu_ram_addr_from_host(ptr, &ram_addr) == NULL) { |
166 | 7443b437 | Paolo Bonzini | fprintf(stderr, "Bad ram pointer %p\n", ptr);
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167 | 7443b437 | Paolo Bonzini | abort(); |
168 | 7443b437 | Paolo Bonzini | } |
169 | 7443b437 | Paolo Bonzini | return ram_addr;
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170 | 7443b437 | Paolo Bonzini | } |
171 | 7443b437 | Paolo Bonzini | |
172 | 0cac1b66 | Blue Swirl | static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry) |
173 | 0cac1b66 | Blue Swirl | { |
174 | 0cac1b66 | Blue Swirl | ram_addr_t ram_addr; |
175 | 0cac1b66 | Blue Swirl | void *p;
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176 | 0cac1b66 | Blue Swirl | |
177 | 0cac1b66 | Blue Swirl | if (tlb_is_dirty_ram(tlb_entry)) {
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178 | 0cac1b66 | Blue Swirl | p = (void *)(uintptr_t)((tlb_entry->addr_write & TARGET_PAGE_MASK)
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179 | 0cac1b66 | Blue Swirl | + tlb_entry->addend); |
180 | 0cac1b66 | Blue Swirl | ram_addr = qemu_ram_addr_from_host_nofail(p); |
181 | 0cac1b66 | Blue Swirl | if (!cpu_physical_memory_is_dirty(ram_addr)) {
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182 | 0cac1b66 | Blue Swirl | tlb_entry->addr_write |= TLB_NOTDIRTY; |
183 | 0cac1b66 | Blue Swirl | } |
184 | 0cac1b66 | Blue Swirl | } |
185 | 0cac1b66 | Blue Swirl | } |
186 | 0cac1b66 | Blue Swirl | |
187 | 0cac1b66 | Blue Swirl | void cpu_tlb_reset_dirty_all(ram_addr_t start1, ram_addr_t length)
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188 | 0cac1b66 | Blue Swirl | { |
189 | 182735ef | Andreas Färber | CPUState *cpu; |
190 | 0cac1b66 | Blue Swirl | CPUArchState *env; |
191 | 0cac1b66 | Blue Swirl | |
192 | bdc44640 | Andreas Färber | CPU_FOREACH(cpu) { |
193 | 0cac1b66 | Blue Swirl | int mmu_idx;
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194 | 0cac1b66 | Blue Swirl | |
195 | 182735ef | Andreas Färber | env = cpu->env_ptr; |
196 | 0cac1b66 | Blue Swirl | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { |
197 | 0cac1b66 | Blue Swirl | unsigned int i; |
198 | 0cac1b66 | Blue Swirl | |
199 | 0cac1b66 | Blue Swirl | for (i = 0; i < CPU_TLB_SIZE; i++) { |
200 | 0cac1b66 | Blue Swirl | tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i], |
201 | 0cac1b66 | Blue Swirl | start1, length); |
202 | 0cac1b66 | Blue Swirl | } |
203 | 0cac1b66 | Blue Swirl | } |
204 | 0cac1b66 | Blue Swirl | } |
205 | 0cac1b66 | Blue Swirl | } |
206 | 0cac1b66 | Blue Swirl | |
207 | 0cac1b66 | Blue Swirl | static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr) |
208 | 0cac1b66 | Blue Swirl | { |
209 | 0cac1b66 | Blue Swirl | if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY)) {
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210 | 0cac1b66 | Blue Swirl | tlb_entry->addr_write = vaddr; |
211 | 0cac1b66 | Blue Swirl | } |
212 | 0cac1b66 | Blue Swirl | } |
213 | 0cac1b66 | Blue Swirl | |
214 | 0cac1b66 | Blue Swirl | /* update the TLB corresponding to virtual page vaddr
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215 | 0cac1b66 | Blue Swirl | so that it is no longer dirty */
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216 | 0cac1b66 | Blue Swirl | void tlb_set_dirty(CPUArchState *env, target_ulong vaddr)
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217 | 0cac1b66 | Blue Swirl | { |
218 | 0cac1b66 | Blue Swirl | int i;
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219 | 0cac1b66 | Blue Swirl | int mmu_idx;
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220 | 0cac1b66 | Blue Swirl | |
221 | 0cac1b66 | Blue Swirl | vaddr &= TARGET_PAGE_MASK; |
222 | 0cac1b66 | Blue Swirl | i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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223 | 0cac1b66 | Blue Swirl | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { |
224 | 0cac1b66 | Blue Swirl | tlb_set_dirty1(&env->tlb_table[mmu_idx][i], vaddr); |
225 | 0cac1b66 | Blue Swirl | } |
226 | 0cac1b66 | Blue Swirl | } |
227 | 0cac1b66 | Blue Swirl | |
228 | 0cac1b66 | Blue Swirl | /* Our TLB does not support large pages, so remember the area covered by
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229 | 0cac1b66 | Blue Swirl | large pages and trigger a full TLB flush if these are invalidated. */
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230 | 0cac1b66 | Blue Swirl | static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr, |
231 | 0cac1b66 | Blue Swirl | target_ulong size) |
232 | 0cac1b66 | Blue Swirl | { |
233 | 0cac1b66 | Blue Swirl | target_ulong mask = ~(size - 1);
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234 | 0cac1b66 | Blue Swirl | |
235 | 0cac1b66 | Blue Swirl | if (env->tlb_flush_addr == (target_ulong)-1) { |
236 | 0cac1b66 | Blue Swirl | env->tlb_flush_addr = vaddr & mask; |
237 | 0cac1b66 | Blue Swirl | env->tlb_flush_mask = mask; |
238 | 0cac1b66 | Blue Swirl | return;
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239 | 0cac1b66 | Blue Swirl | } |
240 | 0cac1b66 | Blue Swirl | /* Extend the existing region to include the new page.
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241 | 0cac1b66 | Blue Swirl | This is a compromise between unnecessary flushes and the cost
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242 | 0cac1b66 | Blue Swirl | of maintaining a full variable size TLB. */
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243 | 0cac1b66 | Blue Swirl | mask &= env->tlb_flush_mask; |
244 | 0cac1b66 | Blue Swirl | while (((env->tlb_flush_addr ^ vaddr) & mask) != 0) { |
245 | 0cac1b66 | Blue Swirl | mask <<= 1;
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246 | 0cac1b66 | Blue Swirl | } |
247 | 0cac1b66 | Blue Swirl | env->tlb_flush_addr &= mask; |
248 | 0cac1b66 | Blue Swirl | env->tlb_flush_mask = mask; |
249 | 0cac1b66 | Blue Swirl | } |
250 | 0cac1b66 | Blue Swirl | |
251 | 0cac1b66 | Blue Swirl | /* Add a new TLB entry. At most one entry for a given virtual address
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252 | 0cac1b66 | Blue Swirl | is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
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253 | 0cac1b66 | Blue Swirl | supplied size is only used by tlb_flush_page. */
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254 | 0cac1b66 | Blue Swirl | void tlb_set_page(CPUArchState *env, target_ulong vaddr,
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255 | a8170e5e | Avi Kivity | hwaddr paddr, int prot,
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256 | 0cac1b66 | Blue Swirl | int mmu_idx, target_ulong size)
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257 | 0cac1b66 | Blue Swirl | { |
258 | 0cac1b66 | Blue Swirl | MemoryRegionSection *section; |
259 | 0cac1b66 | Blue Swirl | unsigned int index; |
260 | 0cac1b66 | Blue Swirl | target_ulong address; |
261 | 0cac1b66 | Blue Swirl | target_ulong code_address; |
262 | 0cac1b66 | Blue Swirl | uintptr_t addend; |
263 | 0cac1b66 | Blue Swirl | CPUTLBEntry *te; |
264 | 149f54b5 | Paolo Bonzini | hwaddr iotlb, xlat, sz; |
265 | 0cac1b66 | Blue Swirl | |
266 | 0cac1b66 | Blue Swirl | assert(size >= TARGET_PAGE_SIZE); |
267 | 0cac1b66 | Blue Swirl | if (size != TARGET_PAGE_SIZE) {
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268 | 0cac1b66 | Blue Swirl | tlb_add_large_page(env, vaddr, size); |
269 | 0cac1b66 | Blue Swirl | } |
270 | 149f54b5 | Paolo Bonzini | |
271 | 149f54b5 | Paolo Bonzini | sz = size; |
272 | 90260c6c | Jan Kiszka | section = address_space_translate_for_iotlb(&address_space_memory, paddr, |
273 | 90260c6c | Jan Kiszka | &xlat, &sz); |
274 | 149f54b5 | Paolo Bonzini | assert(sz >= TARGET_PAGE_SIZE); |
275 | 149f54b5 | Paolo Bonzini | |
276 | 0cac1b66 | Blue Swirl | #if defined(DEBUG_TLB)
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277 | 0cac1b66 | Blue Swirl | printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx |
278 | 54b949d2 | Hervé Poussineau | " prot=%x idx=%d\n",
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279 | 54b949d2 | Hervé Poussineau | vaddr, paddr, prot, mmu_idx); |
280 | 0cac1b66 | Blue Swirl | #endif
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281 | 0cac1b66 | Blue Swirl | |
282 | 0cac1b66 | Blue Swirl | address = vaddr; |
283 | 8f3e03cb | Paolo Bonzini | if (!memory_region_is_ram(section->mr) && !memory_region_is_romd(section->mr)) {
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284 | 8f3e03cb | Paolo Bonzini | /* IO memory case */
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285 | 0cac1b66 | Blue Swirl | address |= TLB_MMIO; |
286 | 8f3e03cb | Paolo Bonzini | addend = 0;
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287 | 8f3e03cb | Paolo Bonzini | } else {
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288 | 8f3e03cb | Paolo Bonzini | /* TLB_MMIO for rom/romd handled below */
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289 | 149f54b5 | Paolo Bonzini | addend = (uintptr_t)memory_region_get_ram_ptr(section->mr) + xlat; |
290 | 0cac1b66 | Blue Swirl | } |
291 | 0cac1b66 | Blue Swirl | |
292 | 0cac1b66 | Blue Swirl | code_address = address; |
293 | 149f54b5 | Paolo Bonzini | iotlb = memory_region_section_get_iotlb(env, section, vaddr, paddr, xlat, |
294 | 149f54b5 | Paolo Bonzini | prot, &address); |
295 | 0cac1b66 | Blue Swirl | |
296 | 0cac1b66 | Blue Swirl | index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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297 | 0cac1b66 | Blue Swirl | env->iotlb[mmu_idx][index] = iotlb - vaddr; |
298 | 0cac1b66 | Blue Swirl | te = &env->tlb_table[mmu_idx][index]; |
299 | 0cac1b66 | Blue Swirl | te->addend = addend - vaddr; |
300 | 0cac1b66 | Blue Swirl | if (prot & PAGE_READ) {
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301 | 0cac1b66 | Blue Swirl | te->addr_read = address; |
302 | 0cac1b66 | Blue Swirl | } else {
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303 | 0cac1b66 | Blue Swirl | te->addr_read = -1;
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304 | 0cac1b66 | Blue Swirl | } |
305 | 0cac1b66 | Blue Swirl | |
306 | 0cac1b66 | Blue Swirl | if (prot & PAGE_EXEC) {
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307 | 0cac1b66 | Blue Swirl | te->addr_code = code_address; |
308 | 0cac1b66 | Blue Swirl | } else {
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309 | 0cac1b66 | Blue Swirl | te->addr_code = -1;
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310 | 0cac1b66 | Blue Swirl | } |
311 | 0cac1b66 | Blue Swirl | if (prot & PAGE_WRITE) {
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312 | 0cac1b66 | Blue Swirl | if ((memory_region_is_ram(section->mr) && section->readonly)
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313 | cc5bea60 | Blue Swirl | || memory_region_is_romd(section->mr)) { |
314 | 0cac1b66 | Blue Swirl | /* Write access calls the I/O callback. */
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315 | 0cac1b66 | Blue Swirl | te->addr_write = address | TLB_MMIO; |
316 | 0cac1b66 | Blue Swirl | } else if (memory_region_is_ram(section->mr) |
317 | 149f54b5 | Paolo Bonzini | && !cpu_physical_memory_is_dirty(section->mr->ram_addr + xlat)) { |
318 | 0cac1b66 | Blue Swirl | te->addr_write = address | TLB_NOTDIRTY; |
319 | 0cac1b66 | Blue Swirl | } else {
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320 | 0cac1b66 | Blue Swirl | te->addr_write = address; |
321 | 0cac1b66 | Blue Swirl | } |
322 | 0cac1b66 | Blue Swirl | } else {
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323 | 0cac1b66 | Blue Swirl | te->addr_write = -1;
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324 | 0cac1b66 | Blue Swirl | } |
325 | 0cac1b66 | Blue Swirl | } |
326 | 0cac1b66 | Blue Swirl | |
327 | 0cac1b66 | Blue Swirl | /* NOTE: this function can trigger an exception */
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328 | 0cac1b66 | Blue Swirl | /* NOTE2: the returned address is not exactly the physical address: it
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329 | 116aae36 | Peter Maydell | * is actually a ram_addr_t (in system mode; the user mode emulation
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330 | 116aae36 | Peter Maydell | * version of this function returns a guest virtual address).
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331 | 116aae36 | Peter Maydell | */
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332 | 0cac1b66 | Blue Swirl | tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr) |
333 | 0cac1b66 | Blue Swirl | { |
334 | 0cac1b66 | Blue Swirl | int mmu_idx, page_index, pd;
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335 | 0cac1b66 | Blue Swirl | void *p;
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336 | 0cac1b66 | Blue Swirl | MemoryRegion *mr; |
337 | 0cac1b66 | Blue Swirl | |
338 | 0cac1b66 | Blue Swirl | page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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339 | 0cac1b66 | Blue Swirl | mmu_idx = cpu_mmu_index(env1); |
340 | 0cac1b66 | Blue Swirl | if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
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341 | 0cac1b66 | Blue Swirl | (addr & TARGET_PAGE_MASK))) { |
342 | 0cac1b66 | Blue Swirl | cpu_ldub_code(env1, addr); |
343 | 0cac1b66 | Blue Swirl | } |
344 | 0cac1b66 | Blue Swirl | pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK; |
345 | 0cac1b66 | Blue Swirl | mr = iotlb_to_region(pd); |
346 | 0cac1b66 | Blue Swirl | if (memory_region_is_unassigned(mr)) {
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347 | c658b94f | Andreas Färber | CPUState *cpu = ENV_GET_CPU(env1); |
348 | c658b94f | Andreas Färber | CPUClass *cc = CPU_GET_CLASS(cpu); |
349 | c658b94f | Andreas Färber | |
350 | c658b94f | Andreas Färber | if (cc->do_unassigned_access) {
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351 | c658b94f | Andreas Färber | cc->do_unassigned_access(cpu, addr, false, true, 0, 4); |
352 | c658b94f | Andreas Färber | } else {
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353 | c658b94f | Andreas Färber | cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x"
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354 | c658b94f | Andreas Färber | TARGET_FMT_lx "\n", addr);
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355 | c658b94f | Andreas Färber | } |
356 | 0cac1b66 | Blue Swirl | } |
357 | 0cac1b66 | Blue Swirl | p = (void *)((uintptr_t)addr + env1->tlb_table[mmu_idx][page_index].addend);
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358 | 0cac1b66 | Blue Swirl | return qemu_ram_addr_from_host_nofail(p);
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359 | 0cac1b66 | Blue Swirl | } |
360 | 0cac1b66 | Blue Swirl | |
361 | 0cac1b66 | Blue Swirl | #define MMUSUFFIX _cmmu
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362 | 0cac1b66 | Blue Swirl | #undef GETPC
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363 | 0cac1b66 | Blue Swirl | #define GETPC() ((uintptr_t)0) |
364 | 0cac1b66 | Blue Swirl | #define SOFTMMU_CODE_ACCESS
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365 | 0cac1b66 | Blue Swirl | |
366 | 0cac1b66 | Blue Swirl | #define SHIFT 0 |
367 | 022c62cb | Paolo Bonzini | #include "exec/softmmu_template.h" |
368 | 0cac1b66 | Blue Swirl | |
369 | 0cac1b66 | Blue Swirl | #define SHIFT 1 |
370 | 022c62cb | Paolo Bonzini | #include "exec/softmmu_template.h" |
371 | 0cac1b66 | Blue Swirl | |
372 | 0cac1b66 | Blue Swirl | #define SHIFT 2 |
373 | 022c62cb | Paolo Bonzini | #include "exec/softmmu_template.h" |
374 | 0cac1b66 | Blue Swirl | |
375 | 0cac1b66 | Blue Swirl | #define SHIFT 3 |
376 | 022c62cb | Paolo Bonzini | #include "exec/softmmu_template.h" |
377 | 0cac1b66 | Blue Swirl | |
378 | 0cac1b66 | Blue Swirl | #undef env |