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1 | 7c23b892 | balrog | /*
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2 | 7c23b892 | balrog | * QEMU e1000 emulation
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3 | 7c23b892 | balrog | *
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4 | 2758aa52 | Michael S. Tsirkin | * Software developer's manual:
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5 | 2758aa52 | Michael S. Tsirkin | * http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf
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6 | 2758aa52 | Michael S. Tsirkin | *
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7 | 7c23b892 | balrog | * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
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8 | 7c23b892 | balrog | * Copyright (c) 2008 Qumranet
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9 | 7c23b892 | balrog | * Based on work done by:
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10 | 7c23b892 | balrog | * Copyright (c) 2007 Dan Aloni
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11 | 7c23b892 | balrog | * Copyright (c) 2004 Antony T Curtis
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12 | 7c23b892 | balrog | *
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13 | 7c23b892 | balrog | * This library is free software; you can redistribute it and/or
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14 | 7c23b892 | balrog | * modify it under the terms of the GNU Lesser General Public
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15 | 7c23b892 | balrog | * License as published by the Free Software Foundation; either
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16 | 7c23b892 | balrog | * version 2 of the License, or (at your option) any later version.
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17 | 7c23b892 | balrog | *
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18 | 7c23b892 | balrog | * This library is distributed in the hope that it will be useful,
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19 | 7c23b892 | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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20 | 7c23b892 | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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21 | 7c23b892 | balrog | * Lesser General Public License for more details.
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22 | 7c23b892 | balrog | *
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23 | 7c23b892 | balrog | * You should have received a copy of the GNU Lesser General Public
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24 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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25 | 7c23b892 | balrog | */
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26 | 7c23b892 | balrog | |
27 | 7c23b892 | balrog | |
28 | 7c23b892 | balrog | #include "hw.h" |
29 | 7c23b892 | balrog | #include "pci.h" |
30 | 7c23b892 | balrog | #include "net.h" |
31 | 7200ac3c | Mark McLoughlin | #include "net/checksum.h" |
32 | fbdaa002 | Gerd Hoffmann | #include "loader.h" |
33 | 1ca4d09a | Gleb Natapov | #include "sysemu.h" |
34 | 62ecbd35 | Eduard - Gabriel Munteanu | #include "dma.h" |
35 | 7c23b892 | balrog | |
36 | 7c23b892 | balrog | #include "e1000_hw.h" |
37 | 7c23b892 | balrog | |
38 | 27124888 | Jes Sorensen | #define E1000_DEBUG
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39 | 7c23b892 | balrog | |
40 | 27124888 | Jes Sorensen | #ifdef E1000_DEBUG
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41 | 7c23b892 | balrog | enum {
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42 | 7c23b892 | balrog | DEBUG_GENERAL, DEBUG_IO, DEBUG_MMIO, DEBUG_INTERRUPT, |
43 | 7c23b892 | balrog | DEBUG_RX, DEBUG_TX, DEBUG_MDIC, DEBUG_EEPROM, |
44 | 7c23b892 | balrog | DEBUG_UNKNOWN, DEBUG_TXSUM, DEBUG_TXERR, DEBUG_RXERR, |
45 | 7c23b892 | balrog | DEBUG_RXFILTER, DEBUG_NOTYET, |
46 | 7c23b892 | balrog | }; |
47 | 7c23b892 | balrog | #define DBGBIT(x) (1<<DEBUG_##x) |
48 | 7c23b892 | balrog | static int debugflags = DBGBIT(TXERR) | DBGBIT(GENERAL); |
49 | 7c23b892 | balrog | |
50 | 6c7f4b47 | Blue Swirl | #define DBGOUT(what, fmt, ...) do { \ |
51 | 7c23b892 | balrog | if (debugflags & DBGBIT(what)) \
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52 | 6c7f4b47 | Blue Swirl | fprintf(stderr, "e1000: " fmt, ## __VA_ARGS__); \ |
53 | 7c23b892 | balrog | } while (0) |
54 | 7c23b892 | balrog | #else
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55 | 6c7f4b47 | Blue Swirl | #define DBGOUT(what, fmt, ...) do {} while (0) |
56 | 7c23b892 | balrog | #endif
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57 | 7c23b892 | balrog | |
58 | 7c23b892 | balrog | #define IOPORT_SIZE 0x40 |
59 | e94bbefe | aurel32 | #define PNPMMIO_SIZE 0x20000 |
60 | 78aeb23e | Stefan Hajnoczi | #define MIN_BUF_SIZE 60 /* Min. octets in an ethernet frame sans FCS */ |
61 | 7c23b892 | balrog | |
62 | 7c23b892 | balrog | /*
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63 | 7c23b892 | balrog | * HW models:
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64 | 7c23b892 | balrog | * E1000_DEV_ID_82540EM works with Windows and Linux
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65 | 7c23b892 | balrog | * E1000_DEV_ID_82573L OK with windoze and Linux 2.6.22,
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66 | 7c23b892 | balrog | * appears to perform better than 82540EM, but breaks with Linux 2.6.18
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67 | 7c23b892 | balrog | * E1000_DEV_ID_82544GC_COPPER appears to work; not well tested
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68 | 7c23b892 | balrog | * Others never tested
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69 | 7c23b892 | balrog | */
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70 | 7c23b892 | balrog | enum { E1000_DEVID = E1000_DEV_ID_82540EM };
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71 | 7c23b892 | balrog | |
72 | 7c23b892 | balrog | /*
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73 | 7c23b892 | balrog | * May need to specify additional MAC-to-PHY entries --
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74 | 7c23b892 | balrog | * Intel's Windows driver refuses to initialize unless they match
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75 | 7c23b892 | balrog | */
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76 | 7c23b892 | balrog | enum {
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77 | 7c23b892 | balrog | PHY_ID2_INIT = E1000_DEVID == E1000_DEV_ID_82573L ? 0xcc2 :
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78 | 7c23b892 | balrog | E1000_DEVID == E1000_DEV_ID_82544GC_COPPER ? 0xc30 :
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79 | 7c23b892 | balrog | /* default to E1000_DEV_ID_82540EM */ 0xc20 |
80 | 7c23b892 | balrog | }; |
81 | 7c23b892 | balrog | |
82 | 7c23b892 | balrog | typedef struct E1000State_st { |
83 | 7c23b892 | balrog | PCIDevice dev; |
84 | a03e2aec | Mark McLoughlin | NICState *nic; |
85 | fbdaa002 | Gerd Hoffmann | NICConf conf; |
86 | ad00a9b9 | Avi Kivity | MemoryRegion mmio; |
87 | ad00a9b9 | Avi Kivity | MemoryRegion io; |
88 | 7c23b892 | balrog | |
89 | 7c23b892 | balrog | uint32_t mac_reg[0x8000];
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90 | 7c23b892 | balrog | uint16_t phy_reg[0x20];
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91 | 7c23b892 | balrog | uint16_t eeprom_data[64];
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92 | 7c23b892 | balrog | |
93 | 7c23b892 | balrog | uint32_t rxbuf_size; |
94 | 7c23b892 | balrog | uint32_t rxbuf_min_shift; |
95 | 7c23b892 | balrog | int check_rxov;
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96 | 7c23b892 | balrog | struct e1000_tx {
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97 | 7c23b892 | balrog | unsigned char header[256]; |
98 | 8f2e8d1f | aliguori | unsigned char vlan_header[4]; |
99 | b10fec9b | Stefan Weil | /* Fields vlan and data must not be reordered or separated. */
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100 | 8f2e8d1f | aliguori | unsigned char vlan[4]; |
101 | 7c23b892 | balrog | unsigned char data[0x10000]; |
102 | 7c23b892 | balrog | uint16_t size; |
103 | 7c23b892 | balrog | unsigned char sum_needed; |
104 | 8f2e8d1f | aliguori | unsigned char vlan_needed; |
105 | 7c23b892 | balrog | uint8_t ipcss; |
106 | 7c23b892 | balrog | uint8_t ipcso; |
107 | 7c23b892 | balrog | uint16_t ipcse; |
108 | 7c23b892 | balrog | uint8_t tucss; |
109 | 7c23b892 | balrog | uint8_t tucso; |
110 | 7c23b892 | balrog | uint16_t tucse; |
111 | 7c23b892 | balrog | uint8_t hdr_len; |
112 | 7c23b892 | balrog | uint16_t mss; |
113 | 7c23b892 | balrog | uint32_t paylen; |
114 | 7c23b892 | balrog | uint16_t tso_frames; |
115 | 7c23b892 | balrog | char tse;
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116 | b6c4f71f | blueswir1 | int8_t ip; |
117 | b6c4f71f | blueswir1 | int8_t tcp; |
118 | 1b0009db | balrog | char cptse; // current packet tse bit |
119 | 7c23b892 | balrog | } tx; |
120 | 7c23b892 | balrog | |
121 | 7c23b892 | balrog | struct {
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122 | 7c23b892 | balrog | uint32_t val_in; // shifted in from guest driver
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123 | 7c23b892 | balrog | uint16_t bitnum_in; |
124 | 7c23b892 | balrog | uint16_t bitnum_out; |
125 | 7c23b892 | balrog | uint16_t reading; |
126 | 7c23b892 | balrog | uint32_t old_eecd; |
127 | 7c23b892 | balrog | } eecd_state; |
128 | 7c23b892 | balrog | } E1000State; |
129 | 7c23b892 | balrog | |
130 | 7c23b892 | balrog | #define defreg(x) x = (E1000_##x>>2) |
131 | 7c23b892 | balrog | enum {
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132 | 7c23b892 | balrog | defreg(CTRL), defreg(EECD), defreg(EERD), defreg(GPRC), |
133 | 7c23b892 | balrog | defreg(GPTC), defreg(ICR), defreg(ICS), defreg(IMC), |
134 | 7c23b892 | balrog | defreg(IMS), defreg(LEDCTL), defreg(MANC), defreg(MDIC), |
135 | 7c23b892 | balrog | defreg(MPC), defreg(PBA), defreg(RCTL), defreg(RDBAH), |
136 | 7c23b892 | balrog | defreg(RDBAL), defreg(RDH), defreg(RDLEN), defreg(RDT), |
137 | 7c23b892 | balrog | defreg(STATUS), defreg(SWSM), defreg(TCTL), defreg(TDBAH), |
138 | 7c23b892 | balrog | defreg(TDBAL), defreg(TDH), defreg(TDLEN), defreg(TDT), |
139 | 7c23b892 | balrog | defreg(TORH), defreg(TORL), defreg(TOTH), defreg(TOTL), |
140 | 7c23b892 | balrog | defreg(TPR), defreg(TPT), defreg(TXDCTL), defreg(WUFC), |
141 | 8f2e8d1f | aliguori | defreg(RA), defreg(MTA), defreg(CRCERRS),defreg(VFTA), |
142 | 8f2e8d1f | aliguori | defreg(VET), |
143 | 7c23b892 | balrog | }; |
144 | 7c23b892 | balrog | |
145 | 7c23b892 | balrog | enum { PHY_R = 1, PHY_W = 2, PHY_RW = PHY_R | PHY_W }; |
146 | 88b4e9db | blueswir1 | static const char phy_regcap[0x20] = { |
147 | 7c23b892 | balrog | [PHY_STATUS] = PHY_R, [M88E1000_EXT_PHY_SPEC_CTRL] = PHY_RW, |
148 | 7c23b892 | balrog | [PHY_ID1] = PHY_R, [M88E1000_PHY_SPEC_CTRL] = PHY_RW, |
149 | 7c23b892 | balrog | [PHY_CTRL] = PHY_RW, [PHY_1000T_CTRL] = PHY_RW, |
150 | 7c23b892 | balrog | [PHY_LP_ABILITY] = PHY_R, [PHY_1000T_STATUS] = PHY_R, |
151 | 7c23b892 | balrog | [PHY_AUTONEG_ADV] = PHY_RW, [M88E1000_RX_ERR_CNTR] = PHY_R, |
152 | 700f6e2c | aurel32 | [PHY_ID2] = PHY_R, [M88E1000_PHY_SPEC_STATUS] = PHY_R |
153 | 7c23b892 | balrog | }; |
154 | 7c23b892 | balrog | |
155 | 7c23b892 | balrog | static void |
156 | 7c23b892 | balrog | set_interrupt_cause(E1000State *s, int index, uint32_t val)
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157 | 7c23b892 | balrog | { |
158 | 7c23b892 | balrog | if (val)
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159 | 7c23b892 | balrog | val |= E1000_ICR_INT_ASSERTED; |
160 | 7c23b892 | balrog | s->mac_reg[ICR] = val; |
161 | b1332393 | Bill Paul | s->mac_reg[ICS] = val; |
162 | bc26e55a | Blue Swirl | qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0); |
163 | 7c23b892 | balrog | } |
164 | 7c23b892 | balrog | |
165 | 7c23b892 | balrog | static void |
166 | 7c23b892 | balrog | set_ics(E1000State *s, int index, uint32_t val)
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167 | 7c23b892 | balrog | { |
168 | 7c23b892 | balrog | DBGOUT(INTERRUPT, "set_ics %x, ICR %x, IMR %x\n", val, s->mac_reg[ICR],
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169 | 7c23b892 | balrog | s->mac_reg[IMS]); |
170 | 7c23b892 | balrog | set_interrupt_cause(s, 0, val | s->mac_reg[ICR]);
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171 | 7c23b892 | balrog | } |
172 | 7c23b892 | balrog | |
173 | 7c23b892 | balrog | static int |
174 | 7c23b892 | balrog | rxbufsize(uint32_t v) |
175 | 7c23b892 | balrog | { |
176 | 7c23b892 | balrog | v &= E1000_RCTL_BSEX | E1000_RCTL_SZ_16384 | E1000_RCTL_SZ_8192 | |
177 | 7c23b892 | balrog | E1000_RCTL_SZ_4096 | E1000_RCTL_SZ_2048 | E1000_RCTL_SZ_1024 | |
178 | 7c23b892 | balrog | E1000_RCTL_SZ_512 | E1000_RCTL_SZ_256; |
179 | 7c23b892 | balrog | switch (v) {
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180 | 7c23b892 | balrog | case E1000_RCTL_BSEX | E1000_RCTL_SZ_16384:
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181 | 7c23b892 | balrog | return 16384; |
182 | 7c23b892 | balrog | case E1000_RCTL_BSEX | E1000_RCTL_SZ_8192:
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183 | 7c23b892 | balrog | return 8192; |
184 | 7c23b892 | balrog | case E1000_RCTL_BSEX | E1000_RCTL_SZ_4096:
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185 | 7c23b892 | balrog | return 4096; |
186 | 7c23b892 | balrog | case E1000_RCTL_SZ_1024:
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187 | 7c23b892 | balrog | return 1024; |
188 | 7c23b892 | balrog | case E1000_RCTL_SZ_512:
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189 | 7c23b892 | balrog | return 512; |
190 | 7c23b892 | balrog | case E1000_RCTL_SZ_256:
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191 | 7c23b892 | balrog | return 256; |
192 | 7c23b892 | balrog | } |
193 | 7c23b892 | balrog | return 2048; |
194 | 7c23b892 | balrog | } |
195 | 7c23b892 | balrog | |
196 | 7c23b892 | balrog | static void |
197 | cab3c825 | Kevin Wolf | set_ctrl(E1000State *s, int index, uint32_t val)
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198 | cab3c825 | Kevin Wolf | { |
199 | cab3c825 | Kevin Wolf | /* RST is self clearing */
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200 | cab3c825 | Kevin Wolf | s->mac_reg[CTRL] = val & ~E1000_CTRL_RST; |
201 | cab3c825 | Kevin Wolf | } |
202 | cab3c825 | Kevin Wolf | |
203 | cab3c825 | Kevin Wolf | static void |
204 | 7c23b892 | balrog | set_rx_control(E1000State *s, int index, uint32_t val)
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205 | 7c23b892 | balrog | { |
206 | 7c23b892 | balrog | s->mac_reg[RCTL] = val; |
207 | 7c23b892 | balrog | s->rxbuf_size = rxbufsize(val); |
208 | 7c23b892 | balrog | s->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1; |
209 | 7c23b892 | balrog | DBGOUT(RX, "RCTL: %d, mac_reg[RCTL] = 0x%x\n", s->mac_reg[RDT],
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210 | 7c23b892 | balrog | s->mac_reg[RCTL]); |
211 | 7c23b892 | balrog | } |
212 | 7c23b892 | balrog | |
213 | 7c23b892 | balrog | static void |
214 | 7c23b892 | balrog | set_mdic(E1000State *s, int index, uint32_t val)
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215 | 7c23b892 | balrog | { |
216 | 7c23b892 | balrog | uint32_t data = val & E1000_MDIC_DATA_MASK; |
217 | 7c23b892 | balrog | uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); |
218 | 7c23b892 | balrog | |
219 | 7c23b892 | balrog | if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) // phy # |
220 | 7c23b892 | balrog | val = s->mac_reg[MDIC] | E1000_MDIC_ERROR; |
221 | 7c23b892 | balrog | else if (val & E1000_MDIC_OP_READ) { |
222 | 7c23b892 | balrog | DBGOUT(MDIC, "MDIC read reg 0x%x\n", addr);
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223 | 7c23b892 | balrog | if (!(phy_regcap[addr] & PHY_R)) {
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224 | 7c23b892 | balrog | DBGOUT(MDIC, "MDIC read reg %x unhandled\n", addr);
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225 | 7c23b892 | balrog | val |= E1000_MDIC_ERROR; |
226 | 7c23b892 | balrog | } else
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227 | 7c23b892 | balrog | val = (val ^ data) | s->phy_reg[addr]; |
228 | 7c23b892 | balrog | } else if (val & E1000_MDIC_OP_WRITE) { |
229 | 7c23b892 | balrog | DBGOUT(MDIC, "MDIC write reg 0x%x, value 0x%x\n", addr, data);
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230 | 7c23b892 | balrog | if (!(phy_regcap[addr] & PHY_W)) {
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231 | 7c23b892 | balrog | DBGOUT(MDIC, "MDIC write reg %x unhandled\n", addr);
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232 | 7c23b892 | balrog | val |= E1000_MDIC_ERROR; |
233 | 7c23b892 | balrog | } else
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234 | 7c23b892 | balrog | s->phy_reg[addr] = data; |
235 | 7c23b892 | balrog | } |
236 | 7c23b892 | balrog | s->mac_reg[MDIC] = val | E1000_MDIC_READY; |
237 | 7c23b892 | balrog | set_ics(s, 0, E1000_ICR_MDAC);
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238 | 7c23b892 | balrog | } |
239 | 7c23b892 | balrog | |
240 | 7c23b892 | balrog | static uint32_t
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241 | 7c23b892 | balrog | get_eecd(E1000State *s, int index)
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242 | 7c23b892 | balrog | { |
243 | 7c23b892 | balrog | uint32_t ret = E1000_EECD_PRES|E1000_EECD_GNT | s->eecd_state.old_eecd; |
244 | 7c23b892 | balrog | |
245 | 7c23b892 | balrog | DBGOUT(EEPROM, "reading eeprom bit %d (reading %d)\n",
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246 | 7c23b892 | balrog | s->eecd_state.bitnum_out, s->eecd_state.reading); |
247 | 7c23b892 | balrog | if (!s->eecd_state.reading ||
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248 | 7c23b892 | balrog | ((s->eeprom_data[(s->eecd_state.bitnum_out >> 4) & 0x3f] >> |
249 | 7c23b892 | balrog | ((s->eecd_state.bitnum_out & 0xf) ^ 0xf))) & 1) |
250 | 7c23b892 | balrog | ret |= E1000_EECD_DO; |
251 | 7c23b892 | balrog | return ret;
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252 | 7c23b892 | balrog | } |
253 | 7c23b892 | balrog | |
254 | 7c23b892 | balrog | static void |
255 | 7c23b892 | balrog | set_eecd(E1000State *s, int index, uint32_t val)
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256 | 7c23b892 | balrog | { |
257 | 7c23b892 | balrog | uint32_t oldval = s->eecd_state.old_eecd; |
258 | 7c23b892 | balrog | |
259 | 7c23b892 | balrog | s->eecd_state.old_eecd = val & (E1000_EECD_SK | E1000_EECD_CS | |
260 | 7c23b892 | balrog | E1000_EECD_DI|E1000_EECD_FWE_MASK|E1000_EECD_REQ); |
261 | 9651ac55 | Izumi Tsutsui | if (!(E1000_EECD_CS & val)) // CS inactive; nothing to do |
262 | 9651ac55 | Izumi Tsutsui | return;
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263 | 9651ac55 | Izumi Tsutsui | if (E1000_EECD_CS & (val ^ oldval)) { // CS rise edge; reset state |
264 | 9651ac55 | Izumi Tsutsui | s->eecd_state.val_in = 0;
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265 | 9651ac55 | Izumi Tsutsui | s->eecd_state.bitnum_in = 0;
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266 | 9651ac55 | Izumi Tsutsui | s->eecd_state.bitnum_out = 0;
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267 | 9651ac55 | Izumi Tsutsui | s->eecd_state.reading = 0;
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268 | 9651ac55 | Izumi Tsutsui | } |
269 | 7c23b892 | balrog | if (!(E1000_EECD_SK & (val ^ oldval))) // no clock edge |
270 | 7c23b892 | balrog | return;
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271 | 7c23b892 | balrog | if (!(E1000_EECD_SK & val)) { // falling edge |
272 | 7c23b892 | balrog | s->eecd_state.bitnum_out++; |
273 | 7c23b892 | balrog | return;
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274 | 7c23b892 | balrog | } |
275 | 7c23b892 | balrog | s->eecd_state.val_in <<= 1;
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276 | 7c23b892 | balrog | if (val & E1000_EECD_DI)
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277 | 7c23b892 | balrog | s->eecd_state.val_in |= 1;
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278 | 7c23b892 | balrog | if (++s->eecd_state.bitnum_in == 9 && !s->eecd_state.reading) { |
279 | 7c23b892 | balrog | s->eecd_state.bitnum_out = ((s->eecd_state.val_in & 0x3f)<<4)-1; |
280 | 7c23b892 | balrog | s->eecd_state.reading = (((s->eecd_state.val_in >> 6) & 7) == |
281 | 7c23b892 | balrog | EEPROM_READ_OPCODE_MICROWIRE); |
282 | 7c23b892 | balrog | } |
283 | 7c23b892 | balrog | DBGOUT(EEPROM, "eeprom bitnum in %d out %d, reading %d\n",
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284 | 7c23b892 | balrog | s->eecd_state.bitnum_in, s->eecd_state.bitnum_out, |
285 | 7c23b892 | balrog | s->eecd_state.reading); |
286 | 7c23b892 | balrog | } |
287 | 7c23b892 | balrog | |
288 | 7c23b892 | balrog | static uint32_t
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289 | 7c23b892 | balrog | flash_eerd_read(E1000State *s, int x)
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290 | 7c23b892 | balrog | { |
291 | 7c23b892 | balrog | unsigned int index, r = s->mac_reg[EERD] & ~E1000_EEPROM_RW_REG_START; |
292 | 7c23b892 | balrog | |
293 | b1332393 | Bill Paul | if ((s->mac_reg[EERD] & E1000_EEPROM_RW_REG_START) == 0) |
294 | b1332393 | Bill Paul | return (s->mac_reg[EERD]);
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295 | b1332393 | Bill Paul | |
296 | 7c23b892 | balrog | if ((index = r >> E1000_EEPROM_RW_ADDR_SHIFT) > EEPROM_CHECKSUM_REG)
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297 | b1332393 | Bill Paul | return (E1000_EEPROM_RW_REG_DONE | r);
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298 | b1332393 | Bill Paul | |
299 | b1332393 | Bill Paul | return ((s->eeprom_data[index] << E1000_EEPROM_RW_REG_DATA) |
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300 | b1332393 | Bill Paul | E1000_EEPROM_RW_REG_DONE | r); |
301 | 7c23b892 | balrog | } |
302 | 7c23b892 | balrog | |
303 | 7c23b892 | balrog | static void |
304 | 7c23b892 | balrog | putsum(uint8_t *data, uint32_t n, uint32_t sloc, uint32_t css, uint32_t cse) |
305 | 7c23b892 | balrog | { |
306 | c6a6a5e3 | aliguori | uint32_t sum; |
307 | c6a6a5e3 | aliguori | |
308 | 7c23b892 | balrog | if (cse && cse < n)
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309 | 7c23b892 | balrog | n = cse + 1;
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310 | c6a6a5e3 | aliguori | if (sloc < n-1) { |
311 | c6a6a5e3 | aliguori | sum = net_checksum_add(n-css, data+css); |
312 | 7c23b892 | balrog | cpu_to_be16wu((uint16_t *)(data + sloc), |
313 | c6a6a5e3 | aliguori | net_checksum_finish(sum)); |
314 | c6a6a5e3 | aliguori | } |
315 | 7c23b892 | balrog | } |
316 | 7c23b892 | balrog | |
317 | 8f2e8d1f | aliguori | static inline int |
318 | 8f2e8d1f | aliguori | vlan_enabled(E1000State *s) |
319 | 8f2e8d1f | aliguori | { |
320 | 8f2e8d1f | aliguori | return ((s->mac_reg[CTRL] & E1000_CTRL_VME) != 0); |
321 | 8f2e8d1f | aliguori | } |
322 | 8f2e8d1f | aliguori | |
323 | 8f2e8d1f | aliguori | static inline int |
324 | 8f2e8d1f | aliguori | vlan_rx_filter_enabled(E1000State *s) |
325 | 8f2e8d1f | aliguori | { |
326 | 8f2e8d1f | aliguori | return ((s->mac_reg[RCTL] & E1000_RCTL_VFE) != 0); |
327 | 8f2e8d1f | aliguori | } |
328 | 8f2e8d1f | aliguori | |
329 | 8f2e8d1f | aliguori | static inline int |
330 | 8f2e8d1f | aliguori | is_vlan_packet(E1000State *s, const uint8_t *buf)
|
331 | 8f2e8d1f | aliguori | { |
332 | 8f2e8d1f | aliguori | return (be16_to_cpup((uint16_t *)(buf + 12)) == |
333 | 8f2e8d1f | aliguori | le16_to_cpup((uint16_t *)(s->mac_reg + VET))); |
334 | 8f2e8d1f | aliguori | } |
335 | 8f2e8d1f | aliguori | |
336 | 8f2e8d1f | aliguori | static inline int |
337 | 8f2e8d1f | aliguori | is_vlan_txd(uint32_t txd_lower) |
338 | 8f2e8d1f | aliguori | { |
339 | 8f2e8d1f | aliguori | return ((txd_lower & E1000_TXD_CMD_VLE) != 0); |
340 | 8f2e8d1f | aliguori | } |
341 | 8f2e8d1f | aliguori | |
342 | 55e8d1ce | Michael S. Tsirkin | /* FCS aka Ethernet CRC-32. We don't get it from backends and can't
|
343 | 55e8d1ce | Michael S. Tsirkin | * fill it in, just pad descriptor length by 4 bytes unless guest
|
344 | a05e8a6e | Michael S. Tsirkin | * told us to strip it off the packet. */
|
345 | 55e8d1ce | Michael S. Tsirkin | static inline int |
346 | 55e8d1ce | Michael S. Tsirkin | fcs_len(E1000State *s) |
347 | 55e8d1ce | Michael S. Tsirkin | { |
348 | 55e8d1ce | Michael S. Tsirkin | return (s->mac_reg[RCTL] & E1000_RCTL_SECRC) ? 0 : 4; |
349 | 55e8d1ce | Michael S. Tsirkin | } |
350 | 55e8d1ce | Michael S. Tsirkin | |
351 | 7c23b892 | balrog | static void |
352 | 7c23b892 | balrog | xmit_seg(E1000State *s) |
353 | 7c23b892 | balrog | { |
354 | 7c23b892 | balrog | uint16_t len, *sp; |
355 | 7c23b892 | balrog | unsigned int frames = s->tx.tso_frames, css, sofar, n; |
356 | 7c23b892 | balrog | struct e1000_tx *tp = &s->tx;
|
357 | 7c23b892 | balrog | |
358 | 1b0009db | balrog | if (tp->tse && tp->cptse) {
|
359 | 7c23b892 | balrog | css = tp->ipcss; |
360 | 7c23b892 | balrog | DBGOUT(TXSUM, "frames %d size %d ipcss %d\n",
|
361 | 7c23b892 | balrog | frames, tp->size, css); |
362 | 7c23b892 | balrog | if (tp->ip) { // IPv4 |
363 | 7c23b892 | balrog | cpu_to_be16wu((uint16_t *)(tp->data+css+2),
|
364 | 7c23b892 | balrog | tp->size - css); |
365 | 7c23b892 | balrog | cpu_to_be16wu((uint16_t *)(tp->data+css+4),
|
366 | 7c23b892 | balrog | be16_to_cpup((uint16_t *)(tp->data+css+4))+frames);
|
367 | 7c23b892 | balrog | } else // IPv6 |
368 | 7c23b892 | balrog | cpu_to_be16wu((uint16_t *)(tp->data+css+4),
|
369 | 7c23b892 | balrog | tp->size - css); |
370 | 7c23b892 | balrog | css = tp->tucss; |
371 | 7c23b892 | balrog | len = tp->size - css; |
372 | 7c23b892 | balrog | DBGOUT(TXSUM, "tcp %d tucss %d len %d\n", tp->tcp, css, len);
|
373 | 7c23b892 | balrog | if (tp->tcp) {
|
374 | 7c23b892 | balrog | sofar = frames * tp->mss; |
375 | 7c23b892 | balrog | cpu_to_be32wu((uint32_t *)(tp->data+css+4), // seq |
376 | 88738c09 | aurel32 | be32_to_cpupu((uint32_t *)(tp->data+css+4))+sofar);
|
377 | 7c23b892 | balrog | if (tp->paylen - sofar > tp->mss)
|
378 | 7c23b892 | balrog | tp->data[css + 13] &= ~9; // PSH, FIN |
379 | 7c23b892 | balrog | } else // UDP |
380 | 7c23b892 | balrog | cpu_to_be16wu((uint16_t *)(tp->data+css+4), len);
|
381 | 7c23b892 | balrog | if (tp->sum_needed & E1000_TXD_POPTS_TXSM) {
|
382 | e685b4eb | Alex Williamson | unsigned int phsum; |
383 | 7c23b892 | balrog | // add pseudo-header length before checksum calculation
|
384 | 7c23b892 | balrog | sp = (uint16_t *)(tp->data + tp->tucso); |
385 | e685b4eb | Alex Williamson | phsum = be16_to_cpup(sp) + len; |
386 | e685b4eb | Alex Williamson | phsum = (phsum >> 16) + (phsum & 0xffff); |
387 | e685b4eb | Alex Williamson | cpu_to_be16wu(sp, phsum); |
388 | 7c23b892 | balrog | } |
389 | 7c23b892 | balrog | tp->tso_frames++; |
390 | 7c23b892 | balrog | } |
391 | 7c23b892 | balrog | |
392 | 7c23b892 | balrog | if (tp->sum_needed & E1000_TXD_POPTS_TXSM)
|
393 | 7c23b892 | balrog | putsum(tp->data, tp->size, tp->tucso, tp->tucss, tp->tucse); |
394 | 7c23b892 | balrog | if (tp->sum_needed & E1000_TXD_POPTS_IXSM)
|
395 | 7c23b892 | balrog | putsum(tp->data, tp->size, tp->ipcso, tp->ipcss, tp->ipcse); |
396 | 8f2e8d1f | aliguori | if (tp->vlan_needed) {
|
397 | b10fec9b | Stefan Weil | memmove(tp->vlan, tp->data, 4);
|
398 | b10fec9b | Stefan Weil | memmove(tp->data, tp->data + 4, 8); |
399 | 8f2e8d1f | aliguori | memcpy(tp->data + 8, tp->vlan_header, 4); |
400 | a03e2aec | Mark McLoughlin | qemu_send_packet(&s->nic->nc, tp->vlan, tp->size + 4);
|
401 | 8f2e8d1f | aliguori | } else
|
402 | a03e2aec | Mark McLoughlin | qemu_send_packet(&s->nic->nc, tp->data, tp->size); |
403 | 7c23b892 | balrog | s->mac_reg[TPT]++; |
404 | 7c23b892 | balrog | s->mac_reg[GPTC]++; |
405 | 7c23b892 | balrog | n = s->mac_reg[TOTL]; |
406 | 7c23b892 | balrog | if ((s->mac_reg[TOTL] += s->tx.size) < n)
|
407 | 7c23b892 | balrog | s->mac_reg[TOTH]++; |
408 | 7c23b892 | balrog | } |
409 | 7c23b892 | balrog | |
410 | 7c23b892 | balrog | static void |
411 | 7c23b892 | balrog | process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
|
412 | 7c23b892 | balrog | { |
413 | 7c23b892 | balrog | uint32_t txd_lower = le32_to_cpu(dp->lower.data); |
414 | 7c23b892 | balrog | uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D); |
415 | 7c23b892 | balrog | unsigned int split_size = txd_lower & 0xffff, bytes, sz, op; |
416 | 7c23b892 | balrog | unsigned int msh = 0xfffff, hdr = 0; |
417 | 7c23b892 | balrog | uint64_t addr; |
418 | 7c23b892 | balrog | struct e1000_context_desc *xp = (struct e1000_context_desc *)dp; |
419 | 7c23b892 | balrog | struct e1000_tx *tp = &s->tx;
|
420 | 7c23b892 | balrog | |
421 | 7c23b892 | balrog | if (dtype == E1000_TXD_CMD_DEXT) { // context descriptor |
422 | 7c23b892 | balrog | op = le32_to_cpu(xp->cmd_and_length); |
423 | 7c23b892 | balrog | tp->ipcss = xp->lower_setup.ip_fields.ipcss; |
424 | 7c23b892 | balrog | tp->ipcso = xp->lower_setup.ip_fields.ipcso; |
425 | 7c23b892 | balrog | tp->ipcse = le16_to_cpu(xp->lower_setup.ip_fields.ipcse); |
426 | 7c23b892 | balrog | tp->tucss = xp->upper_setup.tcp_fields.tucss; |
427 | 7c23b892 | balrog | tp->tucso = xp->upper_setup.tcp_fields.tucso; |
428 | 7c23b892 | balrog | tp->tucse = le16_to_cpu(xp->upper_setup.tcp_fields.tucse); |
429 | 7c23b892 | balrog | tp->paylen = op & 0xfffff;
|
430 | 7c23b892 | balrog | tp->hdr_len = xp->tcp_seg_setup.fields.hdr_len; |
431 | 7c23b892 | balrog | tp->mss = le16_to_cpu(xp->tcp_seg_setup.fields.mss); |
432 | 7c23b892 | balrog | tp->ip = (op & E1000_TXD_CMD_IP) ? 1 : 0; |
433 | 7c23b892 | balrog | tp->tcp = (op & E1000_TXD_CMD_TCP) ? 1 : 0; |
434 | 7c23b892 | balrog | tp->tse = (op & E1000_TXD_CMD_TSE) ? 1 : 0; |
435 | 7c23b892 | balrog | tp->tso_frames = 0;
|
436 | 7c23b892 | balrog | if (tp->tucso == 0) { // this is probably wrong |
437 | 7c23b892 | balrog | DBGOUT(TXSUM, "TCP/UDP: cso 0!\n");
|
438 | 7c23b892 | balrog | tp->tucso = tp->tucss + (tp->tcp ? 16 : 6); |
439 | 7c23b892 | balrog | } |
440 | 7c23b892 | balrog | return;
|
441 | 1b0009db | balrog | } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) { |
442 | 1b0009db | balrog | // data descriptor
|
443 | 735e77ec | Stefan Hajnoczi | if (tp->size == 0) { |
444 | 735e77ec | Stefan Hajnoczi | tp->sum_needed = le32_to_cpu(dp->upper.data) >> 8;
|
445 | 735e77ec | Stefan Hajnoczi | } |
446 | 1b0009db | balrog | tp->cptse = ( txd_lower & E1000_TXD_CMD_TSE ) ? 1 : 0; |
447 | 43ad7e3e | Jes Sorensen | } else {
|
448 | 1b0009db | balrog | // legacy descriptor
|
449 | 1b0009db | balrog | tp->cptse = 0;
|
450 | 43ad7e3e | Jes Sorensen | } |
451 | 7c23b892 | balrog | |
452 | 8f2e8d1f | aliguori | if (vlan_enabled(s) && is_vlan_txd(txd_lower) &&
|
453 | 8f2e8d1f | aliguori | (tp->cptse || txd_lower & E1000_TXD_CMD_EOP)) { |
454 | 8f2e8d1f | aliguori | tp->vlan_needed = 1;
|
455 | 8f2e8d1f | aliguori | cpu_to_be16wu((uint16_t *)(tp->vlan_header), |
456 | 8f2e8d1f | aliguori | le16_to_cpup((uint16_t *)(s->mac_reg + VET))); |
457 | 8f2e8d1f | aliguori | cpu_to_be16wu((uint16_t *)(tp->vlan_header + 2),
|
458 | 8f2e8d1f | aliguori | le16_to_cpu(dp->upper.fields.special)); |
459 | 8f2e8d1f | aliguori | } |
460 | 8f2e8d1f | aliguori | |
461 | 7c23b892 | balrog | addr = le64_to_cpu(dp->buffer_addr); |
462 | 1b0009db | balrog | if (tp->tse && tp->cptse) {
|
463 | 7c23b892 | balrog | hdr = tp->hdr_len; |
464 | 7c23b892 | balrog | msh = hdr + tp->mss; |
465 | 1b0009db | balrog | do {
|
466 | 1b0009db | balrog | bytes = split_size; |
467 | 1b0009db | balrog | if (tp->size + bytes > msh)
|
468 | 1b0009db | balrog | bytes = msh - tp->size; |
469 | 62ecbd35 | Eduard - Gabriel Munteanu | pci_dma_read(&s->dev, addr, tp->data + tp->size, bytes); |
470 | 1b0009db | balrog | if ((sz = tp->size + bytes) >= hdr && tp->size < hdr)
|
471 | 1b0009db | balrog | memmove(tp->header, tp->data, hdr); |
472 | 1b0009db | balrog | tp->size = sz; |
473 | 1b0009db | balrog | addr += bytes; |
474 | 1b0009db | balrog | if (sz == msh) {
|
475 | 1b0009db | balrog | xmit_seg(s); |
476 | 1b0009db | balrog | memmove(tp->data, tp->header, hdr); |
477 | 1b0009db | balrog | tp->size = hdr; |
478 | 1b0009db | balrog | } |
479 | 1b0009db | balrog | } while (split_size -= bytes);
|
480 | 1b0009db | balrog | } else if (!tp->tse && tp->cptse) { |
481 | 1b0009db | balrog | // context descriptor TSE is not set, while data descriptor TSE is set
|
482 | 1b0009db | balrog | DBGOUT(TXERR, "TCP segmentaion Error\n");
|
483 | 1b0009db | balrog | } else {
|
484 | 62ecbd35 | Eduard - Gabriel Munteanu | pci_dma_read(&s->dev, addr, tp->data + tp->size, split_size); |
485 | 1b0009db | balrog | tp->size += split_size; |
486 | 7c23b892 | balrog | } |
487 | 7c23b892 | balrog | |
488 | 7c23b892 | balrog | if (!(txd_lower & E1000_TXD_CMD_EOP))
|
489 | 7c23b892 | balrog | return;
|
490 | 1b0009db | balrog | if (!(tp->tse && tp->cptse && tp->size < hdr))
|
491 | 7c23b892 | balrog | xmit_seg(s); |
492 | 7c23b892 | balrog | tp->tso_frames = 0;
|
493 | 7c23b892 | balrog | tp->sum_needed = 0;
|
494 | 8f2e8d1f | aliguori | tp->vlan_needed = 0;
|
495 | 7c23b892 | balrog | tp->size = 0;
|
496 | 1b0009db | balrog | tp->cptse = 0;
|
497 | 7c23b892 | balrog | } |
498 | 7c23b892 | balrog | |
499 | 7c23b892 | balrog | static uint32_t
|
500 | 62ecbd35 | Eduard - Gabriel Munteanu | txdesc_writeback(E1000State *s, dma_addr_t base, struct e1000_tx_desc *dp)
|
501 | 7c23b892 | balrog | { |
502 | 7c23b892 | balrog | uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data); |
503 | 7c23b892 | balrog | |
504 | 7c23b892 | balrog | if (!(txd_lower & (E1000_TXD_CMD_RS|E1000_TXD_CMD_RPS)))
|
505 | 7c23b892 | balrog | return 0; |
506 | 7c23b892 | balrog | txd_upper = (le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD) & |
507 | 7c23b892 | balrog | ~(E1000_TXD_STAT_EC | E1000_TXD_STAT_LC | E1000_TXD_STAT_TU); |
508 | 7c23b892 | balrog | dp->upper.data = cpu_to_le32(txd_upper); |
509 | 62ecbd35 | Eduard - Gabriel Munteanu | pci_dma_write(&s->dev, base + ((char *)&dp->upper - (char *)dp), |
510 | 00c3a05b | David Gibson | &dp->upper, sizeof(dp->upper));
|
511 | 7c23b892 | balrog | return E1000_ICR_TXDW;
|
512 | 7c23b892 | balrog | } |
513 | 7c23b892 | balrog | |
514 | d17161f6 | Kevin Wolf | static uint64_t tx_desc_base(E1000State *s)
|
515 | d17161f6 | Kevin Wolf | { |
516 | d17161f6 | Kevin Wolf | uint64_t bah = s->mac_reg[TDBAH]; |
517 | d17161f6 | Kevin Wolf | uint64_t bal = s->mac_reg[TDBAL] & ~0xf;
|
518 | d17161f6 | Kevin Wolf | |
519 | d17161f6 | Kevin Wolf | return (bah << 32) + bal; |
520 | d17161f6 | Kevin Wolf | } |
521 | d17161f6 | Kevin Wolf | |
522 | 7c23b892 | balrog | static void |
523 | 7c23b892 | balrog | start_xmit(E1000State *s) |
524 | 7c23b892 | balrog | { |
525 | 62ecbd35 | Eduard - Gabriel Munteanu | dma_addr_t base; |
526 | 7c23b892 | balrog | struct e1000_tx_desc desc;
|
527 | 7c23b892 | balrog | uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE; |
528 | 7c23b892 | balrog | |
529 | 7c23b892 | balrog | if (!(s->mac_reg[TCTL] & E1000_TCTL_EN)) {
|
530 | 7c23b892 | balrog | DBGOUT(TX, "tx disabled\n");
|
531 | 7c23b892 | balrog | return;
|
532 | 7c23b892 | balrog | } |
533 | 7c23b892 | balrog | |
534 | 7c23b892 | balrog | while (s->mac_reg[TDH] != s->mac_reg[TDT]) {
|
535 | d17161f6 | Kevin Wolf | base = tx_desc_base(s) + |
536 | 7c23b892 | balrog | sizeof(struct e1000_tx_desc) * s->mac_reg[TDH]; |
537 | 00c3a05b | David Gibson | pci_dma_read(&s->dev, base, &desc, sizeof(desc));
|
538 | 7c23b892 | balrog | |
539 | 7c23b892 | balrog | DBGOUT(TX, "index %d: %p : %x %x\n", s->mac_reg[TDH],
|
540 | 6106075b | ths | (void *)(intptr_t)desc.buffer_addr, desc.lower.data,
|
541 | 7c23b892 | balrog | desc.upper.data); |
542 | 7c23b892 | balrog | |
543 | 7c23b892 | balrog | process_tx_desc(s, &desc); |
544 | 62ecbd35 | Eduard - Gabriel Munteanu | cause |= txdesc_writeback(s, base, &desc); |
545 | 7c23b892 | balrog | |
546 | 7c23b892 | balrog | if (++s->mac_reg[TDH] * sizeof(desc) >= s->mac_reg[TDLEN]) |
547 | 7c23b892 | balrog | s->mac_reg[TDH] = 0;
|
548 | 7c23b892 | balrog | /*
|
549 | 7c23b892 | balrog | * the following could happen only if guest sw assigns
|
550 | 7c23b892 | balrog | * bogus values to TDT/TDLEN.
|
551 | 7c23b892 | balrog | * there's nothing too intelligent we could do about this.
|
552 | 7c23b892 | balrog | */
|
553 | 7c23b892 | balrog | if (s->mac_reg[TDH] == tdh_start) {
|
554 | 7c23b892 | balrog | DBGOUT(TXERR, "TDH wraparound @%x, TDT %x, TDLEN %x\n",
|
555 | 7c23b892 | balrog | tdh_start, s->mac_reg[TDT], s->mac_reg[TDLEN]); |
556 | 7c23b892 | balrog | break;
|
557 | 7c23b892 | balrog | } |
558 | 7c23b892 | balrog | } |
559 | 7c23b892 | balrog | set_ics(s, 0, cause);
|
560 | 7c23b892 | balrog | } |
561 | 7c23b892 | balrog | |
562 | 7c23b892 | balrog | static int |
563 | 7c23b892 | balrog | receive_filter(E1000State *s, const uint8_t *buf, int size) |
564 | 7c23b892 | balrog | { |
565 | af2960f9 | Blue Swirl | static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; |
566 | af2960f9 | Blue Swirl | static const int mta_shift[] = {4, 3, 2, 0}; |
567 | 7c23b892 | balrog | uint32_t f, rctl = s->mac_reg[RCTL], ra[2], *rp;
|
568 | 7c23b892 | balrog | |
569 | 8f2e8d1f | aliguori | if (is_vlan_packet(s, buf) && vlan_rx_filter_enabled(s)) {
|
570 | 8f2e8d1f | aliguori | uint16_t vid = be16_to_cpup((uint16_t *)(buf + 14));
|
571 | 8f2e8d1f | aliguori | uint32_t vfta = le32_to_cpup((uint32_t *)(s->mac_reg + VFTA) + |
572 | 8f2e8d1f | aliguori | ((vid >> 5) & 0x7f)); |
573 | 8f2e8d1f | aliguori | if ((vfta & (1 << (vid & 0x1f))) == 0) |
574 | 8f2e8d1f | aliguori | return 0; |
575 | 8f2e8d1f | aliguori | } |
576 | 8f2e8d1f | aliguori | |
577 | 7c23b892 | balrog | if (rctl & E1000_RCTL_UPE) // promiscuous |
578 | 7c23b892 | balrog | return 1; |
579 | 7c23b892 | balrog | |
580 | 7c23b892 | balrog | if ((buf[0] & 1) && (rctl & E1000_RCTL_MPE)) // promiscuous mcast |
581 | 7c23b892 | balrog | return 1; |
582 | 7c23b892 | balrog | |
583 | 7c23b892 | balrog | if ((rctl & E1000_RCTL_BAM) && !memcmp(buf, bcast, sizeof bcast)) |
584 | 7c23b892 | balrog | return 1; |
585 | 7c23b892 | balrog | |
586 | 7c23b892 | balrog | for (rp = s->mac_reg + RA; rp < s->mac_reg + RA + 32; rp += 2) { |
587 | 7c23b892 | balrog | if (!(rp[1] & E1000_RAH_AV)) |
588 | 7c23b892 | balrog | continue;
|
589 | 7c23b892 | balrog | ra[0] = cpu_to_le32(rp[0]); |
590 | 7c23b892 | balrog | ra[1] = cpu_to_le32(rp[1]); |
591 | 7c23b892 | balrog | if (!memcmp(buf, (uint8_t *)ra, 6)) { |
592 | 7c23b892 | balrog | DBGOUT(RXFILTER, |
593 | 7c23b892 | balrog | "unicast match[%d]: %02x:%02x:%02x:%02x:%02x:%02x\n",
|
594 | 7c23b892 | balrog | (int)(rp - s->mac_reg - RA)/2, |
595 | 7c23b892 | balrog | buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); |
596 | 7c23b892 | balrog | return 1; |
597 | 7c23b892 | balrog | } |
598 | 7c23b892 | balrog | } |
599 | 7c23b892 | balrog | DBGOUT(RXFILTER, "unicast mismatch: %02x:%02x:%02x:%02x:%02x:%02x\n",
|
600 | 7c23b892 | balrog | buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); |
601 | 7c23b892 | balrog | |
602 | 7c23b892 | balrog | f = mta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3];
|
603 | 7c23b892 | balrog | f = (((buf[5] << 8) | buf[4]) >> f) & 0xfff; |
604 | 7c23b892 | balrog | if (s->mac_reg[MTA + (f >> 5)] & (1 << (f & 0x1f))) |
605 | 7c23b892 | balrog | return 1; |
606 | 7c23b892 | balrog | DBGOUT(RXFILTER, |
607 | 7c23b892 | balrog | "dropping, inexact filter mismatch: %02x:%02x:%02x:%02x:%02x:%02x MO %d MTA[%d] %x\n",
|
608 | 7c23b892 | balrog | buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], |
609 | 7c23b892 | balrog | (rctl >> E1000_RCTL_MO_SHIFT) & 3, f >> 5, |
610 | 7c23b892 | balrog | s->mac_reg[MTA + (f >> 5)]);
|
611 | 7c23b892 | balrog | |
612 | 7c23b892 | balrog | return 0; |
613 | 7c23b892 | balrog | } |
614 | 7c23b892 | balrog | |
615 | 99ed7e30 | aliguori | static void |
616 | a03e2aec | Mark McLoughlin | e1000_set_link_status(VLANClientState *nc) |
617 | 99ed7e30 | aliguori | { |
618 | a03e2aec | Mark McLoughlin | E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
619 | 99ed7e30 | aliguori | uint32_t old_status = s->mac_reg[STATUS]; |
620 | 99ed7e30 | aliguori | |
621 | d4044c2a | Bjรธrn Mork | if (nc->link_down) {
|
622 | 99ed7e30 | aliguori | s->mac_reg[STATUS] &= ~E1000_STATUS_LU; |
623 | d4044c2a | Bjรธrn Mork | s->phy_reg[PHY_STATUS] &= ~MII_SR_LINK_STATUS; |
624 | d4044c2a | Bjรธrn Mork | } else {
|
625 | 99ed7e30 | aliguori | s->mac_reg[STATUS] |= E1000_STATUS_LU; |
626 | d4044c2a | Bjรธrn Mork | s->phy_reg[PHY_STATUS] |= MII_SR_LINK_STATUS; |
627 | d4044c2a | Bjรธrn Mork | } |
628 | 99ed7e30 | aliguori | |
629 | 99ed7e30 | aliguori | if (s->mac_reg[STATUS] != old_status)
|
630 | 99ed7e30 | aliguori | set_ics(s, 0, E1000_ICR_LSC);
|
631 | 99ed7e30 | aliguori | } |
632 | 99ed7e30 | aliguori | |
633 | 322fd48a | Michael S. Tsirkin | static bool e1000_has_rxbufs(E1000State *s, size_t total_size) |
634 | 322fd48a | Michael S. Tsirkin | { |
635 | 322fd48a | Michael S. Tsirkin | int bufs;
|
636 | 322fd48a | Michael S. Tsirkin | /* Fast-path short packets */
|
637 | 322fd48a | Michael S. Tsirkin | if (total_size <= s->rxbuf_size) {
|
638 | 322fd48a | Michael S. Tsirkin | return s->mac_reg[RDH] != s->mac_reg[RDT] || !s->check_rxov;
|
639 | 322fd48a | Michael S. Tsirkin | } |
640 | 322fd48a | Michael S. Tsirkin | if (s->mac_reg[RDH] < s->mac_reg[RDT]) {
|
641 | 322fd48a | Michael S. Tsirkin | bufs = s->mac_reg[RDT] - s->mac_reg[RDH]; |
642 | 322fd48a | Michael S. Tsirkin | } else if (s->mac_reg[RDH] > s->mac_reg[RDT] || !s->check_rxov) { |
643 | 322fd48a | Michael S. Tsirkin | bufs = s->mac_reg[RDLEN] / sizeof(struct e1000_rx_desc) + |
644 | 322fd48a | Michael S. Tsirkin | s->mac_reg[RDT] - s->mac_reg[RDH]; |
645 | 322fd48a | Michael S. Tsirkin | } else {
|
646 | 322fd48a | Michael S. Tsirkin | return false; |
647 | 322fd48a | Michael S. Tsirkin | } |
648 | 322fd48a | Michael S. Tsirkin | return total_size <= bufs * s->rxbuf_size;
|
649 | 322fd48a | Michael S. Tsirkin | } |
650 | 322fd48a | Michael S. Tsirkin | |
651 | 6cdfab28 | Michael S. Tsirkin | static int |
652 | 6cdfab28 | Michael S. Tsirkin | e1000_can_receive(VLANClientState *nc) |
653 | 6cdfab28 | Michael S. Tsirkin | { |
654 | 6cdfab28 | Michael S. Tsirkin | E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
655 | 6cdfab28 | Michael S. Tsirkin | |
656 | 6cdfab28 | Michael S. Tsirkin | return (s->mac_reg[RCTL] & E1000_RCTL_EN) && e1000_has_rxbufs(s, 1); |
657 | 6cdfab28 | Michael S. Tsirkin | } |
658 | 6cdfab28 | Michael S. Tsirkin | |
659 | d17161f6 | Kevin Wolf | static uint64_t rx_desc_base(E1000State *s)
|
660 | d17161f6 | Kevin Wolf | { |
661 | d17161f6 | Kevin Wolf | uint64_t bah = s->mac_reg[RDBAH]; |
662 | d17161f6 | Kevin Wolf | uint64_t bal = s->mac_reg[RDBAL] & ~0xf;
|
663 | d17161f6 | Kevin Wolf | |
664 | d17161f6 | Kevin Wolf | return (bah << 32) + bal; |
665 | d17161f6 | Kevin Wolf | } |
666 | d17161f6 | Kevin Wolf | |
667 | 4f1c942b | Mark McLoughlin | static ssize_t
|
668 | a03e2aec | Mark McLoughlin | e1000_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
|
669 | 7c23b892 | balrog | { |
670 | a03e2aec | Mark McLoughlin | E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
671 | 7c23b892 | balrog | struct e1000_rx_desc desc;
|
672 | 62ecbd35 | Eduard - Gabriel Munteanu | dma_addr_t base; |
673 | 7c23b892 | balrog | unsigned int n, rdt; |
674 | 7c23b892 | balrog | uint32_t rdh_start; |
675 | 8f2e8d1f | aliguori | uint16_t vlan_special = 0;
|
676 | 8f2e8d1f | aliguori | uint8_t vlan_status = 0, vlan_offset = 0; |
677 | 78aeb23e | Stefan Hajnoczi | uint8_t min_buf[MIN_BUF_SIZE]; |
678 | b19487e2 | Michael S. Tsirkin | size_t desc_offset; |
679 | b19487e2 | Michael S. Tsirkin | size_t desc_size; |
680 | b19487e2 | Michael S. Tsirkin | size_t total_size; |
681 | 7c23b892 | balrog | |
682 | 7c23b892 | balrog | if (!(s->mac_reg[RCTL] & E1000_RCTL_EN))
|
683 | 4f1c942b | Mark McLoughlin | return -1; |
684 | 7c23b892 | balrog | |
685 | 78aeb23e | Stefan Hajnoczi | /* Pad to minimum Ethernet frame length */
|
686 | 78aeb23e | Stefan Hajnoczi | if (size < sizeof(min_buf)) { |
687 | 78aeb23e | Stefan Hajnoczi | memcpy(min_buf, buf, size); |
688 | 78aeb23e | Stefan Hajnoczi | memset(&min_buf[size], 0, sizeof(min_buf) - size); |
689 | 78aeb23e | Stefan Hajnoczi | buf = min_buf; |
690 | 78aeb23e | Stefan Hajnoczi | size = sizeof(min_buf);
|
691 | 78aeb23e | Stefan Hajnoczi | } |
692 | 78aeb23e | Stefan Hajnoczi | |
693 | 7c23b892 | balrog | if (!receive_filter(s, buf, size))
|
694 | 4f1c942b | Mark McLoughlin | return size;
|
695 | 7c23b892 | balrog | |
696 | 8f2e8d1f | aliguori | if (vlan_enabled(s) && is_vlan_packet(s, buf)) {
|
697 | 8f2e8d1f | aliguori | vlan_special = cpu_to_le16(be16_to_cpup((uint16_t *)(buf + 14)));
|
698 | 98835fe3 | Thomas Monjalon | memmove((uint8_t *)buf + 4, buf, 12); |
699 | 8f2e8d1f | aliguori | vlan_status = E1000_RXD_STAT_VP; |
700 | 8f2e8d1f | aliguori | vlan_offset = 4;
|
701 | 8f2e8d1f | aliguori | size -= 4;
|
702 | 8f2e8d1f | aliguori | } |
703 | 8f2e8d1f | aliguori | |
704 | 7c23b892 | balrog | rdh_start = s->mac_reg[RDH]; |
705 | b19487e2 | Michael S. Tsirkin | desc_offset = 0;
|
706 | b19487e2 | Michael S. Tsirkin | total_size = size + fcs_len(s); |
707 | 322fd48a | Michael S. Tsirkin | if (!e1000_has_rxbufs(s, total_size)) {
|
708 | 322fd48a | Michael S. Tsirkin | set_ics(s, 0, E1000_ICS_RXO);
|
709 | 322fd48a | Michael S. Tsirkin | return -1; |
710 | 322fd48a | Michael S. Tsirkin | } |
711 | 7c23b892 | balrog | do {
|
712 | b19487e2 | Michael S. Tsirkin | desc_size = total_size - desc_offset; |
713 | b19487e2 | Michael S. Tsirkin | if (desc_size > s->rxbuf_size) {
|
714 | b19487e2 | Michael S. Tsirkin | desc_size = s->rxbuf_size; |
715 | b19487e2 | Michael S. Tsirkin | } |
716 | d17161f6 | Kevin Wolf | base = rx_desc_base(s) + sizeof(desc) * s->mac_reg[RDH];
|
717 | 00c3a05b | David Gibson | pci_dma_read(&s->dev, base, &desc, sizeof(desc));
|
718 | 8f2e8d1f | aliguori | desc.special = vlan_special; |
719 | 8f2e8d1f | aliguori | desc.status |= (vlan_status | E1000_RXD_STAT_DD); |
720 | 7c23b892 | balrog | if (desc.buffer_addr) {
|
721 | b19487e2 | Michael S. Tsirkin | if (desc_offset < size) {
|
722 | b19487e2 | Michael S. Tsirkin | size_t copy_size = size - desc_offset; |
723 | b19487e2 | Michael S. Tsirkin | if (copy_size > s->rxbuf_size) {
|
724 | b19487e2 | Michael S. Tsirkin | copy_size = s->rxbuf_size; |
725 | b19487e2 | Michael S. Tsirkin | } |
726 | 62ecbd35 | Eduard - Gabriel Munteanu | pci_dma_write(&s->dev, le64_to_cpu(desc.buffer_addr), |
727 | 00c3a05b | David Gibson | buf + desc_offset + vlan_offset, copy_size); |
728 | b19487e2 | Michael S. Tsirkin | } |
729 | b19487e2 | Michael S. Tsirkin | desc_offset += desc_size; |
730 | ee912ccf | Michael S. Tsirkin | desc.length = cpu_to_le16(desc_size); |
731 | b19487e2 | Michael S. Tsirkin | if (desc_offset >= total_size) {
|
732 | b19487e2 | Michael S. Tsirkin | desc.status |= E1000_RXD_STAT_EOP | E1000_RXD_STAT_IXSM; |
733 | b19487e2 | Michael S. Tsirkin | } else {
|
734 | ee912ccf | Michael S. Tsirkin | /* Guest zeroing out status is not a hardware requirement.
|
735 | ee912ccf | Michael S. Tsirkin | Clear EOP in case guest didn't do it. */
|
736 | ee912ccf | Michael S. Tsirkin | desc.status &= ~E1000_RXD_STAT_EOP; |
737 | b19487e2 | Michael S. Tsirkin | } |
738 | 43ad7e3e | Jes Sorensen | } else { // as per intel docs; skip descriptors with null buf addr |
739 | 7c23b892 | balrog | DBGOUT(RX, "Null RX descriptor!!\n");
|
740 | 43ad7e3e | Jes Sorensen | } |
741 | 00c3a05b | David Gibson | pci_dma_write(&s->dev, base, &desc, sizeof(desc));
|
742 | 7c23b892 | balrog | |
743 | 7c23b892 | balrog | if (++s->mac_reg[RDH] * sizeof(desc) >= s->mac_reg[RDLEN]) |
744 | 7c23b892 | balrog | s->mac_reg[RDH] = 0;
|
745 | 7c23b892 | balrog | s->check_rxov = 1;
|
746 | 7c23b892 | balrog | /* see comment in start_xmit; same here */
|
747 | 7c23b892 | balrog | if (s->mac_reg[RDH] == rdh_start) {
|
748 | 7c23b892 | balrog | DBGOUT(RXERR, "RDH wraparound @%x, RDT %x, RDLEN %x\n",
|
749 | 7c23b892 | balrog | rdh_start, s->mac_reg[RDT], s->mac_reg[RDLEN]); |
750 | 7c23b892 | balrog | set_ics(s, 0, E1000_ICS_RXO);
|
751 | 4f1c942b | Mark McLoughlin | return -1; |
752 | 7c23b892 | balrog | } |
753 | b19487e2 | Michael S. Tsirkin | } while (desc_offset < total_size);
|
754 | 7c23b892 | balrog | |
755 | 7c23b892 | balrog | s->mac_reg[GPRC]++; |
756 | 7c23b892 | balrog | s->mac_reg[TPR]++; |
757 | a05e8a6e | Michael S. Tsirkin | /* TOR - Total Octets Received:
|
758 | a05e8a6e | Michael S. Tsirkin | * This register includes bytes received in a packet from the <Destination
|
759 | a05e8a6e | Michael S. Tsirkin | * Address> field through the <CRC> field, inclusively.
|
760 | a05e8a6e | Michael S. Tsirkin | */
|
761 | a05e8a6e | Michael S. Tsirkin | n = s->mac_reg[TORL] + size + /* Always include FCS length. */ 4; |
762 | a05e8a6e | Michael S. Tsirkin | if (n < s->mac_reg[TORL])
|
763 | 7c23b892 | balrog | s->mac_reg[TORH]++; |
764 | a05e8a6e | Michael S. Tsirkin | s->mac_reg[TORL] = n; |
765 | 7c23b892 | balrog | |
766 | 7c23b892 | balrog | n = E1000_ICS_RXT0; |
767 | 7c23b892 | balrog | if ((rdt = s->mac_reg[RDT]) < s->mac_reg[RDH])
|
768 | 7c23b892 | balrog | rdt += s->mac_reg[RDLEN] / sizeof(desc);
|
769 | bf16cc8f | aliguori | if (((rdt - s->mac_reg[RDH]) * sizeof(desc)) <= s->mac_reg[RDLEN] >> |
770 | bf16cc8f | aliguori | s->rxbuf_min_shift) |
771 | 7c23b892 | balrog | n |= E1000_ICS_RXDMT0; |
772 | 7c23b892 | balrog | |
773 | 7c23b892 | balrog | set_ics(s, 0, n);
|
774 | 4f1c942b | Mark McLoughlin | |
775 | 4f1c942b | Mark McLoughlin | return size;
|
776 | 7c23b892 | balrog | } |
777 | 7c23b892 | balrog | |
778 | 7c23b892 | balrog | static uint32_t
|
779 | 7c23b892 | balrog | mac_readreg(E1000State *s, int index)
|
780 | 7c23b892 | balrog | { |
781 | 7c23b892 | balrog | return s->mac_reg[index];
|
782 | 7c23b892 | balrog | } |
783 | 7c23b892 | balrog | |
784 | 7c23b892 | balrog | static uint32_t
|
785 | 7c23b892 | balrog | mac_icr_read(E1000State *s, int index)
|
786 | 7c23b892 | balrog | { |
787 | 7c23b892 | balrog | uint32_t ret = s->mac_reg[ICR]; |
788 | 7c23b892 | balrog | |
789 | 7c23b892 | balrog | DBGOUT(INTERRUPT, "ICR read: %x\n", ret);
|
790 | 7c23b892 | balrog | set_interrupt_cause(s, 0, 0); |
791 | 7c23b892 | balrog | return ret;
|
792 | 7c23b892 | balrog | } |
793 | 7c23b892 | balrog | |
794 | 7c23b892 | balrog | static uint32_t
|
795 | 7c23b892 | balrog | mac_read_clr4(E1000State *s, int index)
|
796 | 7c23b892 | balrog | { |
797 | 7c23b892 | balrog | uint32_t ret = s->mac_reg[index]; |
798 | 7c23b892 | balrog | |
799 | 7c23b892 | balrog | s->mac_reg[index] = 0;
|
800 | 7c23b892 | balrog | return ret;
|
801 | 7c23b892 | balrog | } |
802 | 7c23b892 | balrog | |
803 | 7c23b892 | balrog | static uint32_t
|
804 | 7c23b892 | balrog | mac_read_clr8(E1000State *s, int index)
|
805 | 7c23b892 | balrog | { |
806 | 7c23b892 | balrog | uint32_t ret = s->mac_reg[index]; |
807 | 7c23b892 | balrog | |
808 | 7c23b892 | balrog | s->mac_reg[index] = 0;
|
809 | 7c23b892 | balrog | s->mac_reg[index-1] = 0; |
810 | 7c23b892 | balrog | return ret;
|
811 | 7c23b892 | balrog | } |
812 | 7c23b892 | balrog | |
813 | 7c23b892 | balrog | static void |
814 | 7c23b892 | balrog | mac_writereg(E1000State *s, int index, uint32_t val)
|
815 | 7c23b892 | balrog | { |
816 | 7c23b892 | balrog | s->mac_reg[index] = val; |
817 | 7c23b892 | balrog | } |
818 | 7c23b892 | balrog | |
819 | 7c23b892 | balrog | static void |
820 | 7c23b892 | balrog | set_rdt(E1000State *s, int index, uint32_t val)
|
821 | 7c23b892 | balrog | { |
822 | 7c23b892 | balrog | s->check_rxov = 0;
|
823 | 7c23b892 | balrog | s->mac_reg[index] = val & 0xffff;
|
824 | 7c23b892 | balrog | } |
825 | 7c23b892 | balrog | |
826 | 7c23b892 | balrog | static void |
827 | 7c23b892 | balrog | set_16bit(E1000State *s, int index, uint32_t val)
|
828 | 7c23b892 | balrog | { |
829 | 7c23b892 | balrog | s->mac_reg[index] = val & 0xffff;
|
830 | 7c23b892 | balrog | } |
831 | 7c23b892 | balrog | |
832 | 7c23b892 | balrog | static void |
833 | 7c23b892 | balrog | set_dlen(E1000State *s, int index, uint32_t val)
|
834 | 7c23b892 | balrog | { |
835 | 7c23b892 | balrog | s->mac_reg[index] = val & 0xfff80;
|
836 | 7c23b892 | balrog | } |
837 | 7c23b892 | balrog | |
838 | 7c23b892 | balrog | static void |
839 | 7c23b892 | balrog | set_tctl(E1000State *s, int index, uint32_t val)
|
840 | 7c23b892 | balrog | { |
841 | 7c23b892 | balrog | s->mac_reg[index] = val; |
842 | 7c23b892 | balrog | s->mac_reg[TDT] &= 0xffff;
|
843 | 7c23b892 | balrog | start_xmit(s); |
844 | 7c23b892 | balrog | } |
845 | 7c23b892 | balrog | |
846 | 7c23b892 | balrog | static void |
847 | 7c23b892 | balrog | set_icr(E1000State *s, int index, uint32_t val)
|
848 | 7c23b892 | balrog | { |
849 | 7c23b892 | balrog | DBGOUT(INTERRUPT, "set_icr %x\n", val);
|
850 | 7c23b892 | balrog | set_interrupt_cause(s, 0, s->mac_reg[ICR] & ~val);
|
851 | 7c23b892 | balrog | } |
852 | 7c23b892 | balrog | |
853 | 7c23b892 | balrog | static void |
854 | 7c23b892 | balrog | set_imc(E1000State *s, int index, uint32_t val)
|
855 | 7c23b892 | balrog | { |
856 | 7c23b892 | balrog | s->mac_reg[IMS] &= ~val; |
857 | 7c23b892 | balrog | set_ics(s, 0, 0); |
858 | 7c23b892 | balrog | } |
859 | 7c23b892 | balrog | |
860 | 7c23b892 | balrog | static void |
861 | 7c23b892 | balrog | set_ims(E1000State *s, int index, uint32_t val)
|
862 | 7c23b892 | balrog | { |
863 | 7c23b892 | balrog | s->mac_reg[IMS] |= val; |
864 | 7c23b892 | balrog | set_ics(s, 0, 0); |
865 | 7c23b892 | balrog | } |
866 | 7c23b892 | balrog | |
867 | 7c23b892 | balrog | #define getreg(x) [x] = mac_readreg
|
868 | 7c23b892 | balrog | static uint32_t (*macreg_readops[])(E1000State *, int) = { |
869 | 7c23b892 | balrog | getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL), |
870 | 7c23b892 | balrog | getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL), |
871 | 7c23b892 | balrog | getreg(MANC), getreg(MDIC), getreg(SWSM), getreg(STATUS), |
872 | 7c23b892 | balrog | getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL), |
873 | b1332393 | Bill Paul | getreg(RDH), getreg(RDT), getreg(VET), getreg(ICS), |
874 | a00b2335 | Kay Ackermann | getreg(TDBAL), getreg(TDBAH), getreg(RDBAH), getreg(RDBAL), |
875 | a00b2335 | Kay Ackermann | getreg(TDLEN), getreg(RDLEN), |
876 | 7c23b892 | balrog | |
877 | 7c23b892 | balrog | [TOTH] = mac_read_clr8, [TORH] = mac_read_clr8, [GPRC] = mac_read_clr4, |
878 | 7c23b892 | balrog | [GPTC] = mac_read_clr4, [TPR] = mac_read_clr4, [TPT] = mac_read_clr4, |
879 | 7c23b892 | balrog | [ICR] = mac_icr_read, [EECD] = get_eecd, [EERD] = flash_eerd_read, |
880 | 7c23b892 | balrog | [CRCERRS ... MPC] = &mac_readreg, |
881 | 7c23b892 | balrog | [RA ... RA+31] = &mac_readreg,
|
882 | 7c23b892 | balrog | [MTA ... MTA+127] = &mac_readreg,
|
883 | 8f2e8d1f | aliguori | [VFTA ... VFTA+127] = &mac_readreg,
|
884 | 7c23b892 | balrog | }; |
885 | b1503cda | malc | enum { NREADOPS = ARRAY_SIZE(macreg_readops) };
|
886 | 7c23b892 | balrog | |
887 | 7c23b892 | balrog | #define putreg(x) [x] = mac_writereg
|
888 | 7c23b892 | balrog | static void (*macreg_writeops[])(E1000State *, int, uint32_t) = { |
889 | 7c23b892 | balrog | putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC), |
890 | 7c23b892 | balrog | putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH), |
891 | cab3c825 | Kevin Wolf | putreg(RDBAL), putreg(LEDCTL), putreg(VET), |
892 | 7c23b892 | balrog | [TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl, |
893 | 7c23b892 | balrog | [TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics, |
894 | 7c23b892 | balrog | [TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt, |
895 | 7c23b892 | balrog | [IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr, |
896 | cab3c825 | Kevin Wolf | [EECD] = set_eecd, [RCTL] = set_rx_control, [CTRL] = set_ctrl, |
897 | 7c23b892 | balrog | [RA ... RA+31] = &mac_writereg,
|
898 | 7c23b892 | balrog | [MTA ... MTA+127] = &mac_writereg,
|
899 | 8f2e8d1f | aliguori | [VFTA ... VFTA+127] = &mac_writereg,
|
900 | 7c23b892 | balrog | }; |
901 | b1503cda | malc | enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
|
902 | 7c23b892 | balrog | |
903 | 7c23b892 | balrog | static void |
904 | ad00a9b9 | Avi Kivity | e1000_mmio_write(void *opaque, target_phys_addr_t addr, uint64_t val,
|
905 | ad00a9b9 | Avi Kivity | unsigned size)
|
906 | 7c23b892 | balrog | { |
907 | 7c23b892 | balrog | E1000State *s = opaque; |
908 | 8da3ff18 | pbrook | unsigned int index = (addr & 0x1ffff) >> 2; |
909 | 7c23b892 | balrog | |
910 | 43ad7e3e | Jes Sorensen | if (index < NWRITEOPS && macreg_writeops[index]) {
|
911 | 6b59fc74 | aurel32 | macreg_writeops[index](s, index, val); |
912 | 43ad7e3e | Jes Sorensen | } else if (index < NREADOPS && macreg_readops[index]) { |
913 | ad00a9b9 | Avi Kivity | DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04"PRIx64"\n", index<<2, val); |
914 | 43ad7e3e | Jes Sorensen | } else {
|
915 | ad00a9b9 | Avi Kivity | DBGOUT(UNKNOWN, "MMIO unknown write addr=0x%08x,val=0x%08"PRIx64"\n", |
916 | 7c23b892 | balrog | index<<2, val);
|
917 | 43ad7e3e | Jes Sorensen | } |
918 | 7c23b892 | balrog | } |
919 | 7c23b892 | balrog | |
920 | ad00a9b9 | Avi Kivity | static uint64_t
|
921 | ad00a9b9 | Avi Kivity | e1000_mmio_read(void *opaque, target_phys_addr_t addr, unsigned size) |
922 | 7c23b892 | balrog | { |
923 | 7c23b892 | balrog | E1000State *s = opaque; |
924 | 8da3ff18 | pbrook | unsigned int index = (addr & 0x1ffff) >> 2; |
925 | 7c23b892 | balrog | |
926 | 7c23b892 | balrog | if (index < NREADOPS && macreg_readops[index])
|
927 | 6b59fc74 | aurel32 | { |
928 | 32600a30 | Alexander Graf | return macreg_readops[index](s, index);
|
929 | 6b59fc74 | aurel32 | } |
930 | 7c23b892 | balrog | DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2); |
931 | 7c23b892 | balrog | return 0; |
932 | 7c23b892 | balrog | } |
933 | 7c23b892 | balrog | |
934 | ad00a9b9 | Avi Kivity | static const MemoryRegionOps e1000_mmio_ops = { |
935 | ad00a9b9 | Avi Kivity | .read = e1000_mmio_read, |
936 | ad00a9b9 | Avi Kivity | .write = e1000_mmio_write, |
937 | ad00a9b9 | Avi Kivity | .endianness = DEVICE_LITTLE_ENDIAN, |
938 | ad00a9b9 | Avi Kivity | .impl = { |
939 | ad00a9b9 | Avi Kivity | .min_access_size = 4,
|
940 | ad00a9b9 | Avi Kivity | .max_access_size = 4,
|
941 | ad00a9b9 | Avi Kivity | }, |
942 | ad00a9b9 | Avi Kivity | }; |
943 | ad00a9b9 | Avi Kivity | |
944 | ad00a9b9 | Avi Kivity | static uint64_t e1000_io_read(void *opaque, target_phys_addr_t addr, |
945 | ad00a9b9 | Avi Kivity | unsigned size)
|
946 | 7c23b892 | balrog | { |
947 | ad00a9b9 | Avi Kivity | E1000State *s = opaque; |
948 | ad00a9b9 | Avi Kivity | |
949 | ad00a9b9 | Avi Kivity | (void)s;
|
950 | ad00a9b9 | Avi Kivity | return 0; |
951 | 7c23b892 | balrog | } |
952 | 7c23b892 | balrog | |
953 | ad00a9b9 | Avi Kivity | static void e1000_io_write(void *opaque, target_phys_addr_t addr, |
954 | ad00a9b9 | Avi Kivity | uint64_t val, unsigned size)
|
955 | 7c23b892 | balrog | { |
956 | ad00a9b9 | Avi Kivity | E1000State *s = opaque; |
957 | ad00a9b9 | Avi Kivity | |
958 | ad00a9b9 | Avi Kivity | (void)s;
|
959 | 7c23b892 | balrog | } |
960 | 7c23b892 | balrog | |
961 | ad00a9b9 | Avi Kivity | static const MemoryRegionOps e1000_io_ops = { |
962 | ad00a9b9 | Avi Kivity | .read = e1000_io_read, |
963 | ad00a9b9 | Avi Kivity | .write = e1000_io_write, |
964 | ad00a9b9 | Avi Kivity | .endianness = DEVICE_LITTLE_ENDIAN, |
965 | ad00a9b9 | Avi Kivity | }; |
966 | ad00a9b9 | Avi Kivity | |
967 | e482dc3e | Juan Quintela | static bool is_version_1(void *opaque, int version_id) |
968 | 7c23b892 | balrog | { |
969 | e482dc3e | Juan Quintela | return version_id == 1; |
970 | 7c23b892 | balrog | } |
971 | 7c23b892 | balrog | |
972 | e482dc3e | Juan Quintela | static const VMStateDescription vmstate_e1000 = { |
973 | e482dc3e | Juan Quintela | .name = "e1000",
|
974 | e482dc3e | Juan Quintela | .version_id = 2,
|
975 | e482dc3e | Juan Quintela | .minimum_version_id = 1,
|
976 | e482dc3e | Juan Quintela | .minimum_version_id_old = 1,
|
977 | e482dc3e | Juan Quintela | .fields = (VMStateField []) { |
978 | e482dc3e | Juan Quintela | VMSTATE_PCI_DEVICE(dev, E1000State), |
979 | e482dc3e | Juan Quintela | VMSTATE_UNUSED_TEST(is_version_1, 4), /* was instance id */ |
980 | e482dc3e | Juan Quintela | VMSTATE_UNUSED(4), /* Was mmio_base. */ |
981 | e482dc3e | Juan Quintela | VMSTATE_UINT32(rxbuf_size, E1000State), |
982 | e482dc3e | Juan Quintela | VMSTATE_UINT32(rxbuf_min_shift, E1000State), |
983 | e482dc3e | Juan Quintela | VMSTATE_UINT32(eecd_state.val_in, E1000State), |
984 | e482dc3e | Juan Quintela | VMSTATE_UINT16(eecd_state.bitnum_in, E1000State), |
985 | e482dc3e | Juan Quintela | VMSTATE_UINT16(eecd_state.bitnum_out, E1000State), |
986 | e482dc3e | Juan Quintela | VMSTATE_UINT16(eecd_state.reading, E1000State), |
987 | e482dc3e | Juan Quintela | VMSTATE_UINT32(eecd_state.old_eecd, E1000State), |
988 | e482dc3e | Juan Quintela | VMSTATE_UINT8(tx.ipcss, E1000State), |
989 | e482dc3e | Juan Quintela | VMSTATE_UINT8(tx.ipcso, E1000State), |
990 | e482dc3e | Juan Quintela | VMSTATE_UINT16(tx.ipcse, E1000State), |
991 | e482dc3e | Juan Quintela | VMSTATE_UINT8(tx.tucss, E1000State), |
992 | e482dc3e | Juan Quintela | VMSTATE_UINT8(tx.tucso, E1000State), |
993 | e482dc3e | Juan Quintela | VMSTATE_UINT16(tx.tucse, E1000State), |
994 | e482dc3e | Juan Quintela | VMSTATE_UINT32(tx.paylen, E1000State), |
995 | e482dc3e | Juan Quintela | VMSTATE_UINT8(tx.hdr_len, E1000State), |
996 | e482dc3e | Juan Quintela | VMSTATE_UINT16(tx.mss, E1000State), |
997 | e482dc3e | Juan Quintela | VMSTATE_UINT16(tx.size, E1000State), |
998 | e482dc3e | Juan Quintela | VMSTATE_UINT16(tx.tso_frames, E1000State), |
999 | e482dc3e | Juan Quintela | VMSTATE_UINT8(tx.sum_needed, E1000State), |
1000 | e482dc3e | Juan Quintela | VMSTATE_INT8(tx.ip, E1000State), |
1001 | e482dc3e | Juan Quintela | VMSTATE_INT8(tx.tcp, E1000State), |
1002 | e482dc3e | Juan Quintela | VMSTATE_BUFFER(tx.header, E1000State), |
1003 | e482dc3e | Juan Quintela | VMSTATE_BUFFER(tx.data, E1000State), |
1004 | e482dc3e | Juan Quintela | VMSTATE_UINT16_ARRAY(eeprom_data, E1000State, 64),
|
1005 | e482dc3e | Juan Quintela | VMSTATE_UINT16_ARRAY(phy_reg, E1000State, 0x20),
|
1006 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[CTRL], E1000State), |
1007 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[EECD], E1000State), |
1008 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[EERD], E1000State), |
1009 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[GPRC], E1000State), |
1010 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[GPTC], E1000State), |
1011 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[ICR], E1000State), |
1012 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[ICS], E1000State), |
1013 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[IMC], E1000State), |
1014 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[IMS], E1000State), |
1015 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[LEDCTL], E1000State), |
1016 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[MANC], E1000State), |
1017 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[MDIC], E1000State), |
1018 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[MPC], E1000State), |
1019 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[PBA], E1000State), |
1020 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[RCTL], E1000State), |
1021 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[RDBAH], E1000State), |
1022 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[RDBAL], E1000State), |
1023 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[RDH], E1000State), |
1024 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[RDLEN], E1000State), |
1025 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[RDT], E1000State), |
1026 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[STATUS], E1000State), |
1027 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[SWSM], E1000State), |
1028 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[TCTL], E1000State), |
1029 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[TDBAH], E1000State), |
1030 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[TDBAL], E1000State), |
1031 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[TDH], E1000State), |
1032 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[TDLEN], E1000State), |
1033 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[TDT], E1000State), |
1034 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[TORH], E1000State), |
1035 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[TORL], E1000State), |
1036 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[TOTH], E1000State), |
1037 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[TOTL], E1000State), |
1038 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[TPR], E1000State), |
1039 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[TPT], E1000State), |
1040 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[TXDCTL], E1000State), |
1041 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[WUFC], E1000State), |
1042 | e482dc3e | Juan Quintela | VMSTATE_UINT32(mac_reg[VET], E1000State), |
1043 | e482dc3e | Juan Quintela | VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, RA, 32),
|
1044 | e482dc3e | Juan Quintela | VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, MTA, 128),
|
1045 | e482dc3e | Juan Quintela | VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, VFTA, 128),
|
1046 | e482dc3e | Juan Quintela | VMSTATE_END_OF_LIST() |
1047 | e482dc3e | Juan Quintela | } |
1048 | e482dc3e | Juan Quintela | }; |
1049 | 7c23b892 | balrog | |
1050 | 88b4e9db | blueswir1 | static const uint16_t e1000_eeprom_template[64] = { |
1051 | 7c23b892 | balrog | 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0x0000, 0x0000, 0x0000, |
1052 | 7c23b892 | balrog | 0x3000, 0x1000, 0x6403, E1000_DEVID, 0x8086, E1000_DEVID, 0x8086, 0x3040, |
1053 | 7c23b892 | balrog | 0x0008, 0x2000, 0x7e14, 0x0048, 0x1000, 0x00d8, 0x0000, 0x2700, |
1054 | 7c23b892 | balrog | 0x6cc9, 0x3150, 0x0722, 0x040b, 0x0984, 0x0000, 0xc000, 0x0706, |
1055 | 7c23b892 | balrog | 0x1008, 0x0000, 0x0f04, 0x7fff, 0x4d01, 0xffff, 0xffff, 0xffff, |
1056 | 7c23b892 | balrog | 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, |
1057 | 7c23b892 | balrog | 0x0100, 0x4000, 0x121c, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, |
1058 | 7c23b892 | balrog | 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0000, |
1059 | 7c23b892 | balrog | }; |
1060 | 7c23b892 | balrog | |
1061 | 88b4e9db | blueswir1 | static const uint16_t phy_reg_init[] = { |
1062 | 7c23b892 | balrog | [PHY_CTRL] = 0x1140, [PHY_STATUS] = 0x796d, // link initially up |
1063 | 7c23b892 | balrog | [PHY_ID1] = 0x141, [PHY_ID2] = PHY_ID2_INIT,
|
1064 | 7c23b892 | balrog | [PHY_1000T_CTRL] = 0x0e00, [M88E1000_PHY_SPEC_CTRL] = 0x360, |
1065 | 7c23b892 | balrog | [M88E1000_EXT_PHY_SPEC_CTRL] = 0x0d60, [PHY_AUTONEG_ADV] = 0xde1, |
1066 | 7c23b892 | balrog | [PHY_LP_ABILITY] = 0x1e0, [PHY_1000T_STATUS] = 0x3c00, |
1067 | 700f6e2c | aurel32 | [M88E1000_PHY_SPEC_STATUS] = 0xac00,
|
1068 | 7c23b892 | balrog | }; |
1069 | 7c23b892 | balrog | |
1070 | 88b4e9db | blueswir1 | static const uint32_t mac_reg_init[] = { |
1071 | 7c23b892 | balrog | [PBA] = 0x00100030,
|
1072 | 7c23b892 | balrog | [LEDCTL] = 0x602,
|
1073 | 7c23b892 | balrog | [CTRL] = E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 | |
1074 | 7c23b892 | balrog | E1000_CTRL_SPD_1000 | E1000_CTRL_SLU, |
1075 | 7c23b892 | balrog | [STATUS] = 0x80000000 | E1000_STATUS_GIO_MASTER_ENABLE |
|
1076 | 7c23b892 | balrog | E1000_STATUS_ASDV | E1000_STATUS_MTXCKOK | |
1077 | 7c23b892 | balrog | E1000_STATUS_SPEED_1000 | E1000_STATUS_FD | |
1078 | 7c23b892 | balrog | E1000_STATUS_LU, |
1079 | 7c23b892 | balrog | [MANC] = E1000_MANC_EN_MNG2HOST | E1000_MANC_RCV_TCO_EN | |
1080 | 7c23b892 | balrog | E1000_MANC_ARP_EN | E1000_MANC_0298_EN | |
1081 | 7c23b892 | balrog | E1000_MANC_RMCP_EN, |
1082 | 7c23b892 | balrog | }; |
1083 | 7c23b892 | balrog | |
1084 | 7c23b892 | balrog | /* PCI interface */
|
1085 | 7c23b892 | balrog | |
1086 | 7c23b892 | balrog | static void |
1087 | ad00a9b9 | Avi Kivity | e1000_mmio_setup(E1000State *d) |
1088 | 7c23b892 | balrog | { |
1089 | f65ed4c1 | aliguori | int i;
|
1090 | f65ed4c1 | aliguori | const uint32_t excluded_regs[] = {
|
1091 | f65ed4c1 | aliguori | E1000_MDIC, E1000_ICR, E1000_ICS, E1000_IMS, |
1092 | f65ed4c1 | aliguori | E1000_IMC, E1000_TCTL, E1000_TDT, PNPMMIO_SIZE |
1093 | f65ed4c1 | aliguori | }; |
1094 | f65ed4c1 | aliguori | |
1095 | ad00a9b9 | Avi Kivity | memory_region_init_io(&d->mmio, &e1000_mmio_ops, d, "e1000-mmio",
|
1096 | ad00a9b9 | Avi Kivity | PNPMMIO_SIZE); |
1097 | ad00a9b9 | Avi Kivity | memory_region_add_coalescing(&d->mmio, 0, excluded_regs[0]); |
1098 | f65ed4c1 | aliguori | for (i = 0; excluded_regs[i] != PNPMMIO_SIZE; i++) |
1099 | ad00a9b9 | Avi Kivity | memory_region_add_coalescing(&d->mmio, excluded_regs[i] + 4,
|
1100 | ad00a9b9 | Avi Kivity | excluded_regs[i+1] - excluded_regs[i] - 4); |
1101 | ad00a9b9 | Avi Kivity | memory_region_init_io(&d->io, &e1000_io_ops, d, "e1000-io", IOPORT_SIZE);
|
1102 | 7c23b892 | balrog | } |
1103 | 7c23b892 | balrog | |
1104 | b946a153 | aliguori | static void |
1105 | a03e2aec | Mark McLoughlin | e1000_cleanup(VLANClientState *nc) |
1106 | b946a153 | aliguori | { |
1107 | a03e2aec | Mark McLoughlin | E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
1108 | b946a153 | aliguori | |
1109 | a03e2aec | Mark McLoughlin | s->nic = NULL;
|
1110 | b946a153 | aliguori | } |
1111 | b946a153 | aliguori | |
1112 | 4b09be85 | aliguori | static int |
1113 | 4b09be85 | aliguori | pci_e1000_uninit(PCIDevice *dev) |
1114 | 4b09be85 | aliguori | { |
1115 | 7d9e52bd | Juan Quintela | E1000State *d = DO_UPCAST(E1000State, dev, dev); |
1116 | 4b09be85 | aliguori | |
1117 | ad00a9b9 | Avi Kivity | memory_region_destroy(&d->mmio); |
1118 | ad00a9b9 | Avi Kivity | memory_region_destroy(&d->io); |
1119 | a03e2aec | Mark McLoughlin | qemu_del_vlan_client(&d->nic->nc); |
1120 | 4b09be85 | aliguori | return 0; |
1121 | 4b09be85 | aliguori | } |
1122 | 4b09be85 | aliguori | |
1123 | 32c86e95 | Blue Swirl | static void e1000_reset(void *opaque) |
1124 | 32c86e95 | Blue Swirl | { |
1125 | 32c86e95 | Blue Swirl | E1000State *d = opaque; |
1126 | 32c86e95 | Blue Swirl | |
1127 | 32c86e95 | Blue Swirl | memset(d->phy_reg, 0, sizeof d->phy_reg); |
1128 | 32c86e95 | Blue Swirl | memmove(d->phy_reg, phy_reg_init, sizeof phy_reg_init);
|
1129 | 32c86e95 | Blue Swirl | memset(d->mac_reg, 0, sizeof d->mac_reg); |
1130 | 32c86e95 | Blue Swirl | memmove(d->mac_reg, mac_reg_init, sizeof mac_reg_init);
|
1131 | 32c86e95 | Blue Swirl | d->rxbuf_min_shift = 1;
|
1132 | 32c86e95 | Blue Swirl | memset(&d->tx, 0, sizeof d->tx); |
1133 | 32c86e95 | Blue Swirl | } |
1134 | 32c86e95 | Blue Swirl | |
1135 | a03e2aec | Mark McLoughlin | static NetClientInfo net_e1000_info = {
|
1136 | a03e2aec | Mark McLoughlin | .type = NET_CLIENT_TYPE_NIC, |
1137 | a03e2aec | Mark McLoughlin | .size = sizeof(NICState),
|
1138 | a03e2aec | Mark McLoughlin | .can_receive = e1000_can_receive, |
1139 | a03e2aec | Mark McLoughlin | .receive = e1000_receive, |
1140 | a03e2aec | Mark McLoughlin | .cleanup = e1000_cleanup, |
1141 | a03e2aec | Mark McLoughlin | .link_status_changed = e1000_set_link_status, |
1142 | a03e2aec | Mark McLoughlin | }; |
1143 | a03e2aec | Mark McLoughlin | |
1144 | 81a322d4 | Gerd Hoffmann | static int pci_e1000_init(PCIDevice *pci_dev) |
1145 | 7c23b892 | balrog | { |
1146 | 7d9e52bd | Juan Quintela | E1000State *d = DO_UPCAST(E1000State, dev, pci_dev); |
1147 | 7c23b892 | balrog | uint8_t *pci_conf; |
1148 | 7c23b892 | balrog | uint16_t checksum = 0;
|
1149 | 7c23b892 | balrog | int i;
|
1150 | fbdaa002 | Gerd Hoffmann | uint8_t *macaddr; |
1151 | aff427a1 | Chris Wright | |
1152 | 7c23b892 | balrog | pci_conf = d->dev.config; |
1153 | 7c23b892 | balrog | |
1154 | a9cbacb0 | Michael S. Tsirkin | /* TODO: RST# value should be 0, PCI spec 6.2.4 */
|
1155 | a9cbacb0 | Michael S. Tsirkin | pci_conf[PCI_CACHE_LINE_SIZE] = 0x10;
|
1156 | 7c23b892 | balrog | |
1157 | 817e0b6f | Michael S. Tsirkin | pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */ |
1158 | 7c23b892 | balrog | |
1159 | ad00a9b9 | Avi Kivity | e1000_mmio_setup(d); |
1160 | 7c23b892 | balrog | |
1161 | e824b2cc | Avi Kivity | pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
|
1162 | 7c23b892 | balrog | |
1163 | e824b2cc | Avi Kivity | pci_register_bar(&d->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->io);
|
1164 | 7c23b892 | balrog | |
1165 | 7c23b892 | balrog | memmove(d->eeprom_data, e1000_eeprom_template, |
1166 | 7c23b892 | balrog | sizeof e1000_eeprom_template);
|
1167 | fbdaa002 | Gerd Hoffmann | qemu_macaddr_default_if_unset(&d->conf.macaddr); |
1168 | fbdaa002 | Gerd Hoffmann | macaddr = d->conf.macaddr.a; |
1169 | 7c23b892 | balrog | for (i = 0; i < 3; i++) |
1170 | 9d07d757 | Paul Brook | d->eeprom_data[i] = (macaddr[2*i+1]<<8) | macaddr[2*i]; |
1171 | 7c23b892 | balrog | for (i = 0; i < EEPROM_CHECKSUM_REG; i++) |
1172 | 7c23b892 | balrog | checksum += d->eeprom_data[i]; |
1173 | 7c23b892 | balrog | checksum = (uint16_t) EEPROM_SUM - checksum; |
1174 | 7c23b892 | balrog | d->eeprom_data[EEPROM_CHECKSUM_REG] = checksum; |
1175 | 7c23b892 | balrog | |
1176 | a03e2aec | Mark McLoughlin | d->nic = qemu_new_nic(&net_e1000_info, &d->conf, |
1177 | a03e2aec | Mark McLoughlin | d->dev.qdev.info->name, d->dev.qdev.id, d); |
1178 | 7c23b892 | balrog | |
1179 | a03e2aec | Mark McLoughlin | qemu_format_nic_info_str(&d->nic->nc, macaddr); |
1180 | 1ca4d09a | Gleb Natapov | |
1181 | 1ca4d09a | Gleb Natapov | add_boot_device_path(d->conf.bootindex, &pci_dev->qdev, "/ethernet-phy@0");
|
1182 | 1ca4d09a | Gleb Natapov | |
1183 | 81a322d4 | Gerd Hoffmann | return 0; |
1184 | 9d07d757 | Paul Brook | } |
1185 | 72da4208 | aliguori | |
1186 | fbdaa002 | Gerd Hoffmann | static void qdev_e1000_reset(DeviceState *dev) |
1187 | fbdaa002 | Gerd Hoffmann | { |
1188 | fbdaa002 | Gerd Hoffmann | E1000State *d = DO_UPCAST(E1000State, dev.qdev, dev); |
1189 | fbdaa002 | Gerd Hoffmann | e1000_reset(d); |
1190 | fbdaa002 | Gerd Hoffmann | } |
1191 | fbdaa002 | Gerd Hoffmann | |
1192 | 0aab0d3a | Gerd Hoffmann | static PCIDeviceInfo e1000_info = {
|
1193 | fbdaa002 | Gerd Hoffmann | .qdev.name = "e1000",
|
1194 | fbdaa002 | Gerd Hoffmann | .qdev.desc = "Intel Gigabit Ethernet",
|
1195 | fbdaa002 | Gerd Hoffmann | .qdev.size = sizeof(E1000State),
|
1196 | fbdaa002 | Gerd Hoffmann | .qdev.reset = qdev_e1000_reset, |
1197 | be73cfe2 | Juan Quintela | .qdev.vmsd = &vmstate_e1000, |
1198 | fbdaa002 | Gerd Hoffmann | .init = pci_e1000_init, |
1199 | fbdaa002 | Gerd Hoffmann | .exit = pci_e1000_uninit, |
1200 | 5ee8ad71 | Alex Williamson | .romfile = "pxe-e1000.rom",
|
1201 | e72d5c9d | Isaku Yamahata | .vendor_id = PCI_VENDOR_ID_INTEL, |
1202 | e72d5c9d | Isaku Yamahata | .device_id = E1000_DEVID, |
1203 | e72d5c9d | Isaku Yamahata | .revision = 0x03,
|
1204 | e72d5c9d | Isaku Yamahata | .class_id = PCI_CLASS_NETWORK_ETHERNET, |
1205 | fbdaa002 | Gerd Hoffmann | .qdev.props = (Property[]) { |
1206 | fbdaa002 | Gerd Hoffmann | DEFINE_NIC_PROPERTIES(E1000State, conf), |
1207 | fbdaa002 | Gerd Hoffmann | DEFINE_PROP_END_OF_LIST(), |
1208 | fbdaa002 | Gerd Hoffmann | } |
1209 | 0aab0d3a | Gerd Hoffmann | }; |
1210 | 0aab0d3a | Gerd Hoffmann | |
1211 | 9d07d757 | Paul Brook | static void e1000_register_devices(void) |
1212 | 9d07d757 | Paul Brook | { |
1213 | 0aab0d3a | Gerd Hoffmann | pci_qdev_register(&e1000_info); |
1214 | 7c23b892 | balrog | } |
1215 | 9d07d757 | Paul Brook | |
1216 | 9d07d757 | Paul Brook | device_init(e1000_register_devices) |