History | View | Annotate | Download (3.4 kB)
target-ppc: Convert XER accesses to TCG
Define XER bits as a single register and access them individually toavoid defining 5 32-bit registers (TCG doesn't permit to map 8-bitregisters).
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5500 c046a42c-6fe2-441c-8c8c-71466251a162
ppc: cleanup register types
- use target_ulong for gpr and dyngen registers- remove ppc_gpr_t type- define 64-bit dyngen registers for GPE register on 32-bit targets
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5154 c046a42c-6fe2-441c-8c8c-71466251a162
PowerPC hypervisor mode is not fundamentally available only for PowerPC 64.Remove TARGET_PPC64 dependency and add code provision to be able to define a fake 32 bits CPU with hypervisor feature support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3678 c046a42c-6fe2-441c-8c8c-71466251a162
Always make all PowerPC exception definitions visible.Always make the hypervisor timers available.Remove all TARGET_PPC64H checks, keeping a few if (0) tests for casesthat cannot be properly handled with the current PowerPC CPU definition.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3656 c046a42c-6fe2-441c-8c8c-71466251a162
PowerPC 601 need specific callbacks for its BATs setup.Implement PowerPC 601 HID0 register, needed for little-endian mode support.As a consequence, we need to merge hflags coming from MSR with other ones.Use little-endian mode from hflags instead of MSR during code translation....
Implement power-management for all defined PowerPC CPUs.Fix PowerPC 970MP definition.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3440 c046a42c-6fe2-441c-8c8c-71466251a162
Gprof prooved the PowerPC emulation spent too much time in MSR load and storeroutines. Coming back to a raw MSR storage model then speed-up the emulation.Improve fast MSR updates (wrtee wrteei and mtriee cases).Share rfi family instructions helpers code to avoid bug in duplicated code....