fpu: move public header file to include/fpu
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
qom: move include files to include/qom/
exec: move include files to include/exec/
build: kill libdis, move disassemblers to disas/
exec: refactor cpu_restore_state
Refactor common code around calls to cpu_restore_state().
tb_find_pc() has now no external users, make it static.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
TCG: Use gen_opc_instr_start from context instead of global variable.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
TCG: Use gen_opc_pc from context instead of global variable.
TCG: Use gen_opc_icount from context instead of global variable.
TCG: Use gen_opc_buf from context instead of global variable.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
TCG: Use gen_opc_ptr from context instead of global variable.
disas: avoid using cpu_single_env
Pass around CPUArchState instead of using global cpu_single_env.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Acked-by: Richard Henderson <rth@twiddle.net>Acked-by: Aurelien Jarno <aurelien@aurel32.net>Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
cpus: Pass CPUState to [qemu_]cpu_has_work()
For target-mips also change the return type to bool.
Make include paths for cpu-qom.h consistent for alpha and unicore32.
Signed-off-by: Andreas Färber <afaerber@suse.de>[AF: Updated new target-openrisc function accordingly]...
target-sh4: rename helper flags
Rename helper flags to the new ones. This is purely a mechanical change,it's possible to use better flags by looking at the helpers.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Rename target_phys_addr_t to hwaddr
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes arereserved) and its purpose doesn't match the name (most target_phys_addr_taddresses are not target specific). Replace it with a finger-friendly,...
Emit debug_insn for CPU_LOG_TB_OP_OPT as well.
For all targets that currently call tcg_gen_debug_insn_start,add CPU_LOG_TB_OP_OPT to the condition that gates it.
This is useful for comparing optimization dumps, when thepre-optimization dump is merely noise....
target-sh4: implement addv and subv using TCG
addv and subv helpers implementation is directly copied from the SH4manual and looks quite complex. It is however possible to explain itwithout branches, and is therefore possible to implement it with TCG....
target-sh4: optimize xtrct
The register being 32 bit long, after a shift to the right by 16 bits,the upper 16 bit are already cleared. There is no need to call ext16uto clear them.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-sh4: optimize swap.w
It's possible swap the two 16-bit words of a 32-bit register using arotation. If the TCG target doesn't implement rotation, the replacementcode is similar to the previously implemented code.
target-sh4: remove gen_clr_t() and gen_set_t()
gen_clr_t() and gen_set_t() have very few callers and can be remplacedby a single line. Remove them.
target-sh4: rework exceptions handling
Since commit fd4bab102 PC is restored in case of exception through coderetranslation. While it is clearly the thing to do in case it is notnot known if an helper is going to trigger an exception or not(e.g. for load/store, FPU, etc.), it just make things slower when the...
target-sh4: cleanup DisasContext
We should avoid accessing env at translation stage, except of course forstatic values like the supported features.
Remove variables copied from env in DisasContext and use the TB flagsinstead.
target-sh4: remove useless code
Almost dead code.
target-sh4: mark a few helpers const and pure
target-sh4: use float32_muladd() to implement fmac
There is no need to add a SH4 specific pickNaNMulAdd() to softfloat asSH4 is always returning a default NaN.
target-sh4: implement addc and subc using TCG
Now that setcond is available, the addc and subc can easily beimplemented using TCG.
target-sh4: switch to AREG0 free mode
Add an explicit CPUState parameter instead of relying on AREG0and switch to AREG0 free mode.
Acked-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
build: move other target-*/ objects to nested Makefile.objs
build: move libobj-y variable to nested Makefile.objs
build: move obj-TARGET-y variables to nested Makefile.objs
Also drop duplicate occurrence of device-hotplug.o.
Kill off cpu_state_reset()
In commit 1bba0dc932e8826a7d030df3767daf0bc339f9a2 cpu_reset()was renamed to cpu_state_reset(), to allow introducing a new cpu_reset()that would operate on QOM objects.
All callers have been updated except for one in target-mips, so drop all...
target-sh4: Let cpu_sh4_init() return SuperHCPU
Turn cpu_init macro into a static inline function returningCPUSH4State for backwards compatibility.
Signed-off-by: Andreas Färber <afaerber@suse.de>
target-sh4: QOM'ify CPU
Embed CPUSH4State as first member of SuperHCPU.
Let CPUClass::reset() call cpu_state_reset() for now.
Signed-off-by: Andreas Färber <afaerber@suse.de>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
target-sh4: QOM'ify CPU reset
Move code from cpu_state_reset() to QOM superh_cpu_reset().
target-sh4: Start QOM'ifying CPU init
Move code from cpu_sh4_init() into a QOM initfn.
Use uintptr_t for various op related functions
Use uintptr_t instead of void * or unsigned long inseveral op related functions, env->mem_io_pc andGETPC macro.
Reviewed-by: Stefan Weil <sw@weilnetz.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Rename CPUState -> CPUArchState
Scripted conversion: for file in .[hc] hw/.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do sed -i "s/CPUState/CPUArchState/g" $file done...
target-sh4: Don't overuse CPUState
Scripted conversion: sed -i "s/CPUState/CPUSH4State/g" target-sh4/*.[hc] sed -i "s/#define CPUSH4State/#define CPUState/" target-sh4/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Anthony Liguori <aliguori@us.ibm.com>
Rename cpu_reset() to cpu_state_reset()
Frees the identifier cpu_reset for QOM CPUs (manual rename).
Don't hide the parameter type behind explicit casts, use staticfunctions with strongly typed argument to indirect.
Signed-off-by: Andreas Färber <afaerber@suse.de>...
target-sh4: Clean includes
Remove some include statements which are not needed.
Cc: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Stefan Weil <sw@weilnetz.de>
target-sh4: ignore ocbp and ocbwb instructions
ocbp and ocbwb controls the writeback of a cache line to memory. Theyare supposed to do nothing in case of a cache miss. Given QEMU onlypartially emulate caches, it is safe to ignore these instructions.
This fixes a kernel oops when trying to access an rtl8139 NIC with...
target-sh4: Fix operands for fipr, ftrv instructions
Coverity complained about right shifts of opcode (16, 18) which werelarger than the size of opcode (16 bit).
Using the correct shift values fixes this.
Cc: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Stefan Weil <sw@weilnetz.de>...
Merge remote-tracking branch 'stefanha/trivial-patches' into staging
fix spelling in target sub directory
Cc: Richard Henderson <rth@twiddle.net>Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com>Cc: Aurelien Jarno <aurelien@aurel32.net>Cc: Alexander Graf <agraf@suse.de>Cc: Aurelien Jarno <aurelien@aurel32.net>Cc: Blue Swirl <blauwirbel@gmail.com>...
sh_intc: convert interrupt controller to memory API
Signed-off-by: Benoit Canet <benoit.canet@gmail.com>Signed-off-by: Avi Kivity <avi@redhat.com>
softmmu_header: pass CPUState to tlb_fill
Pass CPUState pointer to tlb_fill() instead of architecture localcpu_single_env hacks.
Use glib memory allocation and free functions
qemu_malloc/qemu_free no longer exist after this commit.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Remove unused is_softmmu parameter from cpu_handle_mmu_fault
Parameter is_softmmu (and its evil mutant twin brother is_softmuu)is not used in cpu_*_handle_mmu_fault() functions, remove themand adjust callers.
Acked-by: Richard Henderson <rth@twiddle.net>...
exec.h cleanup
Move softmmu_exec.h include directives from target-*/exec.h totarget-*/op_helper.c. Move also various other stuff only used inop_helper.c there.
Define global env in dyngen-exec.h.
For i386, move wrappers for segment and FPU helpers from user-exec.c...
Remove exec-all.h include directives
Most exec-all.h include directives are now useless, remove them.
Move cpu_has_work and cpu_pc_from_tb to cpu.h
Move functions cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h. This isneeded by later patches.
exec.h: fix coding style and change cpu_has_work to return bool
Before the next patch, fix coding style of the areas affected.
Change the type of the return value from cpu_has_work() andqemu_cpu_has_work() to bool.
cpu_loop_exit: avoid using AREG0
Make cpu_loop_exit() take a parameter for CPUState instead of relyingon global env.
Remove unused function parameter from cpu_restore_state
The previous patch removed the need for parameter puc.Is is now unused, so remove it.
Cc: Aurelien Jarno <aurelien@aurel32.net>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Remove unused function parameters from gen_pc_load and rename the function
Function gen_pc_load was introduced in commitd2856f1ad4c259e5766847c49acbb4e390731bd4.The only reason for parameter searched_pc wasa debug statement in target-i386/translate.c....
target-sh4: get rid of CPU_{Float,Double}U
SH4 is always using softfloat, so it's possible to have helpers directlytaking float32 or float64 value. This allow to get rid of conversionsthrough CPU_{Float,Double}U.
Fix conversions from pointer to tcg_target_long
tcg_gen_exit_tb takes a parameter of type tcg_target_long,so the type casts of pointer to long should be replaced bytype casts of pointer to tcg_target_long (suggested by Blue Swirl).
These changes are needed for build environments where...
inline cpu_halted into sole caller
All implementations are now the same, and there is only one caller,so inline the function there.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-sh4: move intr_at_halt out of cpu_halted()
All targets except SH4 have the same cpu_halted() routine, and it hasonly one caller. It is therefore a good candidate for inlining.
The difference is the handling of the intr_at_halt, which is necessary...
target-sh4: fix negc
sh4: implement missing mmaped TLB write functions
sh4: implement missing mmaped TLB read functions
target-sh4: update PTEH upon MMU exception
Update the PTEH register to contain the VPN at which an MMUexception occured as specified by the SH4 reference.
Signed-off-by: Alexandre Courbot <gnurou@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-sh4: fix index of address read error exception
Exception index of address read error should be 0x0e0.
target-sh4: fix TLB invalidation code
In cpu_sh4_invalidate_tlb, the UTLB was invalidated twice and theITLB left unchaged, probably because of some unfortunate copy/paste.
target-sh4: use rotl/rotr when possible
target-sh4: implement negc using TCG
Using setcond it's now possible to generate a relatively short negcinstruction in TCG.
target-sh4: correct use of ! and &
Fix wrong usage of ! and & in MMU related functions. Thanks to BlueSwirl for reporting the issue.
Reported-by: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-sh4: define FPSCR constants
Define FPSCR constants for all field and use them instead of hardcodedvalues.
target-sh4: implement flush-to-zero
When the FPSCR.DN bit is set, the SH4 FPU treat denormalized numbers aszero. Enable the corresponding softfloat option when this bit is set.
target-sh4: implement FPU exceptions
FPU exception support where not implemented on SH4. Implement them byclearing the softfloat exceptions flags before an FP instruction (theSH4 FPU also clear them before an instruction), and calling a functionto update the FPSCR register after an FP instruction. This function...
target-sh4: add fipr instruction
Add the fipr FVm,FVn instruction, which computes the inner products ofa 4-dimensional single precision floating-point vector.
target-sh4: add ftrv instruction
Add the ftrv XMTRX,FVn instruction, which computes the 4-row x 4-columnmatrix XMTRX by the 4-dimensional vector FVn.
target-sh4: optimize exceptions
As exception is not the normal path, don't bother saving PC, beforeraising one, instead rely on code retranslation to get the CPU state.
target-sh4: fix reset on r2d
target-sh4: simplify comparisons after a 'and' op
When a TCG variable is anded with a value and the compared with the samevalue, we can simply invert the comparison and compare it with 0. Thegenerated code is smaller.
target-sh4: log instructions start in TCG code
target-sh4: use setcond when possible
target-sh4: use default-NaN mode
SH4 FPU doesn't propagate NaN, and instead always regenerate new ones.Enable the default-NaN mode by default.
target-sh4: fix fpu disabled/illegal exception
Illegal instructions in a slot delay should generate a slot illegalinstruction exception instead of an illegal instruction exception.
The current PC should be saved before generating such an exception,but should not be corrected if in a delay slot, given it's already...
target-sh4: improve TLB
SH4 is using 16-bit instructions which means most of the constants areloaded through a constant pool at the end of the subroutine. The samememory page is therefore accessed in exec and read mode.
With the current implementation, a QEMU TLB entry is set to read or...
target-sh4: implement writes to mmaped ITLB
Some Linux kernels seems to implement ITLB/UTLB flushing through bywriting all TLB entries through the memory mapped interface insteadof writing one to MMUCR.TI.
Implement memory mapped ITLB write interface so that such kernels can...
target-xxx: Use fprintf_function (format checking)
fprintf_function uses format checking with GCC_FMT_ATTR.
Cc: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Stefan Weil <weil@mail.berlios.de>...
target-sh4: Add support for ldc & stc with sgr
Add support for the following missing priviledged intructions:
For SH4:- stc sgr, Rn- stc.l sgr, @-Rn
For SH4A:- ldc Rm, sgr- ldc.l @Rm+, sgr
target-sh4: Split the LDST macro into 2 sub-macros
The LDST macro is used to generate ldc and stc instructions that work with aspecific register. However, the SGR register only supports stc up to SH4A,which supports both stc and ldc. This patch creates two sub-macros named LD...
remove exec-all.h inclusion from cpu.h
move cpu_pc_from_tb to target-*/exec.h
target-sh4: Remove duplicate CPU log.
Logging for -d cpu is done in generic code.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
remove TARGET_* defines from translate-all.c
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Replace assert(0) with abort() or cpu_abort()
When building with -DNDEBUG, assert(0) will not stop executionso it must not be used for abnormal termination.
Use cpu_abort() when in CPU context, abort() otherwise.
Large page TLB flush
QEMU uses a fixed page size for the CPU TLB. If the guest uses largepages then we effectively split these into multiple smaller pages, andpopulate the corresponding TLB entries on demand.
When the guest invalidates the TLB by virtual address we must invalidate...
Target specific usermode cleanup
Disable various target specific code that is only relevant to system emulation.
Signed-off-by: Paul Brook <paul@codesourcery.com>
Remove cpu_get_phys_page_debug from userspace emulation
cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it.
Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.
Removes a set of ifdefs from exec.c.
Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets otherthan Alpha. This will be used for page_find_alloc, which issupposed to be using virtual addresses in the first place....
Fix incorrect exception_index use
env->exception_index should be cleared with -1, not 0.
See also 821b19fe923ac49a24cdb4af902584fdd019cee6.
Spotted by Igor Kovalenko.
target-sh4: MMU: separate execute and read/write permissions
On SH4, the ITLB and UTLB configurations are memory mapped, so loadingITLB entries from UTLB has to be simulated correctly. For that the QEMUTLB has to be handle the execute (ITLB) and read/write permissions...
target-sh4: MMU: fix ITLB priviledge check
There is an ITLB access violation if SR_MD=0 (user mode) whilethe high bit of the protection key is 0 (priviledge mode).
target-sh4: MMU: optimize UTLB accesses
With the current code, the QEMU TLB is setup to match the read/writemode of the MMU fault. This means when read access is done, the pageis setup in read-only mode. When the page is later accessed in writemode, an MMU fault happened, and the page is switch in write-only...
target-sh4: MMU: reduce the size of a TLB entry
Reduce the size of the TLB entry from 32 to 16 bytes, reorganisingmembers and using a bit field.
target-sh4: MMU: remove dead code
target-sh4: MMU: fix store queue addresses
The store queues are located from 0xe0000000 to 0xe3ffffff.