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SH: Implement MOVCO.L and MOVLI.L
(Vladimir Prus)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6666 c046a42c-6fe2-441c-8c8c-71466251a162
SH7750/51: add register BCR3, BCR4, PCR, RTCOR, RTCNT, RTCSR, SDMR2, SDMR3 and fix BCR2 support
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6548 c046a42c-6fe2-441c-8c8c-71466251a162
targets: remove error handling from qemu_malloc() callers (Avi Kivity)
Signed-off-by: Avi Kivity <avi@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6530 c046a42c-6fe2-441c-8c8c-71466251a162
Log reset events (Jan Kiszka)
Original idea&code by Kevin Wolf, split-up in two patches and added morearchs.
This patch introduces a flag to log CPU resets. Useful for tracingunexpected resets (such as those triggered by x86 triple faults).
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>...
global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost)
These are references to 'loglevel' that aren't on a simple 'if (loglevel &X) qemu_log()' statement.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>...
Convert references to logfile/loglevel to use qemu_log*() macros
This is a large patch that changes all occurrences of logfile/loglevelglobal variables to use the new qemu_log*() macros.
sh4: Add FMAC instruction support
Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>Signed-off-by: Lionel Landwerlin <lionel.landwerlin@openwide.fr>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6309 c046a42c-6fe2-441c-8c8c-71466251a162
Update FSF address in GPL/LGPL boilerplate
The attached patch updates the FSF address in the GPL/LGPL boilerplatein most GPL/LGPLed files, and also in COPYING.LIB.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
tcg_temp_local_new should take no parameter
This patch removes useless type information in some calls totcg_temp_local_new. It also removes the parameter from themacro declaration; if a target has to use a specific non-defaultsize then it should use tcg_temp_local_new_{i32,i64}....
Use the ARRAY_SIZE() macro where appropriate.
Change from v1: Avoid changing the existing coding style in certain files.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6120 c046a42c-6fe2-441c-8c8c-71466251a162
target-sh4: make the initial value of SR easier to read
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6016 c046a42c-6fe2-441c-8c8c-71466251a162
target-sh4: don't disable FPU instructions in user mode
Based on a patch from Lionel Landwerlin.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6015 c046a42c-6fe2-441c-8c8c-71466251a162
target-sh4: disable debug code
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6014 c046a42c-6fe2-441c-8c8c-71466251a162
target-sh4: add prefi, icbi, synco
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6013 c046a42c-6fe2-441c-8c8c-71466251a162
target-sh4: add SH7785 as CPU option
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6012 c046a42c-6fe2-441c-8c8c-71466251a162
target-sh4: check FD bit for FP instructions
Based on a patch from Vladimir Prus <vladimir@codesourcery.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5970 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: kill a few warnings
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5938 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: Implement FD bit
SH4 manual say that if a floating point instruction is executed whileFD bit in the status register is 1, an exception should be raised. QEMUpresently does not do that, so the kernel does not initialize FP statefor any thread, nor does it save/restore FP state. The most apparent...
Use sys-queue.h for break/watchpoint managment (Jan Kiszka)
This switches cpu_break/watchpoint_* to TAILQ wrappers, simplifying thecode and also fixing a use after release issue incpu_break/watchpoint_remove_all.
target-sh4: fix 64-bit fmov to/from memory
When loading/storing a register pair, the even-numbered registeralways maps to the low 32 bits of memory independently of targetendian configuration.
Signed-off-by: Mans Rullgard <mans@mansr.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
target-sh4: fix fldi0/fldi1
fldi0/fldi1 should be executed as a nop if FPSCR.FR is set instead ofgenerating an exception. Reported by Laurent Desnogues.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5759 c046a42c-6fe2-441c-8c8c-71466251a162
target-sh4: map FP registers as TCG variables
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5758 c046a42c-6fe2-441c-8c8c-71466251a162
Refactor and enhance break/watchpoint API (Jan Kiszka)
This patch prepares the QEMU cpu_watchpoint/breakpoint API to allow thesucceeding enhancements this series comes with.
First of all, it overcomes MAX_BREAKPOINTS/MAX_WATCHPOINTS by switchingto dynamically allocated data structures that are kept in linked lists....
TCG variable type checking.
Signed-off-by: Paul Brook <paul@codesourcery.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
Fix undeclared symbol warnings from sparse
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5539 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: Implement MOVUA.L
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5473 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: fix single-stepping
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5472 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: Fix swap.b
The SH4 manual documents the swap.b instruction as follows:
SWAP.B Rm,Rn Rm → swap lower 2 bytes → Rn
Current QEMU code, in addition to the above, also clears the high16 bits. The immediate breakage I saw is that htonl function applied...
Silence some warnings about no value returned from non-void function
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5430 c046a42c-6fe2-441c-8c8c-71466251a162
Add concat_i32_i64 op.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5280 c046a42c-6fe2-441c-8c8c-71466251a162
Suppress gcc 4.x -Wpointer-sign (included in -Wall) warnings
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5275 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: Privilege check for instructions
This patch adds check for all SH4 instructions which areexecuted only in privileged mode.
(Shin-ichiro KAWASAKI)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5224 c046a42c-6fe2-441c-8c8c-71466251a162
sh4: doesn't set the cpu_model_str
Fix setting of cpu_model_str for sh4
(Michael Trimarchi)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5222 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: sleep instruction bug fix
fix a bug on 'sleep' instruction, which have caused halt of idle task.As i386 'hlt' instruction does, it should save PC before sleep.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5220 c046a42c-6fe2-441c-8c8c-71466251a162
sh4: CPU versioning.
Trivial patch adding CPU listing and the ability to do per-subtypeCVR/PVR/PRR values. Presently SH7750R and SH7751R definitions areprovided, as these are the ones in present use in-tree.
The CVR value for SH7751R is intentionally restricted so the kernel...
SH4: fix a regression introduced in r5122
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5132 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: Remove dyngen leftovers
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5126 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: final conversion to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5125 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: convert floating-point ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5124 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: Remove most uses of cpu_T0 and cpu_T1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5122 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: TCG optimisations
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5121 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: Convert remaining non-fp ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5120 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: Convert shift functions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5119 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: convert control/status register load/store to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5118 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: Convert memory loads/stores to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5117 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: convert some more arithmetics ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5116 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: convert a few helpers to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5112 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: convert branch/jump instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5111 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: convert simple compare instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5108 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: convert a few control or system register functions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5107 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: Fix bugs introduce in r5099
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5106 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: fix xtrct Rm,Rn (broken in r5103)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5105 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: convert logic and arithmetic ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5103 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: use TCG variables for gregs
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5102 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: use uint32_t/i32 based types/ops
Use uint32_t/i32 based types/ops to stay consistent with previous dyngencode. Thanks to Paul Brook for noticing that.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5101 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: Convert register moves to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5100 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: Convert dyngen registers moves to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5099 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: Convert immediate loads to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5098 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: add support for TCG helpers
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5096 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: Init TCG variables
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5095 c046a42c-6fe2-441c-8c8c-71466251a162
sh4: fix tas.b @Rn instruction
(Shin-ichiro KAWASAKI, based on a patch from Andrzej Zaborowski)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5074 c046a42c-6fe2-441c-8c8c-71466251a162
[sh4] code translation bug fix
When a TLB miss occurs while pre-decrement store instruction such as"mov.l Rm, @-Rn" is executed, re-execution of such instruction causestatus confusion. Because pre Rn decrement is executed before TLB miss,re-execution decrements Rn again....
[sh4] delay slot bug fix
Two bugs about delay slot handlings are fixed.
- After an exception occurred in delay slot, the branch instruction before delay slot should be executed again. To judge such re-execution is necessery or not, delay slot status is kept in SH4 CPU data structure....
[sh4] sleep instruction
This patch adds sleep instruction.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5065 c046a42c-6fe2-441c-8c8c-71466251a162
Fix warnings that would be generated by gcc -Wstrict-prototypes
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5021 c046a42c-6fe2-441c-8c8c-71466251a162
Small cleanup of gen_intermediate_code(_internal), by Laurent Desnogues.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4891 c046a42c-6fe2-441c-8c8c-71466251a162
Add missing static qualifiers.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4801 c046a42c-6fe2-441c-8c8c-71466251a162
Add instruction counter.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4799 c046a42c-6fe2-441c-8c8c-71466251a162
SH4 MMU improvements
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4396 c046a42c-6fe2-441c-8c8c-71466251a162
Factorize code in translate.c
(Glauber Costa)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4274 c046a42c-6fe2-441c-8c8c-71466251a162
Remove osdep.c/qemu-img code duplication
(Kevin Wolf)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4191 c046a42c-6fe2-441c-8c8c-71466251a162
SH4, fix several instructions
fix instruction code for frchg, fschg, ocbp.fix addressing mode handling for Rn+, -Rn, (disp,gbr).fix operation for div0s.fix comments for mov imm, add imm, (r0+,gbr), mac.l Rm+,@Rn+.fix ldb to ldub for or/tst/xor.b #imm,(r0,gbr)....
Rn+,
(disp,gbr).fix operation for div0s.fix comments for mov imm, add imm,
Rm+,@Rn+.fix ldb to ldub for or/tst/xor.b #imm,
use the TCG code generator
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3944 c046a42c-6fe2-441c-8c8c-71466251a162
SH4 delay slot code update, by Magnus Damm.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3761 c046a42c-6fe2-441c-8c8c-71466251a162
fixed FPU rounding init
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3615 c046a42c-6fe2-441c-8c8c-71466251a162
added cpu_model parameter to cpu_init()
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3562 c046a42c-6fe2-441c-8c8c-71466251a162
Fix rte opcode, by Magnus Damm.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3273 c046a42c-6fe2-441c-8c8c-71466251a162
find -type f | xargs sed -i 's/[\t ]$//g' # on most files
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
Fix tb->size mishandling, by Daniel Jacobowitz.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3160 c046a42c-6fe2-441c-8c8c-71466251a162
SH4 mov.b fix, by Vince Weaver.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3152 c046a42c-6fe2-441c-8c8c-71466251a162
Ignore PR flag in FPSCR when performing fmov, by Magnus Damm.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3005 c046a42c-6fe2-441c-8c8c-71466251a162
Document FPSCR usage, by Magnus Damm.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3004 c046a42c-6fe2-441c-8c8c-71466251a162
Use DREG instead of XREG wherever possible, by Magnus Damm.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3003 c046a42c-6fe2-441c-8c8c-71466251a162
Emulate more fpu opcodes, by Magnus Damm.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3002 c046a42c-6fe2-441c-8c8c-71466251a162
Set FD bit in SR to emulate kernel behaviour, by Magnus Damm.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2999 c046a42c-6fe2-441c-8c8c-71466251a162
Fix XHACK macro and use FREG if possible, by Magnus Damm.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2815 c046a42c-6fe2-441c-8c8c-71466251a162
Fix opcode for sts.l fpul/cpscr, by Magnus Damm.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2729 c046a42c-6fe2-441c-8c8c-71466251a162
Define gen_intermediate_code_internal as "static inline".
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2512 c046a42c-6fe2-441c-8c8c-71466251a162
SH bugfixes.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1991 c046a42c-6fe2-441c-8c8c-71466251a162
Remove debug output.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1990 c046a42c-6fe2-441c-8c8c-71466251a162
SH usermode fault handling.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1988 c046a42c-6fe2-441c-8c8c-71466251a162
SH4 rts fix.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1987 c046a42c-6fe2-441c-8c8c-71466251a162
sh4 fmov et al instructions (amatus)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1971 c046a42c-6fe2-441c-8c8c-71466251a162
sh4 target (Samuel Tardieu)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1861 c046a42c-6fe2-441c-8c8c-71466251a162