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Name Size
Makefile.objs 465 Bytes
arm-semi.c 17.2 kB
cpu-qom.h 5.9 kB
cpu.c 32.5 kB
cpu.h 38.6 kB
cpu64.c 3.5 kB
crypto_helper.c 13 kB
gdbstub.c 2.8 kB
gdbstub64.c 1.9 kB
helper-a64.c 4.3 kB
helper-a64.h 1.4 kB
helper.c 143.6 kB
helper.h 18.8 kB
iwmmxt_helper.c 24.8 kB
kvm-consts.h 3.8 kB
kvm-stub.c 437 Bytes
kvm.c 9.4 kB
kvm32.c 15.7 kB
kvm64.c 5.2 kB
kvm_arm.h 3.8 kB
machine.c 7.9 kB
neon_helper.c 52.7 kB
op_addsub.h 1.8 kB
op_helper.c 8.9 kB
translate-a64.c 247.6 kB
translate.c 377.7 kB
translate.h 1.9 kB

Latest revisions

# Date Author Comment
ab1da857 02/11/2014 02:57 pm Edgar E. Iglesias

exec: Make stl_*_phys input an AddressSpace

Reviewed-by: Peter Maydell <>
Signed-off-by: Edgar E. Iglesias <>
2c17449b 02/11/2014 02:57 pm Edgar E. Iglesias

exec: Make ldq/ldub_*_phys input an AddressSpace

Reviewed-by: Peter Maydell <>
Signed-off-by: Edgar E. Iglesias <>
fdfba1a2 02/11/2014 02:56 pm Edgar E. Iglesias

exec: Make ldl_*_phys input an AddressSpace

Reviewed-by: Peter Maydell <>
Signed-off-by: Edgar E. Iglesias <>
999b53ec 02/08/2014 04:50 pm Claudio Fontana

disas: Implement disassembly output for A64

Use libvixl to implement disassembly output in debug
logs for A64, for use with both AArch64 hosts and targets.

Signed-off-by: Claudio Fontana <>
[PMM: * added support for target disassembly...
94b6c911 02/08/2014 04:47 pm Peter Maydell

target-arm: A64: Implement 2-register misc compares, ABS, NEG

Implement the simple 2-register-misc operations we can share
with the scalar-two-register-misc code. (SUQADD, USQADD, SQABS,
SQNEG also fall into this category, but aren't implemented in
the scalar-2-register case yet either.)...
86cbc418 02/08/2014 04:47 pm Peter Maydell

target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT

Implement the 2-reg-misc CNT, NOT and RBIT instructions.

Signed-off-by: Peter Maydell <>
Reviewed-by: Richard Henderson <>
d980fd59 02/08/2014 04:47 pm Peter Maydell

target-arm: A64: Add narrowing 2-reg-misc instructions

Add the narrowing integer instructions in the 2-reg-misc class.

Signed-off-by: Peter Maydell <>
Reviewed-by: Richard Henderson <>
39d82118 02/08/2014 04:47 pm Alex Bennée

target-arm: A64: Add 2-reg-misc REV* instructions

Add the byte-reverse operations REV64, REV32 and REV16 from the
two-reg-misc group.

Signed-off-by: Alex Bennée <>
Signed-off-by: Peter Maydell <>
Reviewed-by: Richard Henderson <>
f93d0138 02/08/2014 04:47 pm Peter Maydell

target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group

Add the SIMD FNEG and FABS instructions in the SIMD 2-reg-misc group.

Signed-off-by: Peter Maydell <>
Reviewed-by: Richard Henderson <>
239c20c7 02/08/2014 04:47 pm Will Newton

target-arm: Add support for AArch32 64bit VCVTB and VCVTT

Add support for the AArch32 floating-point half-precision to double-
precision conversion VCVTB and VCVTT instructions.

Signed-off-by: Will Newton <>
[PMM: fixed a minor missing-braces style issue]...

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