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1 | 79aceca5 | bellard | /*
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2 | 3fc6c082 | bellard | * PowerPC emulation helpers for qemu.
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3 | 5fafdf24 | ths | *
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4 | 76a66253 | j_mayer | * Copyright (c) 2003-2007 Jocelyn Mayer
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5 | 79aceca5 | bellard | *
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6 | 79aceca5 | bellard | * This library is free software; you can redistribute it and/or
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7 | 79aceca5 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 79aceca5 | bellard | * License as published by the Free Software Foundation; either
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9 | 79aceca5 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 79aceca5 | bellard | *
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11 | 79aceca5 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 79aceca5 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 79aceca5 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 79aceca5 | bellard | * Lesser General Public License for more details.
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15 | 79aceca5 | bellard | *
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16 | 79aceca5 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 79aceca5 | bellard | * License along with this library; if not, write to the Free Software
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18 | 79aceca5 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 79aceca5 | bellard | */
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20 | fdabc366 | bellard | #include <stdarg.h> |
21 | fdabc366 | bellard | #include <stdlib.h> |
22 | fdabc366 | bellard | #include <stdio.h> |
23 | fdabc366 | bellard | #include <string.h> |
24 | fdabc366 | bellard | #include <inttypes.h> |
25 | fdabc366 | bellard | #include <signal.h> |
26 | fdabc366 | bellard | #include <assert.h> |
27 | fdabc366 | bellard | |
28 | fdabc366 | bellard | #include "cpu.h" |
29 | fdabc366 | bellard | #include "exec-all.h" |
30 | 9a64fbe4 | bellard | |
31 | 9a64fbe4 | bellard | //#define DEBUG_MMU
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32 | 9a64fbe4 | bellard | //#define DEBUG_BATS
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33 | 76a66253 | j_mayer | //#define DEBUG_SOFTWARE_TLB
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34 | 9a64fbe4 | bellard | //#define DEBUG_EXCEPTIONS
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35 | fdabc366 | bellard | //#define FLUSH_ALL_TLBS
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36 | 9a64fbe4 | bellard | |
37 | 9a64fbe4 | bellard | /*****************************************************************************/
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38 | 3fc6c082 | bellard | /* PowerPC MMU emulation */
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39 | a541f297 | bellard | |
40 | d9bce9d9 | j_mayer | #if defined(CONFIG_USER_ONLY)
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41 | e96efcfc | j_mayer | int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
42 | 24741ef3 | bellard | int is_user, int is_softmmu) |
43 | 24741ef3 | bellard | { |
44 | 24741ef3 | bellard | int exception, error_code;
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45 | d9bce9d9 | j_mayer | |
46 | 24741ef3 | bellard | if (rw == 2) { |
47 | e1833e1f | j_mayer | exception = POWERPC_EXCP_ISI; |
48 | 24741ef3 | bellard | error_code = 0;
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49 | 24741ef3 | bellard | } else {
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50 | e1833e1f | j_mayer | exception = POWERPC_EXCP_DSI; |
51 | 24741ef3 | bellard | error_code = 0;
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52 | 24741ef3 | bellard | if (rw)
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53 | 24741ef3 | bellard | error_code |= 0x02000000;
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54 | 24741ef3 | bellard | env->spr[SPR_DAR] = address; |
55 | 24741ef3 | bellard | env->spr[SPR_DSISR] = error_code; |
56 | 24741ef3 | bellard | } |
57 | 24741ef3 | bellard | env->exception_index = exception; |
58 | 24741ef3 | bellard | env->error_code = error_code; |
59 | 76a66253 | j_mayer | |
60 | 24741ef3 | bellard | return 1; |
61 | 24741ef3 | bellard | } |
62 | 76a66253 | j_mayer | |
63 | 9b3c35e0 | j_mayer | target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr) |
64 | 24741ef3 | bellard | { |
65 | 24741ef3 | bellard | return addr;
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66 | 24741ef3 | bellard | } |
67 | 36081602 | j_mayer | |
68 | 24741ef3 | bellard | #else
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69 | 76a66253 | j_mayer | /* Common routines used by software and hardware TLBs emulation */
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70 | 76a66253 | j_mayer | static inline int pte_is_valid (target_ulong pte0) |
71 | 76a66253 | j_mayer | { |
72 | 76a66253 | j_mayer | return pte0 & 0x80000000 ? 1 : 0; |
73 | 76a66253 | j_mayer | } |
74 | 76a66253 | j_mayer | |
75 | 76a66253 | j_mayer | static inline void pte_invalidate (target_ulong *pte0) |
76 | 76a66253 | j_mayer | { |
77 | 76a66253 | j_mayer | *pte0 &= ~0x80000000;
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78 | 76a66253 | j_mayer | } |
79 | 76a66253 | j_mayer | |
80 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
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81 | caa4039c | j_mayer | static inline int pte64_is_valid (target_ulong pte0) |
82 | caa4039c | j_mayer | { |
83 | caa4039c | j_mayer | return pte0 & 0x0000000000000001ULL ? 1 : 0; |
84 | caa4039c | j_mayer | } |
85 | caa4039c | j_mayer | |
86 | caa4039c | j_mayer | static inline void pte64_invalidate (target_ulong *pte0) |
87 | caa4039c | j_mayer | { |
88 | caa4039c | j_mayer | *pte0 &= ~0x0000000000000001ULL;
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89 | caa4039c | j_mayer | } |
90 | caa4039c | j_mayer | #endif
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91 | caa4039c | j_mayer | |
92 | 76a66253 | j_mayer | #define PTE_PTEM_MASK 0x7FFFFFBF |
93 | 76a66253 | j_mayer | #define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B) |
94 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
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95 | caa4039c | j_mayer | #define PTE64_PTEM_MASK 0xFFFFFFFFFFFFFF80ULL |
96 | caa4039c | j_mayer | #define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F) |
97 | caa4039c | j_mayer | #endif
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98 | 76a66253 | j_mayer | |
99 | caa4039c | j_mayer | static inline int _pte_check (mmu_ctx_t *ctx, int is_64b, |
100 | caa4039c | j_mayer | target_ulong pte0, target_ulong pte1, |
101 | caa4039c | j_mayer | int h, int rw) |
102 | 76a66253 | j_mayer | { |
103 | caa4039c | j_mayer | target_ulong ptem, mmask; |
104 | caa4039c | j_mayer | int access, ret, pteh, ptev;
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105 | 76a66253 | j_mayer | |
106 | 76a66253 | j_mayer | access = 0;
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107 | 76a66253 | j_mayer | ret = -1;
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108 | 76a66253 | j_mayer | /* Check validity and table match */
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109 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
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110 | caa4039c | j_mayer | if (is_64b) {
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111 | caa4039c | j_mayer | ptev = pte64_is_valid(pte0); |
112 | caa4039c | j_mayer | pteh = (pte0 >> 1) & 1; |
113 | caa4039c | j_mayer | } else
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114 | caa4039c | j_mayer | #endif
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115 | caa4039c | j_mayer | { |
116 | caa4039c | j_mayer | ptev = pte_is_valid(pte0); |
117 | caa4039c | j_mayer | pteh = (pte0 >> 6) & 1; |
118 | caa4039c | j_mayer | } |
119 | caa4039c | j_mayer | if (ptev && h == pteh) {
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120 | 76a66253 | j_mayer | /* Check vsid & api */
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121 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
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122 | caa4039c | j_mayer | if (is_64b) {
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123 | caa4039c | j_mayer | ptem = pte0 & PTE64_PTEM_MASK; |
124 | caa4039c | j_mayer | mmask = PTE64_CHECK_MASK; |
125 | caa4039c | j_mayer | } else
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126 | caa4039c | j_mayer | #endif
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127 | caa4039c | j_mayer | { |
128 | caa4039c | j_mayer | ptem = pte0 & PTE_PTEM_MASK; |
129 | caa4039c | j_mayer | mmask = PTE_CHECK_MASK; |
130 | caa4039c | j_mayer | } |
131 | caa4039c | j_mayer | if (ptem == ctx->ptem) {
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132 | 76a66253 | j_mayer | if (ctx->raddr != (target_ulong)-1) { |
133 | 76a66253 | j_mayer | /* all matches should have equal RPN, WIMG & PP */
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134 | caa4039c | j_mayer | if ((ctx->raddr & mmask) != (pte1 & mmask)) {
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135 | caa4039c | j_mayer | if (loglevel != 0) |
136 | 76a66253 | j_mayer | fprintf(logfile, "Bad RPN/WIMG/PP\n");
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137 | 76a66253 | j_mayer | return -3; |
138 | 76a66253 | j_mayer | } |
139 | 76a66253 | j_mayer | } |
140 | 76a66253 | j_mayer | /* Compute access rights */
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141 | 76a66253 | j_mayer | if (ctx->key == 0) { |
142 | 76a66253 | j_mayer | access = PAGE_READ; |
143 | 76a66253 | j_mayer | if ((pte1 & 0x00000003) != 0x3) |
144 | 76a66253 | j_mayer | access |= PAGE_WRITE; |
145 | 76a66253 | j_mayer | } else {
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146 | 76a66253 | j_mayer | switch (pte1 & 0x00000003) { |
147 | 76a66253 | j_mayer | case 0x0: |
148 | 76a66253 | j_mayer | access = 0;
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149 | 76a66253 | j_mayer | break;
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150 | 76a66253 | j_mayer | case 0x1: |
151 | 76a66253 | j_mayer | case 0x3: |
152 | 76a66253 | j_mayer | access = PAGE_READ; |
153 | 76a66253 | j_mayer | break;
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154 | 76a66253 | j_mayer | case 0x2: |
155 | 76a66253 | j_mayer | access = PAGE_READ | PAGE_WRITE; |
156 | 76a66253 | j_mayer | break;
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157 | 76a66253 | j_mayer | } |
158 | 76a66253 | j_mayer | } |
159 | 76a66253 | j_mayer | /* Keep the matching PTE informations */
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160 | 76a66253 | j_mayer | ctx->raddr = pte1; |
161 | 76a66253 | j_mayer | ctx->prot = access; |
162 | 76a66253 | j_mayer | if ((rw == 0 && (access & PAGE_READ)) || |
163 | 76a66253 | j_mayer | (rw == 1 && (access & PAGE_WRITE))) {
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164 | 76a66253 | j_mayer | /* Access granted */
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165 | 76a66253 | j_mayer | #if defined (DEBUG_MMU)
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166 | 4a057712 | j_mayer | if (loglevel != 0) |
167 | 76a66253 | j_mayer | fprintf(logfile, "PTE access granted !\n");
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168 | 76a66253 | j_mayer | #endif
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169 | 76a66253 | j_mayer | ret = 0;
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170 | 76a66253 | j_mayer | } else {
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171 | 76a66253 | j_mayer | /* Access right violation */
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172 | 76a66253 | j_mayer | #if defined (DEBUG_MMU)
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173 | 4a057712 | j_mayer | if (loglevel != 0) |
174 | 76a66253 | j_mayer | fprintf(logfile, "PTE access rejected\n");
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175 | 76a66253 | j_mayer | #endif
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176 | 76a66253 | j_mayer | ret = -2;
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177 | 76a66253 | j_mayer | } |
178 | 76a66253 | j_mayer | } |
179 | 76a66253 | j_mayer | } |
180 | 76a66253 | j_mayer | |
181 | 76a66253 | j_mayer | return ret;
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182 | 76a66253 | j_mayer | } |
183 | 76a66253 | j_mayer | |
184 | caa4039c | j_mayer | static int pte32_check (mmu_ctx_t *ctx, |
185 | caa4039c | j_mayer | target_ulong pte0, target_ulong pte1, int h, int rw) |
186 | caa4039c | j_mayer | { |
187 | caa4039c | j_mayer | return _pte_check(ctx, 0, pte0, pte1, h, rw); |
188 | caa4039c | j_mayer | } |
189 | caa4039c | j_mayer | |
190 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
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191 | caa4039c | j_mayer | static int pte64_check (mmu_ctx_t *ctx, |
192 | caa4039c | j_mayer | target_ulong pte0, target_ulong pte1, int h, int rw) |
193 | caa4039c | j_mayer | { |
194 | caa4039c | j_mayer | return _pte_check(ctx, 1, pte0, pte1, h, rw); |
195 | caa4039c | j_mayer | } |
196 | caa4039c | j_mayer | #endif
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197 | caa4039c | j_mayer | |
198 | 76a66253 | j_mayer | static int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p, |
199 | 76a66253 | j_mayer | int ret, int rw) |
200 | 76a66253 | j_mayer | { |
201 | 76a66253 | j_mayer | int store = 0; |
202 | 76a66253 | j_mayer | |
203 | 76a66253 | j_mayer | /* Update page flags */
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204 | 76a66253 | j_mayer | if (!(*pte1p & 0x00000100)) { |
205 | 76a66253 | j_mayer | /* Update accessed flag */
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206 | 76a66253 | j_mayer | *pte1p |= 0x00000100;
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207 | 76a66253 | j_mayer | store = 1;
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208 | 76a66253 | j_mayer | } |
209 | 76a66253 | j_mayer | if (!(*pte1p & 0x00000080)) { |
210 | 76a66253 | j_mayer | if (rw == 1 && ret == 0) { |
211 | 76a66253 | j_mayer | /* Update changed flag */
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212 | 76a66253 | j_mayer | *pte1p |= 0x00000080;
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213 | 76a66253 | j_mayer | store = 1;
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214 | 76a66253 | j_mayer | } else {
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215 | 76a66253 | j_mayer | /* Force page fault for first write access */
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216 | 76a66253 | j_mayer | ctx->prot &= ~PAGE_WRITE; |
217 | 76a66253 | j_mayer | } |
218 | 76a66253 | j_mayer | } |
219 | 76a66253 | j_mayer | |
220 | 76a66253 | j_mayer | return store;
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221 | 76a66253 | j_mayer | } |
222 | 76a66253 | j_mayer | |
223 | 76a66253 | j_mayer | /* Software driven TLB helpers */
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224 | 76a66253 | j_mayer | static int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr, |
225 | 76a66253 | j_mayer | int way, int is_code) |
226 | 76a66253 | j_mayer | { |
227 | 76a66253 | j_mayer | int nr;
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228 | 76a66253 | j_mayer | |
229 | 76a66253 | j_mayer | /* Select TLB num in a way from address */
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230 | 76a66253 | j_mayer | nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);
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231 | 76a66253 | j_mayer | /* Select TLB way */
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232 | 76a66253 | j_mayer | nr += env->tlb_per_way * way; |
233 | 76a66253 | j_mayer | /* 6xx have separate TLBs for instructions and data */
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234 | 76a66253 | j_mayer | if (is_code && env->id_tlbs == 1) |
235 | 76a66253 | j_mayer | nr += env->nb_tlb; |
236 | 76a66253 | j_mayer | |
237 | 76a66253 | j_mayer | return nr;
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238 | 76a66253 | j_mayer | } |
239 | 76a66253 | j_mayer | |
240 | 76a66253 | j_mayer | void ppc6xx_tlb_invalidate_all (CPUState *env)
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241 | 76a66253 | j_mayer | { |
242 | 1d0a48fb | j_mayer | ppc6xx_tlb_t *tlb; |
243 | 76a66253 | j_mayer | int nr, max;
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244 | 76a66253 | j_mayer | |
245 | 76a66253 | j_mayer | #if defined (DEBUG_SOFTWARE_TLB) && 0 |
246 | 76a66253 | j_mayer | if (loglevel != 0) { |
247 | 76a66253 | j_mayer | fprintf(logfile, "Invalidate all TLBs\n");
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248 | 76a66253 | j_mayer | } |
249 | 76a66253 | j_mayer | #endif
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250 | 76a66253 | j_mayer | /* Invalidate all defined software TLB */
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251 | 76a66253 | j_mayer | max = env->nb_tlb; |
252 | 76a66253 | j_mayer | if (env->id_tlbs == 1) |
253 | 76a66253 | j_mayer | max *= 2;
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254 | 76a66253 | j_mayer | for (nr = 0; nr < max; nr++) { |
255 | 1d0a48fb | j_mayer | tlb = &env->tlb[nr].tlb6; |
256 | 76a66253 | j_mayer | #if !defined(FLUSH_ALL_TLBS)
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257 | 76a66253 | j_mayer | tlb_flush_page(env, tlb->EPN); |
258 | 76a66253 | j_mayer | #endif
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259 | 76a66253 | j_mayer | pte_invalidate(&tlb->pte0); |
260 | 76a66253 | j_mayer | } |
261 | 76a66253 | j_mayer | #if defined(FLUSH_ALL_TLBS)
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262 | 76a66253 | j_mayer | tlb_flush(env, 1);
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263 | 76a66253 | j_mayer | #endif
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264 | 76a66253 | j_mayer | } |
265 | 76a66253 | j_mayer | |
266 | 76a66253 | j_mayer | static inline void __ppc6xx_tlb_invalidate_virt (CPUState *env, |
267 | 76a66253 | j_mayer | target_ulong eaddr, |
268 | 76a66253 | j_mayer | int is_code, int match_epn) |
269 | 76a66253 | j_mayer | { |
270 | 4a057712 | j_mayer | #if !defined(FLUSH_ALL_TLBS)
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271 | 1d0a48fb | j_mayer | ppc6xx_tlb_t *tlb; |
272 | 76a66253 | j_mayer | int way, nr;
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273 | 76a66253 | j_mayer | |
274 | 76a66253 | j_mayer | /* Invalidate ITLB + DTLB, all ways */
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275 | 76a66253 | j_mayer | for (way = 0; way < env->nb_ways; way++) { |
276 | 76a66253 | j_mayer | nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code); |
277 | 1d0a48fb | j_mayer | tlb = &env->tlb[nr].tlb6; |
278 | 76a66253 | j_mayer | if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) { |
279 | 76a66253 | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
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280 | 76a66253 | j_mayer | if (loglevel != 0) { |
281 | 1b9eb036 | j_mayer | fprintf(logfile, "TLB invalidate %d/%d " ADDRX "\n", |
282 | 76a66253 | j_mayer | nr, env->nb_tlb, eaddr); |
283 | 76a66253 | j_mayer | } |
284 | 76a66253 | j_mayer | #endif
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285 | 76a66253 | j_mayer | pte_invalidate(&tlb->pte0); |
286 | 76a66253 | j_mayer | tlb_flush_page(env, tlb->EPN); |
287 | 76a66253 | j_mayer | } |
288 | 76a66253 | j_mayer | } |
289 | 76a66253 | j_mayer | #else
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290 | 76a66253 | j_mayer | /* XXX: PowerPC specification say this is valid as well */
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291 | 76a66253 | j_mayer | ppc6xx_tlb_invalidate_all(env); |
292 | 76a66253 | j_mayer | #endif
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293 | 76a66253 | j_mayer | } |
294 | 76a66253 | j_mayer | |
295 | 76a66253 | j_mayer | void ppc6xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,
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296 | 76a66253 | j_mayer | int is_code)
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297 | 76a66253 | j_mayer | { |
298 | 76a66253 | j_mayer | __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
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299 | 76a66253 | j_mayer | } |
300 | 76a66253 | j_mayer | |
301 | 76a66253 | j_mayer | void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code, |
302 | 76a66253 | j_mayer | target_ulong pte0, target_ulong pte1) |
303 | 76a66253 | j_mayer | { |
304 | 1d0a48fb | j_mayer | ppc6xx_tlb_t *tlb; |
305 | 76a66253 | j_mayer | int nr;
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306 | 76a66253 | j_mayer | |
307 | 76a66253 | j_mayer | nr = ppc6xx_tlb_getnum(env, EPN, way, is_code); |
308 | 1d0a48fb | j_mayer | tlb = &env->tlb[nr].tlb6; |
309 | 76a66253 | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
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310 | 76a66253 | j_mayer | if (loglevel != 0) { |
311 | 5fafdf24 | ths | fprintf(logfile, "Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX |
312 | 1b9eb036 | j_mayer | " PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1); |
313 | 76a66253 | j_mayer | } |
314 | 76a66253 | j_mayer | #endif
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315 | 76a66253 | j_mayer | /* Invalidate any pending reference in Qemu for this virtual address */
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316 | 76a66253 | j_mayer | __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
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317 | 76a66253 | j_mayer | tlb->pte0 = pte0; |
318 | 76a66253 | j_mayer | tlb->pte1 = pte1; |
319 | 76a66253 | j_mayer | tlb->EPN = EPN; |
320 | 76a66253 | j_mayer | /* Store last way for LRU mechanism */
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321 | 76a66253 | j_mayer | env->last_way = way; |
322 | 76a66253 | j_mayer | } |
323 | 76a66253 | j_mayer | |
324 | 76a66253 | j_mayer | static int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx, |
325 | 76a66253 | j_mayer | target_ulong eaddr, int rw, int access_type) |
326 | 76a66253 | j_mayer | { |
327 | 1d0a48fb | j_mayer | ppc6xx_tlb_t *tlb; |
328 | 76a66253 | j_mayer | int nr, best, way;
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329 | 76a66253 | j_mayer | int ret;
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330 | d9bce9d9 | j_mayer | |
331 | 76a66253 | j_mayer | best = -1;
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332 | 76a66253 | j_mayer | ret = -1; /* No TLB found */ |
333 | 76a66253 | j_mayer | for (way = 0; way < env->nb_ways; way++) { |
334 | 76a66253 | j_mayer | nr = ppc6xx_tlb_getnum(env, eaddr, way, |
335 | 76a66253 | j_mayer | access_type == ACCESS_CODE ? 1 : 0); |
336 | 1d0a48fb | j_mayer | tlb = &env->tlb[nr].tlb6; |
337 | 76a66253 | j_mayer | /* This test "emulates" the PTE index match for hardware TLBs */
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338 | 76a66253 | j_mayer | if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
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339 | 76a66253 | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
|
340 | 76a66253 | j_mayer | if (loglevel != 0) { |
341 | 1b9eb036 | j_mayer | fprintf(logfile, "TLB %d/%d %s [" ADDRX " " ADDRX |
342 | 1b9eb036 | j_mayer | "] <> " ADDRX "\n", |
343 | 76a66253 | j_mayer | nr, env->nb_tlb, |
344 | 76a66253 | j_mayer | pte_is_valid(tlb->pte0) ? "valid" : "inval", |
345 | 76a66253 | j_mayer | tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr); |
346 | 76a66253 | j_mayer | } |
347 | 76a66253 | j_mayer | #endif
|
348 | 76a66253 | j_mayer | continue;
|
349 | 76a66253 | j_mayer | } |
350 | 76a66253 | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
|
351 | 76a66253 | j_mayer | if (loglevel != 0) { |
352 | 1b9eb036 | j_mayer | fprintf(logfile, "TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX |
353 | 1b9eb036 | j_mayer | " %c %c\n",
|
354 | 76a66253 | j_mayer | nr, env->nb_tlb, |
355 | 76a66253 | j_mayer | pte_is_valid(tlb->pte0) ? "valid" : "inval", |
356 | 76a66253 | j_mayer | tlb->EPN, eaddr, tlb->pte1, |
357 | 76a66253 | j_mayer | rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D'); |
358 | 76a66253 | j_mayer | } |
359 | 76a66253 | j_mayer | #endif
|
360 | caa4039c | j_mayer | switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw)) { |
361 | 76a66253 | j_mayer | case -3: |
362 | 76a66253 | j_mayer | /* TLB inconsistency */
|
363 | 76a66253 | j_mayer | return -1; |
364 | 76a66253 | j_mayer | case -2: |
365 | 76a66253 | j_mayer | /* Access violation */
|
366 | 76a66253 | j_mayer | ret = -2;
|
367 | 76a66253 | j_mayer | best = nr; |
368 | 76a66253 | j_mayer | break;
|
369 | 76a66253 | j_mayer | case -1: |
370 | 76a66253 | j_mayer | default:
|
371 | 76a66253 | j_mayer | /* No match */
|
372 | 76a66253 | j_mayer | break;
|
373 | 76a66253 | j_mayer | case 0: |
374 | 76a66253 | j_mayer | /* access granted */
|
375 | 76a66253 | j_mayer | /* XXX: we should go on looping to check all TLBs consistency
|
376 | 76a66253 | j_mayer | * but we can speed-up the whole thing as the
|
377 | 76a66253 | j_mayer | * result would be undefined if TLBs are not consistent.
|
378 | 76a66253 | j_mayer | */
|
379 | 76a66253 | j_mayer | ret = 0;
|
380 | 76a66253 | j_mayer | best = nr; |
381 | 76a66253 | j_mayer | goto done;
|
382 | 76a66253 | j_mayer | } |
383 | 76a66253 | j_mayer | } |
384 | 76a66253 | j_mayer | if (best != -1) { |
385 | 76a66253 | j_mayer | done:
|
386 | 76a66253 | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
|
387 | 4a057712 | j_mayer | if (loglevel != 0) { |
388 | 76a66253 | j_mayer | fprintf(logfile, "found TLB at addr 0x%08lx prot=0x%01x ret=%d\n",
|
389 | 76a66253 | j_mayer | ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret); |
390 | 76a66253 | j_mayer | } |
391 | 76a66253 | j_mayer | #endif
|
392 | 76a66253 | j_mayer | /* Update page flags */
|
393 | 1d0a48fb | j_mayer | pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw); |
394 | 76a66253 | j_mayer | } |
395 | 76a66253 | j_mayer | |
396 | 76a66253 | j_mayer | return ret;
|
397 | 76a66253 | j_mayer | } |
398 | 76a66253 | j_mayer | |
399 | 9a64fbe4 | bellard | /* Perform BAT hit & translation */
|
400 | 76a66253 | j_mayer | static int get_bat (CPUState *env, mmu_ctx_t *ctx, |
401 | 76a66253 | j_mayer | target_ulong virtual, int rw, int type) |
402 | 9a64fbe4 | bellard | { |
403 | 76a66253 | j_mayer | target_ulong *BATlt, *BATut, *BATu, *BATl; |
404 | 76a66253 | j_mayer | target_ulong base, BEPIl, BEPIu, bl; |
405 | 9a64fbe4 | bellard | int i;
|
406 | 9a64fbe4 | bellard | int ret = -1; |
407 | 9a64fbe4 | bellard | |
408 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
|
409 | 4a057712 | j_mayer | if (loglevel != 0) { |
410 | 1b9eb036 | j_mayer | fprintf(logfile, "%s: %cBAT v 0x" ADDRX "\n", __func__, |
411 | 76a66253 | j_mayer | type == ACCESS_CODE ? 'I' : 'D', virtual); |
412 | 9a64fbe4 | bellard | } |
413 | 9a64fbe4 | bellard | #endif
|
414 | 9a64fbe4 | bellard | switch (type) {
|
415 | 9a64fbe4 | bellard | case ACCESS_CODE:
|
416 | 9a64fbe4 | bellard | BATlt = env->IBAT[1];
|
417 | 9a64fbe4 | bellard | BATut = env->IBAT[0];
|
418 | 9a64fbe4 | bellard | break;
|
419 | 9a64fbe4 | bellard | default:
|
420 | 9a64fbe4 | bellard | BATlt = env->DBAT[1];
|
421 | 9a64fbe4 | bellard | BATut = env->DBAT[0];
|
422 | 9a64fbe4 | bellard | break;
|
423 | 9a64fbe4 | bellard | } |
424 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
|
425 | 4a057712 | j_mayer | if (loglevel != 0) { |
426 | 1b9eb036 | j_mayer | fprintf(logfile, "%s...: %cBAT v 0x" ADDRX "\n", __func__, |
427 | 76a66253 | j_mayer | type == ACCESS_CODE ? 'I' : 'D', virtual); |
428 | 9a64fbe4 | bellard | } |
429 | 9a64fbe4 | bellard | #endif
|
430 | 9a64fbe4 | bellard | base = virtual & 0xFFFC0000;
|
431 | 9a64fbe4 | bellard | for (i = 0; i < 4; i++) { |
432 | 9a64fbe4 | bellard | BATu = &BATut[i]; |
433 | 9a64fbe4 | bellard | BATl = &BATlt[i]; |
434 | 9a64fbe4 | bellard | BEPIu = *BATu & 0xF0000000;
|
435 | 9a64fbe4 | bellard | BEPIl = *BATu & 0x0FFE0000;
|
436 | 9a64fbe4 | bellard | bl = (*BATu & 0x00001FFC) << 15; |
437 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
|
438 | 4a057712 | j_mayer | if (loglevel != 0) { |
439 | 5fafdf24 | ths | fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX |
440 | 1b9eb036 | j_mayer | " BATl 0x" ADDRX "\n", |
441 | 9a64fbe4 | bellard | __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, |
442 | 9a64fbe4 | bellard | *BATu, *BATl); |
443 | 9a64fbe4 | bellard | } |
444 | 9a64fbe4 | bellard | #endif
|
445 | 9a64fbe4 | bellard | if ((virtual & 0xF0000000) == BEPIu && |
446 | 9a64fbe4 | bellard | ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
|
447 | 9a64fbe4 | bellard | /* BAT matches */
|
448 | 9a64fbe4 | bellard | if ((msr_pr == 0 && (*BATu & 0x00000002)) || |
449 | 9a64fbe4 | bellard | (msr_pr == 1 && (*BATu & 0x00000001))) { |
450 | 9a64fbe4 | bellard | /* Get physical address */
|
451 | 76a66253 | j_mayer | ctx->raddr = (*BATl & 0xF0000000) |
|
452 | 9a64fbe4 | bellard | ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) | |
453 | a541f297 | bellard | (virtual & 0x0001F000);
|
454 | 9a64fbe4 | bellard | if (*BATl & 0x00000001) |
455 | 76a66253 | j_mayer | ctx->prot = PAGE_READ; |
456 | 9a64fbe4 | bellard | if (*BATl & 0x00000002) |
457 | 76a66253 | j_mayer | ctx->prot = PAGE_WRITE | PAGE_READ; |
458 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
|
459 | 4a057712 | j_mayer | if (loglevel != 0) { |
460 | 4a057712 | j_mayer | fprintf(logfile, "BAT %d match: r 0x" PADDRX
|
461 | 1b9eb036 | j_mayer | " prot=%c%c\n",
|
462 | 76a66253 | j_mayer | i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-', |
463 | 76a66253 | j_mayer | ctx->prot & PAGE_WRITE ? 'W' : '-'); |
464 | 9a64fbe4 | bellard | } |
465 | 9a64fbe4 | bellard | #endif
|
466 | 9a64fbe4 | bellard | ret = 0;
|
467 | 9a64fbe4 | bellard | break;
|
468 | 9a64fbe4 | bellard | } |
469 | 9a64fbe4 | bellard | } |
470 | 9a64fbe4 | bellard | } |
471 | 9a64fbe4 | bellard | if (ret < 0) { |
472 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
|
473 | 4a057712 | j_mayer | if (loglevel != 0) { |
474 | 4a057712 | j_mayer | fprintf(logfile, "no BAT match for 0x" ADDRX ":\n", virtual); |
475 | 4a057712 | j_mayer | for (i = 0; i < 4; i++) { |
476 | 4a057712 | j_mayer | BATu = &BATut[i]; |
477 | 4a057712 | j_mayer | BATl = &BATlt[i]; |
478 | 4a057712 | j_mayer | BEPIu = *BATu & 0xF0000000;
|
479 | 4a057712 | j_mayer | BEPIl = *BATu & 0x0FFE0000;
|
480 | 4a057712 | j_mayer | bl = (*BATu & 0x00001FFC) << 15; |
481 | 4a057712 | j_mayer | fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX |
482 | 4a057712 | j_mayer | " BATl 0x" ADDRX " \n\t" |
483 | 4a057712 | j_mayer | "0x" ADDRX " 0x" ADDRX " 0x" ADDRX "\n", |
484 | 4a057712 | j_mayer | __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, |
485 | 4a057712 | j_mayer | *BATu, *BATl, BEPIu, BEPIl, bl); |
486 | 4a057712 | j_mayer | } |
487 | 9a64fbe4 | bellard | } |
488 | 9a64fbe4 | bellard | #endif
|
489 | 9a64fbe4 | bellard | } |
490 | 9a64fbe4 | bellard | /* No hit */
|
491 | 9a64fbe4 | bellard | return ret;
|
492 | 9a64fbe4 | bellard | } |
493 | 9a64fbe4 | bellard | |
494 | 9a64fbe4 | bellard | /* PTE table lookup */
|
495 | caa4039c | j_mayer | static inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h, int rw) |
496 | 9a64fbe4 | bellard | { |
497 | 76a66253 | j_mayer | target_ulong base, pte0, pte1; |
498 | 76a66253 | j_mayer | int i, good = -1; |
499 | caa4039c | j_mayer | int ret, r;
|
500 | 9a64fbe4 | bellard | |
501 | 76a66253 | j_mayer | ret = -1; /* No entry found */ |
502 | 76a66253 | j_mayer | base = ctx->pg_addr[h]; |
503 | 9a64fbe4 | bellard | for (i = 0; i < 8; i++) { |
504 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
505 | caa4039c | j_mayer | if (is_64b) {
|
506 | caa4039c | j_mayer | pte0 = ldq_phys(base + (i * 16));
|
507 | caa4039c | j_mayer | pte1 = ldq_phys(base + (i * 16) + 8); |
508 | caa4039c | j_mayer | r = pte64_check(ctx, pte0, pte1, h, rw); |
509 | caa4039c | j_mayer | } else
|
510 | caa4039c | j_mayer | #endif
|
511 | caa4039c | j_mayer | { |
512 | caa4039c | j_mayer | pte0 = ldl_phys(base + (i * 8));
|
513 | caa4039c | j_mayer | pte1 = ldl_phys(base + (i * 8) + 4); |
514 | caa4039c | j_mayer | r = pte32_check(ctx, pte0, pte1, h, rw); |
515 | caa4039c | j_mayer | } |
516 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
517 | caa4039c | j_mayer | if (loglevel != 0) { |
518 | 5fafdf24 | ths | fprintf(logfile, "Load pte from 0x" ADDRX " => 0x" ADDRX |
519 | 1b9eb036 | j_mayer | " 0x" ADDRX " %d %d %d 0x" ADDRX "\n", |
520 | 1b9eb036 | j_mayer | base + (i * 8), pte0, pte1,
|
521 | caa4039c | j_mayer | (int)(pte0 >> 31), h, (int)((pte0 >> 6) & 1), ctx->ptem); |
522 | 76a66253 | j_mayer | } |
523 | 9a64fbe4 | bellard | #endif
|
524 | caa4039c | j_mayer | switch (r) {
|
525 | 76a66253 | j_mayer | case -3: |
526 | 76a66253 | j_mayer | /* PTE inconsistency */
|
527 | 76a66253 | j_mayer | return -1; |
528 | 76a66253 | j_mayer | case -2: |
529 | 76a66253 | j_mayer | /* Access violation */
|
530 | 76a66253 | j_mayer | ret = -2;
|
531 | 76a66253 | j_mayer | good = i; |
532 | 76a66253 | j_mayer | break;
|
533 | 76a66253 | j_mayer | case -1: |
534 | 76a66253 | j_mayer | default:
|
535 | 76a66253 | j_mayer | /* No PTE match */
|
536 | 76a66253 | j_mayer | break;
|
537 | 76a66253 | j_mayer | case 0: |
538 | 76a66253 | j_mayer | /* access granted */
|
539 | 76a66253 | j_mayer | /* XXX: we should go on looping to check all PTEs consistency
|
540 | 76a66253 | j_mayer | * but if we can speed-up the whole thing as the
|
541 | 76a66253 | j_mayer | * result would be undefined if PTEs are not consistent.
|
542 | 76a66253 | j_mayer | */
|
543 | 76a66253 | j_mayer | ret = 0;
|
544 | 76a66253 | j_mayer | good = i; |
545 | 76a66253 | j_mayer | goto done;
|
546 | 9a64fbe4 | bellard | } |
547 | 9a64fbe4 | bellard | } |
548 | 9a64fbe4 | bellard | if (good != -1) { |
549 | 76a66253 | j_mayer | done:
|
550 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
551 | 4a057712 | j_mayer | if (loglevel != 0) { |
552 | 4a057712 | j_mayer | fprintf(logfile, "found PTE at addr 0x" PADDRX " prot=0x%01x " |
553 | 1b9eb036 | j_mayer | "ret=%d\n",
|
554 | 76a66253 | j_mayer | ctx->raddr, ctx->prot, ret); |
555 | 76a66253 | j_mayer | } |
556 | 9a64fbe4 | bellard | #endif
|
557 | 9a64fbe4 | bellard | /* Update page flags */
|
558 | 76a66253 | j_mayer | pte1 = ctx->raddr; |
559 | caa4039c | j_mayer | if (pte_update_flags(ctx, &pte1, ret, rw) == 1) { |
560 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
561 | caa4039c | j_mayer | if (is_64b) {
|
562 | caa4039c | j_mayer | stq_phys_notdirty(base + (good * 16) + 8, pte1); |
563 | caa4039c | j_mayer | } else
|
564 | caa4039c | j_mayer | #endif
|
565 | caa4039c | j_mayer | { |
566 | caa4039c | j_mayer | stl_phys_notdirty(base + (good * 8) + 4, pte1); |
567 | caa4039c | j_mayer | } |
568 | caa4039c | j_mayer | } |
569 | 9a64fbe4 | bellard | } |
570 | 9a64fbe4 | bellard | |
571 | 9a64fbe4 | bellard | return ret;
|
572 | 79aceca5 | bellard | } |
573 | 79aceca5 | bellard | |
574 | caa4039c | j_mayer | static int find_pte32 (mmu_ctx_t *ctx, int h, int rw) |
575 | caa4039c | j_mayer | { |
576 | caa4039c | j_mayer | return _find_pte(ctx, 0, h, rw); |
577 | caa4039c | j_mayer | } |
578 | caa4039c | j_mayer | |
579 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
580 | caa4039c | j_mayer | static int find_pte64 (mmu_ctx_t *ctx, int h, int rw) |
581 | caa4039c | j_mayer | { |
582 | caa4039c | j_mayer | return _find_pte(ctx, 1, h, rw); |
583 | caa4039c | j_mayer | } |
584 | caa4039c | j_mayer | #endif
|
585 | caa4039c | j_mayer | |
586 | caa4039c | j_mayer | static inline int find_pte (CPUState *env, mmu_ctx_t *ctx, int h, int rw) |
587 | caa4039c | j_mayer | { |
588 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
589 | a750fc0b | j_mayer | if (env->mmu_model == POWERPC_MMU_64B ||
|
590 | a750fc0b | j_mayer | env->mmu_model == POWERPC_MMU_64BRIDGE) |
591 | caa4039c | j_mayer | return find_pte64(ctx, h, rw);
|
592 | caa4039c | j_mayer | #endif
|
593 | caa4039c | j_mayer | |
594 | caa4039c | j_mayer | return find_pte32(ctx, h, rw);
|
595 | caa4039c | j_mayer | } |
596 | caa4039c | j_mayer | |
597 | 76a66253 | j_mayer | static inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1, |
598 | caa4039c | j_mayer | int sdr_sh,
|
599 | 76a66253 | j_mayer | target_phys_addr_t hash, |
600 | 76a66253 | j_mayer | target_phys_addr_t mask) |
601 | 79aceca5 | bellard | { |
602 | caa4039c | j_mayer | return (sdr1 & ((target_ulong)(-1ULL) << sdr_sh)) | (hash & mask); |
603 | caa4039c | j_mayer | } |
604 | caa4039c | j_mayer | |
605 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
606 | caa4039c | j_mayer | static int slb_lookup (CPUState *env, target_ulong eaddr, |
607 | caa4039c | j_mayer | target_ulong *vsid, target_ulong *page_mask, int *attr)
|
608 | caa4039c | j_mayer | { |
609 | caa4039c | j_mayer | target_phys_addr_t sr_base; |
610 | caa4039c | j_mayer | target_ulong mask; |
611 | caa4039c | j_mayer | uint64_t tmp64; |
612 | caa4039c | j_mayer | uint32_t tmp; |
613 | caa4039c | j_mayer | int n, ret;
|
614 | caa4039c | j_mayer | int slb_nr;
|
615 | caa4039c | j_mayer | |
616 | caa4039c | j_mayer | ret = -5;
|
617 | caa4039c | j_mayer | sr_base = env->spr[SPR_ASR]; |
618 | caa4039c | j_mayer | mask = 0x0000000000000000ULL; /* Avoid gcc warning */ |
619 | caa4039c | j_mayer | #if 0 /* XXX: Fix this */
|
620 | caa4039c | j_mayer | slb_nr = env->slb_nr;
|
621 | caa4039c | j_mayer | #else
|
622 | caa4039c | j_mayer | slb_nr = 32;
|
623 | caa4039c | j_mayer | #endif
|
624 | caa4039c | j_mayer | for (n = 0; n < slb_nr; n++) { |
625 | caa4039c | j_mayer | tmp64 = ldq_phys(sr_base); |
626 | caa4039c | j_mayer | if (tmp64 & 0x0000000008000000ULL) { |
627 | caa4039c | j_mayer | /* SLB entry is valid */
|
628 | caa4039c | j_mayer | switch (tmp64 & 0x0000000006000000ULL) { |
629 | caa4039c | j_mayer | case 0x0000000000000000ULL: |
630 | caa4039c | j_mayer | /* 256 MB segment */
|
631 | caa4039c | j_mayer | mask = 0xFFFFFFFFF0000000ULL;
|
632 | caa4039c | j_mayer | break;
|
633 | caa4039c | j_mayer | case 0x0000000002000000ULL: |
634 | caa4039c | j_mayer | /* 1 TB segment */
|
635 | caa4039c | j_mayer | mask = 0xFFFF000000000000ULL;
|
636 | caa4039c | j_mayer | break;
|
637 | caa4039c | j_mayer | case 0x0000000004000000ULL: |
638 | caa4039c | j_mayer | case 0x0000000006000000ULL: |
639 | caa4039c | j_mayer | /* Reserved => segment is invalid */
|
640 | caa4039c | j_mayer | continue;
|
641 | caa4039c | j_mayer | } |
642 | caa4039c | j_mayer | if ((eaddr & mask) == (tmp64 & mask)) {
|
643 | caa4039c | j_mayer | /* SLB match */
|
644 | caa4039c | j_mayer | tmp = ldl_phys(sr_base + 8);
|
645 | caa4039c | j_mayer | *vsid = ((tmp64 << 24) | (tmp >> 8)) & 0x0003FFFFFFFFFFFFULL; |
646 | caa4039c | j_mayer | *page_mask = ~mask; |
647 | caa4039c | j_mayer | *attr = tmp & 0xFF;
|
648 | caa4039c | j_mayer | ret = 0;
|
649 | caa4039c | j_mayer | break;
|
650 | caa4039c | j_mayer | } |
651 | caa4039c | j_mayer | } |
652 | caa4039c | j_mayer | sr_base += 12;
|
653 | caa4039c | j_mayer | } |
654 | caa4039c | j_mayer | |
655 | caa4039c | j_mayer | return ret;
|
656 | 79aceca5 | bellard | } |
657 | caa4039c | j_mayer | #endif /* defined(TARGET_PPC64) */ |
658 | 79aceca5 | bellard | |
659 | 9a64fbe4 | bellard | /* Perform segment based translation */
|
660 | 76a66253 | j_mayer | static int get_segment (CPUState *env, mmu_ctx_t *ctx, |
661 | 76a66253 | j_mayer | target_ulong eaddr, int rw, int type) |
662 | 79aceca5 | bellard | { |
663 | caa4039c | j_mayer | target_phys_addr_t sdr, hash, mask, sdr_mask; |
664 | caa4039c | j_mayer | target_ulong sr, vsid, vsid_mask, pgidx, page_mask; |
665 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
666 | caa4039c | j_mayer | int attr;
|
667 | 9a64fbe4 | bellard | #endif
|
668 | caa4039c | j_mayer | int ds, nx, vsid_sh, sdr_sh;
|
669 | caa4039c | j_mayer | int ret, ret2;
|
670 | caa4039c | j_mayer | |
671 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
672 | a750fc0b | j_mayer | if (env->mmu_model == POWERPC_MMU_64B) {
|
673 | caa4039c | j_mayer | ret = slb_lookup(env, eaddr, &vsid, &page_mask, &attr); |
674 | caa4039c | j_mayer | if (ret < 0) |
675 | caa4039c | j_mayer | return ret;
|
676 | caa4039c | j_mayer | ctx->key = ((attr & 0x40) && msr_pr == 1) || |
677 | caa4039c | j_mayer | ((attr & 0x80) && msr_pr == 0) ? 1 : 0; |
678 | caa4039c | j_mayer | ds = 0;
|
679 | caa4039c | j_mayer | nx = attr & 0x20 ? 1 : 0; |
680 | caa4039c | j_mayer | vsid_mask = 0x00003FFFFFFFFF80ULL;
|
681 | caa4039c | j_mayer | vsid_sh = 7;
|
682 | caa4039c | j_mayer | sdr_sh = 18;
|
683 | caa4039c | j_mayer | sdr_mask = 0x3FF80;
|
684 | caa4039c | j_mayer | } else
|
685 | caa4039c | j_mayer | #endif /* defined(TARGET_PPC64) */ |
686 | caa4039c | j_mayer | { |
687 | caa4039c | j_mayer | sr = env->sr[eaddr >> 28];
|
688 | caa4039c | j_mayer | page_mask = 0x0FFFFFFF;
|
689 | caa4039c | j_mayer | ctx->key = (((sr & 0x20000000) && msr_pr == 1) || |
690 | caa4039c | j_mayer | ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0; |
691 | caa4039c | j_mayer | ds = sr & 0x80000000 ? 1 : 0; |
692 | caa4039c | j_mayer | nx = sr & 0x10000000 ? 1 : 0; |
693 | caa4039c | j_mayer | vsid = sr & 0x00FFFFFF;
|
694 | caa4039c | j_mayer | vsid_mask = 0x01FFFFC0;
|
695 | caa4039c | j_mayer | vsid_sh = 6;
|
696 | caa4039c | j_mayer | sdr_sh = 16;
|
697 | caa4039c | j_mayer | sdr_mask = 0xFFC0;
|
698 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
699 | caa4039c | j_mayer | if (loglevel != 0) { |
700 | caa4039c | j_mayer | fprintf(logfile, "Check segment v=0x" ADDRX " %d 0x" ADDRX |
701 | caa4039c | j_mayer | " nip=0x" ADDRX " lr=0x" ADDRX |
702 | caa4039c | j_mayer | " ir=%d dr=%d pr=%d %d t=%d\n",
|
703 | caa4039c | j_mayer | eaddr, (int)(eaddr >> 28), sr, env->nip, |
704 | caa4039c | j_mayer | env->lr, msr_ir, msr_dr, msr_pr, rw, type); |
705 | caa4039c | j_mayer | } |
706 | caa4039c | j_mayer | if (!ds && loglevel != 0) { |
707 | 1b9eb036 | j_mayer | fprintf(logfile, "pte segment: key=%d n=0x" ADDRX "\n", |
708 | 76a66253 | j_mayer | ctx->key, sr & 0x10000000);
|
709 | caa4039c | j_mayer | } |
710 | 9a64fbe4 | bellard | #endif
|
711 | caa4039c | j_mayer | } |
712 | caa4039c | j_mayer | ret = -1;
|
713 | caa4039c | j_mayer | if (!ds) {
|
714 | 9a64fbe4 | bellard | /* Check if instruction fetch is allowed, if needed */
|
715 | caa4039c | j_mayer | if (type != ACCESS_CODE || nx == 0) { |
716 | 9a64fbe4 | bellard | /* Page address translation */
|
717 | caa4039c | j_mayer | pgidx = (eaddr & page_mask) >> TARGET_PAGE_BITS; |
718 | caa4039c | j_mayer | hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask; |
719 | 76a66253 | j_mayer | /* Primary table address */
|
720 | 76a66253 | j_mayer | sdr = env->sdr1; |
721 | caa4039c | j_mayer | mask = ((sdr & 0x000001FF) << sdr_sh) | sdr_mask;
|
722 | caa4039c | j_mayer | ctx->pg_addr[0] = get_pgaddr(sdr, sdr_sh, hash, mask);
|
723 | 76a66253 | j_mayer | /* Secondary table address */
|
724 | caa4039c | j_mayer | hash = (~hash) & vsid_mask; |
725 | caa4039c | j_mayer | ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask);
|
726 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
727 | a750fc0b | j_mayer | if (env->mmu_model == POWERPC_MMU_64B ||
|
728 | a750fc0b | j_mayer | env->mmu_model == POWERPC_MMU_64BRIDGE) { |
729 | caa4039c | j_mayer | /* Only 5 bits of the page index are used in the AVPN */
|
730 | caa4039c | j_mayer | ctx->ptem = (vsid << 12) | ((pgidx >> 4) & 0x0F80); |
731 | caa4039c | j_mayer | } else
|
732 | caa4039c | j_mayer | #endif
|
733 | caa4039c | j_mayer | { |
734 | caa4039c | j_mayer | ctx->ptem = (vsid << 7) | (pgidx >> 10); |
735 | caa4039c | j_mayer | } |
736 | 76a66253 | j_mayer | /* Initialize real address with an invalid value */
|
737 | 76a66253 | j_mayer | ctx->raddr = (target_ulong)-1;
|
738 | a750fc0b | j_mayer | if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx)) {
|
739 | 76a66253 | j_mayer | /* Software TLB search */
|
740 | 76a66253 | j_mayer | ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type); |
741 | 76a66253 | j_mayer | } else {
|
742 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
743 | 4a057712 | j_mayer | if (loglevel != 0) { |
744 | 4a057712 | j_mayer | fprintf(logfile, "0 sdr1=0x" PADDRX " vsid=0x%06x " |
745 | 4a057712 | j_mayer | "api=0x%04x hash=0x%07x pg_addr=0x" PADDRX "\n", |
746 | 4a057712 | j_mayer | sdr, (uint32_t)vsid, (uint32_t)pgidx, |
747 | 4a057712 | j_mayer | (uint32_t)hash, ctx->pg_addr[0]);
|
748 | 76a66253 | j_mayer | } |
749 | 9a64fbe4 | bellard | #endif
|
750 | 76a66253 | j_mayer | /* Primary table lookup */
|
751 | caa4039c | j_mayer | ret = find_pte(env, ctx, 0, rw);
|
752 | 76a66253 | j_mayer | if (ret < 0) { |
753 | 76a66253 | j_mayer | /* Secondary table lookup */
|
754 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
755 | 4a057712 | j_mayer | if (eaddr != 0xEFFFFFFF && loglevel != 0) { |
756 | 76a66253 | j_mayer | fprintf(logfile, |
757 | 4a057712 | j_mayer | "1 sdr1=0x" PADDRX " vsid=0x%06x api=0x%04x " |
758 | 4a057712 | j_mayer | "hash=0x%05x pg_addr=0x" PADDRX "\n", |
759 | 4a057712 | j_mayer | sdr, (uint32_t)vsid, (uint32_t)pgidx, |
760 | 4a057712 | j_mayer | (uint32_t)hash, ctx->pg_addr[1]);
|
761 | 76a66253 | j_mayer | } |
762 | 9a64fbe4 | bellard | #endif
|
763 | caa4039c | j_mayer | ret2 = find_pte(env, ctx, 1, rw);
|
764 | 76a66253 | j_mayer | if (ret2 != -1) |
765 | 76a66253 | j_mayer | ret = ret2; |
766 | 76a66253 | j_mayer | } |
767 | 9a64fbe4 | bellard | } |
768 | 9a64fbe4 | bellard | } else {
|
769 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
770 | 4a057712 | j_mayer | if (loglevel != 0) |
771 | 76a66253 | j_mayer | fprintf(logfile, "No access allowed\n");
|
772 | 9a64fbe4 | bellard | #endif
|
773 | 76a66253 | j_mayer | ret = -3;
|
774 | 9a64fbe4 | bellard | } |
775 | 9a64fbe4 | bellard | } else {
|
776 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
777 | 4a057712 | j_mayer | if (loglevel != 0) |
778 | 76a66253 | j_mayer | fprintf(logfile, "direct store...\n");
|
779 | 9a64fbe4 | bellard | #endif
|
780 | 9a64fbe4 | bellard | /* Direct-store segment : absolutely *BUGGY* for now */
|
781 | 9a64fbe4 | bellard | switch (type) {
|
782 | 9a64fbe4 | bellard | case ACCESS_INT:
|
783 | 9a64fbe4 | bellard | /* Integer load/store : only access allowed */
|
784 | 9a64fbe4 | bellard | break;
|
785 | 9a64fbe4 | bellard | case ACCESS_CODE:
|
786 | 9a64fbe4 | bellard | /* No code fetch is allowed in direct-store areas */
|
787 | 9a64fbe4 | bellard | return -4; |
788 | 9a64fbe4 | bellard | case ACCESS_FLOAT:
|
789 | 9a64fbe4 | bellard | /* Floating point load/store */
|
790 | 9a64fbe4 | bellard | return -4; |
791 | 9a64fbe4 | bellard | case ACCESS_RES:
|
792 | 9a64fbe4 | bellard | /* lwarx, ldarx or srwcx. */
|
793 | 9a64fbe4 | bellard | return -4; |
794 | 9a64fbe4 | bellard | case ACCESS_CACHE:
|
795 | 9a64fbe4 | bellard | /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
|
796 | 9a64fbe4 | bellard | /* Should make the instruction do no-op.
|
797 | 9a64fbe4 | bellard | * As it already do no-op, it's quite easy :-)
|
798 | 9a64fbe4 | bellard | */
|
799 | 76a66253 | j_mayer | ctx->raddr = eaddr; |
800 | 9a64fbe4 | bellard | return 0; |
801 | 9a64fbe4 | bellard | case ACCESS_EXT:
|
802 | 9a64fbe4 | bellard | /* eciwx or ecowx */
|
803 | 9a64fbe4 | bellard | return -4; |
804 | 9a64fbe4 | bellard | default:
|
805 | 9a64fbe4 | bellard | if (logfile) {
|
806 | 9a64fbe4 | bellard | fprintf(logfile, "ERROR: instruction should not need "
|
807 | 9a64fbe4 | bellard | "address translation\n");
|
808 | 9a64fbe4 | bellard | } |
809 | 9a64fbe4 | bellard | return -4; |
810 | 9a64fbe4 | bellard | } |
811 | 76a66253 | j_mayer | if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) { |
812 | 76a66253 | j_mayer | ctx->raddr = eaddr; |
813 | 9a64fbe4 | bellard | ret = 2;
|
814 | 9a64fbe4 | bellard | } else {
|
815 | 9a64fbe4 | bellard | ret = -2;
|
816 | 9a64fbe4 | bellard | } |
817 | 79aceca5 | bellard | } |
818 | 9a64fbe4 | bellard | |
819 | 9a64fbe4 | bellard | return ret;
|
820 | 79aceca5 | bellard | } |
821 | 79aceca5 | bellard | |
822 | c294fc58 | j_mayer | /* Generic TLB check function for embedded PowerPC implementations */
|
823 | c294fc58 | j_mayer | static int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb, |
824 | c294fc58 | j_mayer | target_phys_addr_t *raddrp, |
825 | 36081602 | j_mayer | target_ulong address, |
826 | 36081602 | j_mayer | uint32_t pid, int ext, int i) |
827 | c294fc58 | j_mayer | { |
828 | c294fc58 | j_mayer | target_ulong mask; |
829 | c294fc58 | j_mayer | |
830 | c294fc58 | j_mayer | /* Check valid flag */
|
831 | c294fc58 | j_mayer | if (!(tlb->prot & PAGE_VALID)) {
|
832 | c294fc58 | j_mayer | if (loglevel != 0) |
833 | c294fc58 | j_mayer | fprintf(logfile, "%s: TLB %d not valid\n", __func__, i);
|
834 | c294fc58 | j_mayer | return -1; |
835 | c294fc58 | j_mayer | } |
836 | c294fc58 | j_mayer | mask = ~(tlb->size - 1);
|
837 | c294fc58 | j_mayer | if (loglevel != 0) { |
838 | c294fc58 | j_mayer | fprintf(logfile, "%s: TLB %d address " ADDRX " PID %d <=> " |
839 | c294fc58 | j_mayer | ADDRX " " ADDRX " %d\n", |
840 | 36081602 | j_mayer | __func__, i, address, pid, tlb->EPN, mask, (int)tlb->PID);
|
841 | c294fc58 | j_mayer | } |
842 | c294fc58 | j_mayer | /* Check PID */
|
843 | 36081602 | j_mayer | if (tlb->PID != 0 && tlb->PID != pid) |
844 | c294fc58 | j_mayer | return -1; |
845 | c294fc58 | j_mayer | /* Check effective address */
|
846 | c294fc58 | j_mayer | if ((address & mask) != tlb->EPN)
|
847 | c294fc58 | j_mayer | return -1; |
848 | c294fc58 | j_mayer | *raddrp = (tlb->RPN & mask) | (address & ~mask); |
849 | 9706285b | j_mayer | #if (TARGET_PHYS_ADDR_BITS >= 36) |
850 | 36081602 | j_mayer | if (ext) {
|
851 | 36081602 | j_mayer | /* Extend the physical address to 36 bits */
|
852 | 36081602 | j_mayer | *raddrp |= (target_phys_addr_t)(tlb->RPN & 0xF) << 32; |
853 | 36081602 | j_mayer | } |
854 | 9706285b | j_mayer | #endif
|
855 | c294fc58 | j_mayer | |
856 | c294fc58 | j_mayer | return 0; |
857 | c294fc58 | j_mayer | } |
858 | c294fc58 | j_mayer | |
859 | c294fc58 | j_mayer | /* Generic TLB search function for PowerPC embedded implementations */
|
860 | 36081602 | j_mayer | int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid)
|
861 | c294fc58 | j_mayer | { |
862 | c294fc58 | j_mayer | ppcemb_tlb_t *tlb; |
863 | c294fc58 | j_mayer | target_phys_addr_t raddr; |
864 | c294fc58 | j_mayer | int i, ret;
|
865 | c294fc58 | j_mayer | |
866 | c294fc58 | j_mayer | /* Default return value is no match */
|
867 | c294fc58 | j_mayer | ret = -1;
|
868 | a750fc0b | j_mayer | for (i = 0; i < env->nb_tlb; i++) { |
869 | c294fc58 | j_mayer | tlb = &env->tlb[i].tlbe; |
870 | 36081602 | j_mayer | if (ppcemb_tlb_check(env, tlb, &raddr, address, pid, 0, i) == 0) { |
871 | c294fc58 | j_mayer | ret = i; |
872 | c294fc58 | j_mayer | break;
|
873 | c294fc58 | j_mayer | } |
874 | c294fc58 | j_mayer | } |
875 | c294fc58 | j_mayer | |
876 | c294fc58 | j_mayer | return ret;
|
877 | c294fc58 | j_mayer | } |
878 | c294fc58 | j_mayer | |
879 | a750fc0b | j_mayer | void ppc4xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,
|
880 | a750fc0b | j_mayer | uint32_t pid) |
881 | a750fc0b | j_mayer | { |
882 | a750fc0b | j_mayer | ppcemb_tlb_t *tlb; |
883 | a750fc0b | j_mayer | target_phys_addr_t raddr; |
884 | a750fc0b | j_mayer | target_ulong page, end; |
885 | a750fc0b | j_mayer | int i;
|
886 | a750fc0b | j_mayer | |
887 | a750fc0b | j_mayer | for (i = 0; i < env->nb_tlb; i++) { |
888 | a750fc0b | j_mayer | tlb = &env->tlb[i].tlbe; |
889 | a750fc0b | j_mayer | if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) { |
890 | a750fc0b | j_mayer | end = tlb->EPN + tlb->size; |
891 | a750fc0b | j_mayer | for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
|
892 | a750fc0b | j_mayer | tlb_flush_page(env, page); |
893 | a750fc0b | j_mayer | tlb->prot &= ~PAGE_VALID; |
894 | a750fc0b | j_mayer | break;
|
895 | a750fc0b | j_mayer | } |
896 | a750fc0b | j_mayer | } |
897 | a750fc0b | j_mayer | } |
898 | a750fc0b | j_mayer | |
899 | c294fc58 | j_mayer | /* Helpers specific to PowerPC 40x implementations */
|
900 | 0a032cbe | j_mayer | void ppc4xx_tlb_invalidate_all (CPUState *env)
|
901 | 0a032cbe | j_mayer | { |
902 | 0a032cbe | j_mayer | ppcemb_tlb_t *tlb; |
903 | 0a032cbe | j_mayer | int i;
|
904 | 0a032cbe | j_mayer | |
905 | 0a032cbe | j_mayer | for (i = 0; i < env->nb_tlb; i++) { |
906 | 0a032cbe | j_mayer | tlb = &env->tlb[i].tlbe; |
907 | 0a032cbe | j_mayer | if (tlb->prot & PAGE_VALID) {
|
908 | 0a032cbe | j_mayer | #if 0 // XXX: TLB have variable sizes then we flush all Qemu TLB.
|
909 | 0a032cbe | j_mayer | end = tlb->EPN + tlb->size;
|
910 | 0a032cbe | j_mayer | for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
|
911 | 0a032cbe | j_mayer | tlb_flush_page(env, page);
|
912 | 0a032cbe | j_mayer | #endif
|
913 | 0a032cbe | j_mayer | tlb->prot &= ~PAGE_VALID; |
914 | 0a032cbe | j_mayer | } |
915 | 0a032cbe | j_mayer | } |
916 | 0a032cbe | j_mayer | tlb_flush(env, 1);
|
917 | 0a032cbe | j_mayer | } |
918 | 0a032cbe | j_mayer | |
919 | 36081602 | j_mayer | int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
|
920 | e96efcfc | j_mayer | target_ulong address, int rw, int access_type) |
921 | a8dea12f | j_mayer | { |
922 | a8dea12f | j_mayer | ppcemb_tlb_t *tlb; |
923 | a8dea12f | j_mayer | target_phys_addr_t raddr; |
924 | a8dea12f | j_mayer | int i, ret, zsel, zpr;
|
925 | 3b46e624 | ths | |
926 | c55e9aef | j_mayer | ret = -1;
|
927 | c55e9aef | j_mayer | raddr = -1;
|
928 | a8dea12f | j_mayer | for (i = 0; i < env->nb_tlb; i++) { |
929 | a8dea12f | j_mayer | tlb = &env->tlb[i].tlbe; |
930 | 36081602 | j_mayer | if (ppcemb_tlb_check(env, tlb, &raddr, address,
|
931 | 36081602 | j_mayer | env->spr[SPR_40x_PID], 0, i) < 0) |
932 | a8dea12f | j_mayer | continue;
|
933 | a8dea12f | j_mayer | zsel = (tlb->attr >> 4) & 0xF; |
934 | a8dea12f | j_mayer | zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3; |
935 | 4a057712 | j_mayer | if (loglevel != 0) { |
936 | a8dea12f | j_mayer | fprintf(logfile, "%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
|
937 | a8dea12f | j_mayer | __func__, i, zsel, zpr, rw, tlb->attr); |
938 | a8dea12f | j_mayer | } |
939 | a8dea12f | j_mayer | if (access_type == ACCESS_CODE) {
|
940 | a8dea12f | j_mayer | /* Check execute enable bit */
|
941 | a8dea12f | j_mayer | switch (zpr) {
|
942 | c294fc58 | j_mayer | case 0x2: |
943 | c294fc58 | j_mayer | if (msr_pr)
|
944 | c294fc58 | j_mayer | goto check_exec_perm;
|
945 | c294fc58 | j_mayer | goto exec_granted;
|
946 | a8dea12f | j_mayer | case 0x0: |
947 | a8dea12f | j_mayer | if (msr_pr) {
|
948 | a8dea12f | j_mayer | ctx->prot = 0;
|
949 | c55e9aef | j_mayer | ret = -3;
|
950 | a8dea12f | j_mayer | break;
|
951 | a8dea12f | j_mayer | } |
952 | a8dea12f | j_mayer | /* No break here */
|
953 | a8dea12f | j_mayer | case 0x1: |
954 | c294fc58 | j_mayer | check_exec_perm:
|
955 | a8dea12f | j_mayer | /* Check from TLB entry */
|
956 | a8dea12f | j_mayer | if (!(tlb->prot & PAGE_EXEC)) {
|
957 | a8dea12f | j_mayer | ret = -3;
|
958 | a8dea12f | j_mayer | } else {
|
959 | c55e9aef | j_mayer | if (tlb->prot & PAGE_WRITE) {
|
960 | a8dea12f | j_mayer | ctx->prot = PAGE_READ | PAGE_WRITE; |
961 | c55e9aef | j_mayer | } else {
|
962 | a8dea12f | j_mayer | ctx->prot = PAGE_READ; |
963 | c55e9aef | j_mayer | } |
964 | a8dea12f | j_mayer | ret = 0;
|
965 | a8dea12f | j_mayer | } |
966 | a8dea12f | j_mayer | break;
|
967 | a8dea12f | j_mayer | case 0x3: |
968 | c294fc58 | j_mayer | exec_granted:
|
969 | a8dea12f | j_mayer | /* All accesses granted */
|
970 | a8dea12f | j_mayer | ctx->prot = PAGE_READ | PAGE_WRITE; |
971 | c55e9aef | j_mayer | ret = 0;
|
972 | a8dea12f | j_mayer | break;
|
973 | a8dea12f | j_mayer | } |
974 | a8dea12f | j_mayer | } else {
|
975 | a8dea12f | j_mayer | switch (zpr) {
|
976 | c294fc58 | j_mayer | case 0x2: |
977 | c294fc58 | j_mayer | if (msr_pr)
|
978 | c294fc58 | j_mayer | goto check_rw_perm;
|
979 | c294fc58 | j_mayer | goto rw_granted;
|
980 | a8dea12f | j_mayer | case 0x0: |
981 | a8dea12f | j_mayer | if (msr_pr) {
|
982 | a8dea12f | j_mayer | ctx->prot = 0;
|
983 | c55e9aef | j_mayer | ret = -2;
|
984 | a8dea12f | j_mayer | break;
|
985 | a8dea12f | j_mayer | } |
986 | a8dea12f | j_mayer | /* No break here */
|
987 | a8dea12f | j_mayer | case 0x1: |
988 | c294fc58 | j_mayer | check_rw_perm:
|
989 | a8dea12f | j_mayer | /* Check from TLB entry */
|
990 | a8dea12f | j_mayer | /* Check write protection bit */
|
991 | c55e9aef | j_mayer | if (tlb->prot & PAGE_WRITE) {
|
992 | c55e9aef | j_mayer | ctx->prot = PAGE_READ | PAGE_WRITE; |
993 | c55e9aef | j_mayer | ret = 0;
|
994 | a8dea12f | j_mayer | } else {
|
995 | c55e9aef | j_mayer | ctx->prot = PAGE_READ; |
996 | c55e9aef | j_mayer | if (rw)
|
997 | c55e9aef | j_mayer | ret = -2;
|
998 | a8dea12f | j_mayer | else
|
999 | c55e9aef | j_mayer | ret = 0;
|
1000 | a8dea12f | j_mayer | } |
1001 | a8dea12f | j_mayer | break;
|
1002 | a8dea12f | j_mayer | case 0x3: |
1003 | c294fc58 | j_mayer | rw_granted:
|
1004 | a8dea12f | j_mayer | /* All accesses granted */
|
1005 | a8dea12f | j_mayer | ctx->prot = PAGE_READ | PAGE_WRITE; |
1006 | c55e9aef | j_mayer | ret = 0;
|
1007 | a8dea12f | j_mayer | break;
|
1008 | a8dea12f | j_mayer | } |
1009 | a8dea12f | j_mayer | } |
1010 | a8dea12f | j_mayer | if (ret >= 0) { |
1011 | a8dea12f | j_mayer | ctx->raddr = raddr; |
1012 | 4a057712 | j_mayer | if (loglevel != 0) { |
1013 | a8dea12f | j_mayer | fprintf(logfile, "%s: access granted " ADDRX " => " REGX |
1014 | c55e9aef | j_mayer | " %d %d\n", __func__, address, ctx->raddr, ctx->prot,
|
1015 | c55e9aef | j_mayer | ret); |
1016 | a8dea12f | j_mayer | } |
1017 | c55e9aef | j_mayer | return 0; |
1018 | a8dea12f | j_mayer | } |
1019 | a8dea12f | j_mayer | } |
1020 | 4a057712 | j_mayer | if (loglevel != 0) { |
1021 | c55e9aef | j_mayer | fprintf(logfile, "%s: access refused " ADDRX " => " REGX |
1022 | c55e9aef | j_mayer | " %d %d\n", __func__, address, raddr, ctx->prot,
|
1023 | c55e9aef | j_mayer | ret); |
1024 | c55e9aef | j_mayer | } |
1025 | 3b46e624 | ths | |
1026 | a8dea12f | j_mayer | return ret;
|
1027 | a8dea12f | j_mayer | } |
1028 | a8dea12f | j_mayer | |
1029 | c294fc58 | j_mayer | void store_40x_sler (CPUPPCState *env, uint32_t val)
|
1030 | c294fc58 | j_mayer | { |
1031 | c294fc58 | j_mayer | /* XXX: TO BE FIXED */
|
1032 | c294fc58 | j_mayer | if (val != 0x00000000) { |
1033 | c294fc58 | j_mayer | cpu_abort(env, "Little-endian regions are not supported by now\n");
|
1034 | c294fc58 | j_mayer | } |
1035 | c294fc58 | j_mayer | env->spr[SPR_405_SLER] = val; |
1036 | c294fc58 | j_mayer | } |
1037 | c294fc58 | j_mayer | |
1038 | 5eb7995e | j_mayer | int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
|
1039 | 5eb7995e | j_mayer | target_ulong address, int rw,
|
1040 | 5eb7995e | j_mayer | int access_type)
|
1041 | 5eb7995e | j_mayer | { |
1042 | 5eb7995e | j_mayer | ppcemb_tlb_t *tlb; |
1043 | 5eb7995e | j_mayer | target_phys_addr_t raddr; |
1044 | 5eb7995e | j_mayer | int i, prot, ret;
|
1045 | 5eb7995e | j_mayer | |
1046 | 5eb7995e | j_mayer | ret = -1;
|
1047 | 5eb7995e | j_mayer | raddr = -1;
|
1048 | 5eb7995e | j_mayer | for (i = 0; i < env->nb_tlb; i++) { |
1049 | 5eb7995e | j_mayer | tlb = &env->tlb[i].tlbe; |
1050 | 5eb7995e | j_mayer | if (ppcemb_tlb_check(env, tlb, &raddr, address,
|
1051 | 5eb7995e | j_mayer | env->spr[SPR_BOOKE_PID], 1, i) < 0) |
1052 | 5eb7995e | j_mayer | continue;
|
1053 | 5eb7995e | j_mayer | if (msr_pr)
|
1054 | 5eb7995e | j_mayer | prot = tlb->prot & 0xF;
|
1055 | 5eb7995e | j_mayer | else
|
1056 | 5eb7995e | j_mayer | prot = (tlb->prot >> 4) & 0xF; |
1057 | 5eb7995e | j_mayer | /* Check the address space */
|
1058 | 5eb7995e | j_mayer | if (access_type == ACCESS_CODE) {
|
1059 | 5eb7995e | j_mayer | if (msr_is != (tlb->attr & 1)) |
1060 | 5eb7995e | j_mayer | continue;
|
1061 | 5eb7995e | j_mayer | ctx->prot = prot; |
1062 | 5eb7995e | j_mayer | if (prot & PAGE_EXEC) {
|
1063 | 5eb7995e | j_mayer | ret = 0;
|
1064 | 5eb7995e | j_mayer | break;
|
1065 | 5eb7995e | j_mayer | } |
1066 | 5eb7995e | j_mayer | ret = -3;
|
1067 | 5eb7995e | j_mayer | } else {
|
1068 | 5eb7995e | j_mayer | if (msr_ds != (tlb->attr & 1)) |
1069 | 5eb7995e | j_mayer | continue;
|
1070 | 5eb7995e | j_mayer | ctx->prot = prot; |
1071 | 5eb7995e | j_mayer | if ((!rw && prot & PAGE_READ) || (rw && (prot & PAGE_WRITE))) {
|
1072 | 5eb7995e | j_mayer | ret = 0;
|
1073 | 5eb7995e | j_mayer | break;
|
1074 | 5eb7995e | j_mayer | } |
1075 | 5eb7995e | j_mayer | ret = -2;
|
1076 | 5eb7995e | j_mayer | } |
1077 | 5eb7995e | j_mayer | } |
1078 | 5eb7995e | j_mayer | if (ret >= 0) |
1079 | 5eb7995e | j_mayer | ctx->raddr = raddr; |
1080 | 5eb7995e | j_mayer | |
1081 | 5eb7995e | j_mayer | return ret;
|
1082 | 5eb7995e | j_mayer | } |
1083 | 5eb7995e | j_mayer | |
1084 | 76a66253 | j_mayer | static int check_physical (CPUState *env, mmu_ctx_t *ctx, |
1085 | 76a66253 | j_mayer | target_ulong eaddr, int rw)
|
1086 | 76a66253 | j_mayer | { |
1087 | 76a66253 | j_mayer | int in_plb, ret;
|
1088 | 3b46e624 | ths | |
1089 | 76a66253 | j_mayer | ctx->raddr = eaddr; |
1090 | 76a66253 | j_mayer | ctx->prot = PAGE_READ; |
1091 | 76a66253 | j_mayer | ret = 0;
|
1092 | a750fc0b | j_mayer | switch (env->mmu_model) {
|
1093 | a750fc0b | j_mayer | case POWERPC_MMU_32B:
|
1094 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1095 | a750fc0b | j_mayer | case POWERPC_MMU_601:
|
1096 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1097 | a750fc0b | j_mayer | case POWERPC_MMU_REAL_4xx:
|
1098 | caa4039c | j_mayer | ctx->prot |= PAGE_WRITE; |
1099 | caa4039c | j_mayer | break;
|
1100 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
1101 | a750fc0b | j_mayer | case POWERPC_MMU_64B:
|
1102 | a750fc0b | j_mayer | case POWERPC_MMU_64BRIDGE:
|
1103 | caa4039c | j_mayer | /* Real address are 60 bits long */
|
1104 | a750fc0b | j_mayer | ctx->raddr &= 0x0FFFFFFFFFFFFFFFULL;
|
1105 | caa4039c | j_mayer | ctx->prot |= PAGE_WRITE; |
1106 | caa4039c | j_mayer | break;
|
1107 | 9706285b | j_mayer | #endif
|
1108 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1109 | caa4039c | j_mayer | if (unlikely(msr_pe != 0)) { |
1110 | caa4039c | j_mayer | /* 403 family add some particular protections,
|
1111 | caa4039c | j_mayer | * using PBL/PBU registers for accesses with no translation.
|
1112 | caa4039c | j_mayer | */
|
1113 | caa4039c | j_mayer | in_plb = |
1114 | caa4039c | j_mayer | /* Check PLB validity */
|
1115 | caa4039c | j_mayer | (env->pb[0] < env->pb[1] && |
1116 | caa4039c | j_mayer | /* and address in plb area */
|
1117 | caa4039c | j_mayer | eaddr >= env->pb[0] && eaddr < env->pb[1]) || |
1118 | caa4039c | j_mayer | (env->pb[2] < env->pb[3] && |
1119 | caa4039c | j_mayer | eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0; |
1120 | caa4039c | j_mayer | if (in_plb ^ msr_px) {
|
1121 | caa4039c | j_mayer | /* Access in protected area */
|
1122 | caa4039c | j_mayer | if (rw == 1) { |
1123 | caa4039c | j_mayer | /* Access is not allowed */
|
1124 | caa4039c | j_mayer | ret = -2;
|
1125 | caa4039c | j_mayer | } |
1126 | caa4039c | j_mayer | } else {
|
1127 | caa4039c | j_mayer | /* Read-write access is allowed */
|
1128 | caa4039c | j_mayer | ctx->prot |= PAGE_WRITE; |
1129 | 76a66253 | j_mayer | } |
1130 | 76a66253 | j_mayer | } |
1131 | e1833e1f | j_mayer | break;
|
1132 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE:
|
1133 | 76a66253 | j_mayer | ctx->prot |= PAGE_WRITE; |
1134 | caa4039c | j_mayer | break;
|
1135 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1136 | caa4039c | j_mayer | /* XXX: TODO */
|
1137 | caa4039c | j_mayer | cpu_abort(env, "BookE FSL MMU model not implemented\n");
|
1138 | caa4039c | j_mayer | break;
|
1139 | caa4039c | j_mayer | default:
|
1140 | caa4039c | j_mayer | cpu_abort(env, "Unknown or invalid MMU model\n");
|
1141 | caa4039c | j_mayer | return -1; |
1142 | 76a66253 | j_mayer | } |
1143 | 76a66253 | j_mayer | |
1144 | 76a66253 | j_mayer | return ret;
|
1145 | 76a66253 | j_mayer | } |
1146 | 76a66253 | j_mayer | |
1147 | 76a66253 | j_mayer | int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
|
1148 | 76a66253 | j_mayer | int rw, int access_type, int check_BATs) |
1149 | 9a64fbe4 | bellard | { |
1150 | 9a64fbe4 | bellard | int ret;
|
1151 | 514fb8c1 | bellard | #if 0
|
1152 | 4a057712 | j_mayer | if (loglevel != 0) {
|
1153 | 9a64fbe4 | bellard | fprintf(logfile, "%s\n", __func__);
|
1154 | 9a64fbe4 | bellard | }
|
1155 | d9bce9d9 | j_mayer | #endif
|
1156 | 4b3686fa | bellard | if ((access_type == ACCESS_CODE && msr_ir == 0) || |
1157 | 4b3686fa | bellard | (access_type != ACCESS_CODE && msr_dr == 0)) {
|
1158 | 9a64fbe4 | bellard | /* No address translation */
|
1159 | 76a66253 | j_mayer | ret = check_physical(env, ctx, eaddr, rw); |
1160 | 9a64fbe4 | bellard | } else {
|
1161 | c55e9aef | j_mayer | ret = -1;
|
1162 | a750fc0b | j_mayer | switch (env->mmu_model) {
|
1163 | a750fc0b | j_mayer | case POWERPC_MMU_32B:
|
1164 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1165 | a8dea12f | j_mayer | /* Try to find a BAT */
|
1166 | a8dea12f | j_mayer | if (check_BATs)
|
1167 | a8dea12f | j_mayer | ret = get_bat(env, ctx, eaddr, rw, access_type); |
1168 | c55e9aef | j_mayer | /* No break here */
|
1169 | c55e9aef | j_mayer | #if defined(TARGET_PPC64)
|
1170 | a750fc0b | j_mayer | case POWERPC_MMU_64B:
|
1171 | a750fc0b | j_mayer | case POWERPC_MMU_64BRIDGE:
|
1172 | c55e9aef | j_mayer | #endif
|
1173 | a8dea12f | j_mayer | if (ret < 0) { |
1174 | c55e9aef | j_mayer | /* We didn't match any BAT entry or don't have BATs */
|
1175 | a8dea12f | j_mayer | ret = get_segment(env, ctx, eaddr, rw, access_type); |
1176 | a8dea12f | j_mayer | } |
1177 | a8dea12f | j_mayer | break;
|
1178 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1179 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1180 | 36081602 | j_mayer | ret = mmu40x_get_physical_address(env, ctx, eaddr, |
1181 | a8dea12f | j_mayer | rw, access_type); |
1182 | a8dea12f | j_mayer | break;
|
1183 | a750fc0b | j_mayer | case POWERPC_MMU_601:
|
1184 | c55e9aef | j_mayer | /* XXX: TODO */
|
1185 | c55e9aef | j_mayer | cpu_abort(env, "601 MMU model not implemented\n");
|
1186 | c55e9aef | j_mayer | return -1; |
1187 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE:
|
1188 | 5eb7995e | j_mayer | ret = mmubooke_get_physical_address(env, ctx, eaddr, |
1189 | 5eb7995e | j_mayer | rw, access_type); |
1190 | 5eb7995e | j_mayer | break;
|
1191 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1192 | c55e9aef | j_mayer | /* XXX: TODO */
|
1193 | c55e9aef | j_mayer | cpu_abort(env, "BookE FSL MMU model not implemented\n");
|
1194 | c55e9aef | j_mayer | return -1; |
1195 | a750fc0b | j_mayer | case POWERPC_MMU_REAL_4xx:
|
1196 | 2662a059 | j_mayer | cpu_abort(env, "PowerPC 401 does not do any translation\n");
|
1197 | 2662a059 | j_mayer | return -1; |
1198 | c55e9aef | j_mayer | default:
|
1199 | c55e9aef | j_mayer | cpu_abort(env, "Unknown or invalid MMU model\n");
|
1200 | a8dea12f | j_mayer | return -1; |
1201 | 9a64fbe4 | bellard | } |
1202 | 9a64fbe4 | bellard | } |
1203 | 514fb8c1 | bellard | #if 0
|
1204 | 4a057712 | j_mayer | if (loglevel != 0) {
|
1205 | 4a057712 | j_mayer | fprintf(logfile, "%s address " ADDRX " => %d " PADDRX "\n",
|
1206 | c55e9aef | j_mayer | __func__, eaddr, ret, ctx->raddr);
|
1207 | a541f297 | bellard | }
|
1208 | 76a66253 | j_mayer | #endif
|
1209 | d9bce9d9 | j_mayer | |
1210 | 9a64fbe4 | bellard | return ret;
|
1211 | 9a64fbe4 | bellard | } |
1212 | 9a64fbe4 | bellard | |
1213 | 9b3c35e0 | j_mayer | target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr) |
1214 | a6b025d3 | bellard | { |
1215 | 76a66253 | j_mayer | mmu_ctx_t ctx; |
1216 | a6b025d3 | bellard | |
1217 | 76a66253 | j_mayer | if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT, 1) != 0)) |
1218 | a6b025d3 | bellard | return -1; |
1219 | 76a66253 | j_mayer | |
1220 | 76a66253 | j_mayer | return ctx.raddr & TARGET_PAGE_MASK;
|
1221 | a6b025d3 | bellard | } |
1222 | 9a64fbe4 | bellard | |
1223 | 9a64fbe4 | bellard | /* Perform address translation */
|
1224 | e96efcfc | j_mayer | int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
1225 | a541f297 | bellard | int is_user, int is_softmmu) |
1226 | 9a64fbe4 | bellard | { |
1227 | 76a66253 | j_mayer | mmu_ctx_t ctx; |
1228 | 9a64fbe4 | bellard | int exception = 0, error_code = 0; |
1229 | a541f297 | bellard | int access_type;
|
1230 | 9a64fbe4 | bellard | int ret = 0; |
1231 | d9bce9d9 | j_mayer | |
1232 | b769d8fe | bellard | if (rw == 2) { |
1233 | b769d8fe | bellard | /* code access */
|
1234 | b769d8fe | bellard | rw = 0;
|
1235 | b769d8fe | bellard | access_type = ACCESS_CODE; |
1236 | b769d8fe | bellard | } else {
|
1237 | b769d8fe | bellard | /* data access */
|
1238 | b769d8fe | bellard | /* XXX: put correct access by using cpu_restore_state()
|
1239 | b769d8fe | bellard | correctly */
|
1240 | b769d8fe | bellard | access_type = ACCESS_INT; |
1241 | b769d8fe | bellard | // access_type = env->access_type;
|
1242 | b769d8fe | bellard | } |
1243 | 76a66253 | j_mayer | ret = get_physical_address(env, &ctx, address, rw, access_type, 1);
|
1244 | 9a64fbe4 | bellard | if (ret == 0) { |
1245 | 76a66253 | j_mayer | ret = tlb_set_page(env, address & TARGET_PAGE_MASK, |
1246 | 76a66253 | j_mayer | ctx.raddr & TARGET_PAGE_MASK, ctx.prot, |
1247 | 76a66253 | j_mayer | is_user, is_softmmu); |
1248 | 9a64fbe4 | bellard | } else if (ret < 0) { |
1249 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
1250 | 4a057712 | j_mayer | if (loglevel != 0) |
1251 | 76a66253 | j_mayer | cpu_dump_state(env, logfile, fprintf, 0);
|
1252 | 9a64fbe4 | bellard | #endif
|
1253 | 9a64fbe4 | bellard | if (access_type == ACCESS_CODE) {
|
1254 | e1833e1f | j_mayer | exception = POWERPC_EXCP_ISI; |
1255 | 9a64fbe4 | bellard | switch (ret) {
|
1256 | 9a64fbe4 | bellard | case -1: |
1257 | 76a66253 | j_mayer | /* No matches in page tables or TLB */
|
1258 | a750fc0b | j_mayer | switch (env->mmu_model) {
|
1259 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1260 | e1833e1f | j_mayer | exception = POWERPC_EXCP_IFTLB; |
1261 | 76a66253 | j_mayer | env->spr[SPR_IMISS] = address; |
1262 | 76a66253 | j_mayer | env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
|
1263 | 76a66253 | j_mayer | error_code = 1 << 18; |
1264 | 76a66253 | j_mayer | goto tlb_miss;
|
1265 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1266 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1267 | e1833e1f | j_mayer | exception = POWERPC_EXCP_ITLB; |
1268 | a8dea12f | j_mayer | error_code = 0;
|
1269 | a8dea12f | j_mayer | env->spr[SPR_40x_DEAR] = address; |
1270 | a8dea12f | j_mayer | env->spr[SPR_40x_ESR] = 0x00000000;
|
1271 | c55e9aef | j_mayer | break;
|
1272 | a750fc0b | j_mayer | case POWERPC_MMU_32B:
|
1273 | 76a66253 | j_mayer | error_code = 0x40000000;
|
1274 | c55e9aef | j_mayer | break;
|
1275 | c55e9aef | j_mayer | #if defined(TARGET_PPC64)
|
1276 | a750fc0b | j_mayer | case POWERPC_MMU_64B:
|
1277 | c55e9aef | j_mayer | /* XXX: TODO */
|
1278 | c55e9aef | j_mayer | cpu_abort(env, "MMU model not implemented\n");
|
1279 | c55e9aef | j_mayer | return -1; |
1280 | a750fc0b | j_mayer | case POWERPC_MMU_64BRIDGE:
|
1281 | c55e9aef | j_mayer | /* XXX: TODO */
|
1282 | c55e9aef | j_mayer | cpu_abort(env, "MMU model not implemented\n");
|
1283 | c55e9aef | j_mayer | return -1; |
1284 | c55e9aef | j_mayer | #endif
|
1285 | a750fc0b | j_mayer | case POWERPC_MMU_601:
|
1286 | c55e9aef | j_mayer | /* XXX: TODO */
|
1287 | c55e9aef | j_mayer | cpu_abort(env, "MMU model not implemented\n");
|
1288 | c55e9aef | j_mayer | return -1; |
1289 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE:
|
1290 | c55e9aef | j_mayer | /* XXX: TODO */
|
1291 | c55e9aef | j_mayer | cpu_abort(env, "MMU model not implemented\n");
|
1292 | c55e9aef | j_mayer | return -1; |
1293 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1294 | c55e9aef | j_mayer | /* XXX: TODO */
|
1295 | c55e9aef | j_mayer | cpu_abort(env, "MMU model not implemented\n");
|
1296 | c55e9aef | j_mayer | return -1; |
1297 | a750fc0b | j_mayer | case POWERPC_MMU_REAL_4xx:
|
1298 | 2662a059 | j_mayer | cpu_abort(env, "PowerPC 401 should never raise any MMU "
|
1299 | 2662a059 | j_mayer | "exceptions\n");
|
1300 | 2662a059 | j_mayer | return -1; |
1301 | c55e9aef | j_mayer | default:
|
1302 | c55e9aef | j_mayer | cpu_abort(env, "Unknown or invalid MMU model\n");
|
1303 | c55e9aef | j_mayer | return -1; |
1304 | 76a66253 | j_mayer | } |
1305 | 9a64fbe4 | bellard | break;
|
1306 | 9a64fbe4 | bellard | case -2: |
1307 | 9a64fbe4 | bellard | /* Access rights violation */
|
1308 | 2be0071f | bellard | error_code = 0x08000000;
|
1309 | 9a64fbe4 | bellard | break;
|
1310 | 9a64fbe4 | bellard | case -3: |
1311 | 76a66253 | j_mayer | /* No execute protection violation */
|
1312 | 2be0071f | bellard | error_code = 0x10000000;
|
1313 | 9a64fbe4 | bellard | break;
|
1314 | 9a64fbe4 | bellard | case -4: |
1315 | 9a64fbe4 | bellard | /* Direct store exception */
|
1316 | 9a64fbe4 | bellard | /* No code fetch is allowed in direct-store areas */
|
1317 | 2be0071f | bellard | error_code = 0x10000000;
|
1318 | 2be0071f | bellard | break;
|
1319 | e1833e1f | j_mayer | #if defined(TARGET_PPC64)
|
1320 | 2be0071f | bellard | case -5: |
1321 | 2be0071f | bellard | /* No match in segment table */
|
1322 | e1833e1f | j_mayer | exception = POWERPC_EXCP_ISEG; |
1323 | 2be0071f | bellard | error_code = 0;
|
1324 | 9a64fbe4 | bellard | break;
|
1325 | e1833e1f | j_mayer | #endif
|
1326 | 9a64fbe4 | bellard | } |
1327 | 9a64fbe4 | bellard | } else {
|
1328 | e1833e1f | j_mayer | exception = POWERPC_EXCP_DSI; |
1329 | 9a64fbe4 | bellard | switch (ret) {
|
1330 | 9a64fbe4 | bellard | case -1: |
1331 | 76a66253 | j_mayer | /* No matches in page tables or TLB */
|
1332 | a750fc0b | j_mayer | switch (env->mmu_model) {
|
1333 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1334 | 76a66253 | j_mayer | if (rw == 1) { |
1335 | e1833e1f | j_mayer | exception = POWERPC_EXCP_DSTLB; |
1336 | 76a66253 | j_mayer | error_code = 1 << 16; |
1337 | 76a66253 | j_mayer | } else {
|
1338 | e1833e1f | j_mayer | exception = POWERPC_EXCP_DLTLB; |
1339 | 76a66253 | j_mayer | error_code = 0;
|
1340 | 76a66253 | j_mayer | } |
1341 | 76a66253 | j_mayer | env->spr[SPR_DMISS] = address; |
1342 | 76a66253 | j_mayer | env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
|
1343 | 76a66253 | j_mayer | tlb_miss:
|
1344 | 76a66253 | j_mayer | error_code |= ctx.key << 19;
|
1345 | 76a66253 | j_mayer | env->spr[SPR_HASH1] = ctx.pg_addr[0];
|
1346 | 76a66253 | j_mayer | env->spr[SPR_HASH2] = ctx.pg_addr[1];
|
1347 | 76a66253 | j_mayer | /* Do not alter DAR nor DSISR */
|
1348 | 76a66253 | j_mayer | goto out;
|
1349 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1350 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1351 | e1833e1f | j_mayer | exception = POWERPC_EXCP_DTLB; |
1352 | a8dea12f | j_mayer | error_code = 0;
|
1353 | a8dea12f | j_mayer | env->spr[SPR_40x_DEAR] = address; |
1354 | a8dea12f | j_mayer | if (rw)
|
1355 | a8dea12f | j_mayer | env->spr[SPR_40x_ESR] = 0x00800000;
|
1356 | a8dea12f | j_mayer | else
|
1357 | a8dea12f | j_mayer | env->spr[SPR_40x_ESR] = 0x00000000;
|
1358 | c55e9aef | j_mayer | break;
|
1359 | a750fc0b | j_mayer | case POWERPC_MMU_32B:
|
1360 | 76a66253 | j_mayer | error_code = 0x40000000;
|
1361 | c55e9aef | j_mayer | break;
|
1362 | c55e9aef | j_mayer | #if defined(TARGET_PPC64)
|
1363 | a750fc0b | j_mayer | case POWERPC_MMU_64B:
|
1364 | c55e9aef | j_mayer | /* XXX: TODO */
|
1365 | c55e9aef | j_mayer | cpu_abort(env, "MMU model not implemented\n");
|
1366 | c55e9aef | j_mayer | return -1; |
1367 | a750fc0b | j_mayer | case POWERPC_MMU_64BRIDGE:
|
1368 | c55e9aef | j_mayer | /* XXX: TODO */
|
1369 | c55e9aef | j_mayer | cpu_abort(env, "MMU model not implemented\n");
|
1370 | c55e9aef | j_mayer | return -1; |
1371 | c55e9aef | j_mayer | #endif
|
1372 | a750fc0b | j_mayer | case POWERPC_MMU_601:
|
1373 | c55e9aef | j_mayer | /* XXX: TODO */
|
1374 | c55e9aef | j_mayer | cpu_abort(env, "MMU model not implemented\n");
|
1375 | c55e9aef | j_mayer | return -1; |
1376 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE:
|
1377 | c55e9aef | j_mayer | /* XXX: TODO */
|
1378 | c55e9aef | j_mayer | cpu_abort(env, "MMU model not implemented\n");
|
1379 | c55e9aef | j_mayer | return -1; |
1380 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1381 | c55e9aef | j_mayer | /* XXX: TODO */
|
1382 | c55e9aef | j_mayer | cpu_abort(env, "MMU model not implemented\n");
|
1383 | c55e9aef | j_mayer | return -1; |
1384 | a750fc0b | j_mayer | case POWERPC_MMU_REAL_4xx:
|
1385 | 2662a059 | j_mayer | cpu_abort(env, "PowerPC 401 should never raise any MMU "
|
1386 | 2662a059 | j_mayer | "exceptions\n");
|
1387 | 2662a059 | j_mayer | return -1; |
1388 | c55e9aef | j_mayer | default:
|
1389 | c55e9aef | j_mayer | cpu_abort(env, "Unknown or invalid MMU model\n");
|
1390 | c55e9aef | j_mayer | return -1; |
1391 | 76a66253 | j_mayer | } |
1392 | 9a64fbe4 | bellard | break;
|
1393 | 9a64fbe4 | bellard | case -2: |
1394 | 9a64fbe4 | bellard | /* Access rights violation */
|
1395 | 2be0071f | bellard | error_code = 0x08000000;
|
1396 | 9a64fbe4 | bellard | break;
|
1397 | 9a64fbe4 | bellard | case -4: |
1398 | 9a64fbe4 | bellard | /* Direct store exception */
|
1399 | 9a64fbe4 | bellard | switch (access_type) {
|
1400 | 9a64fbe4 | bellard | case ACCESS_FLOAT:
|
1401 | 9a64fbe4 | bellard | /* Floating point load/store */
|
1402 | e1833e1f | j_mayer | exception = POWERPC_EXCP_ALIGN; |
1403 | e1833e1f | j_mayer | error_code = POWERPC_EXCP_ALIGN_FP; |
1404 | 9a64fbe4 | bellard | break;
|
1405 | 9a64fbe4 | bellard | case ACCESS_RES:
|
1406 | 9a64fbe4 | bellard | /* lwarx, ldarx or srwcx. */
|
1407 | 2be0071f | bellard | error_code = 0x04000000;
|
1408 | 9a64fbe4 | bellard | break;
|
1409 | 9a64fbe4 | bellard | case ACCESS_EXT:
|
1410 | 9a64fbe4 | bellard | /* eciwx or ecowx */
|
1411 | 2be0071f | bellard | error_code = 0x04100000;
|
1412 | 9a64fbe4 | bellard | break;
|
1413 | 9a64fbe4 | bellard | default:
|
1414 | 76a66253 | j_mayer | printf("DSI: invalid exception (%d)\n", ret);
|
1415 | e1833e1f | j_mayer | exception = POWERPC_EXCP_PROGRAM; |
1416 | e1833e1f | j_mayer | error_code = POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL; |
1417 | 9a64fbe4 | bellard | break;
|
1418 | 9a64fbe4 | bellard | } |
1419 | fdabc366 | bellard | break;
|
1420 | e1833e1f | j_mayer | #if defined(TARGET_PPC64)
|
1421 | 2be0071f | bellard | case -5: |
1422 | 2be0071f | bellard | /* No match in segment table */
|
1423 | e1833e1f | j_mayer | exception = POWERPC_EXCP_DSEG; |
1424 | 2be0071f | bellard | error_code = 0;
|
1425 | 2be0071f | bellard | break;
|
1426 | e1833e1f | j_mayer | #endif
|
1427 | 9a64fbe4 | bellard | } |
1428 | e1833e1f | j_mayer | if (exception == POWERPC_EXCP_DSI && rw == 1) |
1429 | 2be0071f | bellard | error_code |= 0x02000000;
|
1430 | 76a66253 | j_mayer | /* Store fault address */
|
1431 | 76a66253 | j_mayer | env->spr[SPR_DAR] = address; |
1432 | 2be0071f | bellard | env->spr[SPR_DSISR] = error_code; |
1433 | 9a64fbe4 | bellard | } |
1434 | 76a66253 | j_mayer | out:
|
1435 | 9a64fbe4 | bellard | #if 0
|
1436 | 9a64fbe4 | bellard | printf("%s: set exception to %d %02x\n",
|
1437 | 9a64fbe4 | bellard | __func__, exception, error_code);
|
1438 | 9a64fbe4 | bellard | #endif
|
1439 | 9a64fbe4 | bellard | env->exception_index = exception; |
1440 | 9a64fbe4 | bellard | env->error_code = error_code; |
1441 | 9a64fbe4 | bellard | ret = 1;
|
1442 | 9a64fbe4 | bellard | } |
1443 | 76a66253 | j_mayer | |
1444 | 9a64fbe4 | bellard | return ret;
|
1445 | 9a64fbe4 | bellard | } |
1446 | 9a64fbe4 | bellard | |
1447 | 3fc6c082 | bellard | /*****************************************************************************/
|
1448 | 3fc6c082 | bellard | /* BATs management */
|
1449 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS)
|
1450 | 3fc6c082 | bellard | static inline void do_invalidate_BAT (CPUPPCState *env, |
1451 | 3fc6c082 | bellard | target_ulong BATu, target_ulong mask) |
1452 | 3fc6c082 | bellard | { |
1453 | 3fc6c082 | bellard | target_ulong base, end, page; |
1454 | 76a66253 | j_mayer | |
1455 | 3fc6c082 | bellard | base = BATu & ~0x0001FFFF;
|
1456 | 3fc6c082 | bellard | end = base + mask + 0x00020000;
|
1457 | 3fc6c082 | bellard | #if defined (DEBUG_BATS)
|
1458 | 76a66253 | j_mayer | if (loglevel != 0) { |
1459 | 1b9eb036 | j_mayer | fprintf(logfile, "Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n", |
1460 | 76a66253 | j_mayer | base, end, mask); |
1461 | 76a66253 | j_mayer | } |
1462 | 3fc6c082 | bellard | #endif
|
1463 | 3fc6c082 | bellard | for (page = base; page != end; page += TARGET_PAGE_SIZE)
|
1464 | 3fc6c082 | bellard | tlb_flush_page(env, page); |
1465 | 3fc6c082 | bellard | #if defined (DEBUG_BATS)
|
1466 | 3fc6c082 | bellard | if (loglevel != 0) |
1467 | 3fc6c082 | bellard | fprintf(logfile, "Flush done\n");
|
1468 | 3fc6c082 | bellard | #endif
|
1469 | 3fc6c082 | bellard | } |
1470 | 3fc6c082 | bellard | #endif
|
1471 | 3fc6c082 | bellard | |
1472 | 3fc6c082 | bellard | static inline void dump_store_bat (CPUPPCState *env, char ID, int ul, int nr, |
1473 | 3fc6c082 | bellard | target_ulong value) |
1474 | 3fc6c082 | bellard | { |
1475 | 3fc6c082 | bellard | #if defined (DEBUG_BATS)
|
1476 | 3fc6c082 | bellard | if (loglevel != 0) { |
1477 | 1b9eb036 | j_mayer | fprintf(logfile, "Set %cBAT%d%c to 0x" ADDRX " (0x" ADDRX ")\n", |
1478 | 1b9eb036 | j_mayer | ID, nr, ul == 0 ? 'u' : 'l', value, env->nip); |
1479 | 3fc6c082 | bellard | } |
1480 | 3fc6c082 | bellard | #endif
|
1481 | 3fc6c082 | bellard | } |
1482 | 3fc6c082 | bellard | |
1483 | 3fc6c082 | bellard | target_ulong do_load_ibatu (CPUPPCState *env, int nr)
|
1484 | 3fc6c082 | bellard | { |
1485 | 3fc6c082 | bellard | return env->IBAT[0][nr]; |
1486 | 3fc6c082 | bellard | } |
1487 | 3fc6c082 | bellard | |
1488 | 3fc6c082 | bellard | target_ulong do_load_ibatl (CPUPPCState *env, int nr)
|
1489 | 3fc6c082 | bellard | { |
1490 | 3fc6c082 | bellard | return env->IBAT[1][nr]; |
1491 | 3fc6c082 | bellard | } |
1492 | 3fc6c082 | bellard | |
1493 | 3fc6c082 | bellard | void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value) |
1494 | 3fc6c082 | bellard | { |
1495 | 3fc6c082 | bellard | target_ulong mask; |
1496 | 3fc6c082 | bellard | |
1497 | 3fc6c082 | bellard | dump_store_bat(env, 'I', 0, nr, value); |
1498 | 3fc6c082 | bellard | if (env->IBAT[0][nr] != value) { |
1499 | 3fc6c082 | bellard | mask = (value << 15) & 0x0FFE0000UL; |
1500 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS)
|
1501 | 3fc6c082 | bellard | do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
1502 | 3fc6c082 | bellard | #endif
|
1503 | 3fc6c082 | bellard | /* When storing valid upper BAT, mask BEPI and BRPN
|
1504 | 3fc6c082 | bellard | * and invalidate all TLBs covered by this BAT
|
1505 | 3fc6c082 | bellard | */
|
1506 | 3fc6c082 | bellard | mask = (value << 15) & 0x0FFE0000UL; |
1507 | 3fc6c082 | bellard | env->IBAT[0][nr] = (value & 0x00001FFFUL) | |
1508 | 3fc6c082 | bellard | (value & ~0x0001FFFFUL & ~mask);
|
1509 | 3fc6c082 | bellard | env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) | |
1510 | 3fc6c082 | bellard | (env->IBAT[1][nr] & ~0x0001FFFF & ~mask); |
1511 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS)
|
1512 | 3fc6c082 | bellard | do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
1513 | 76a66253 | j_mayer | #else
|
1514 | 3fc6c082 | bellard | tlb_flush(env, 1);
|
1515 | 3fc6c082 | bellard | #endif
|
1516 | 3fc6c082 | bellard | } |
1517 | 3fc6c082 | bellard | } |
1518 | 3fc6c082 | bellard | |
1519 | 3fc6c082 | bellard | void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value) |
1520 | 3fc6c082 | bellard | { |
1521 | 3fc6c082 | bellard | dump_store_bat(env, 'I', 1, nr, value); |
1522 | 3fc6c082 | bellard | env->IBAT[1][nr] = value;
|
1523 | 3fc6c082 | bellard | } |
1524 | 3fc6c082 | bellard | |
1525 | 3fc6c082 | bellard | target_ulong do_load_dbatu (CPUPPCState *env, int nr)
|
1526 | 3fc6c082 | bellard | { |
1527 | 3fc6c082 | bellard | return env->DBAT[0][nr]; |
1528 | 3fc6c082 | bellard | } |
1529 | 3fc6c082 | bellard | |
1530 | 3fc6c082 | bellard | target_ulong do_load_dbatl (CPUPPCState *env, int nr)
|
1531 | 3fc6c082 | bellard | { |
1532 | 3fc6c082 | bellard | return env->DBAT[1][nr]; |
1533 | 3fc6c082 | bellard | } |
1534 | 3fc6c082 | bellard | |
1535 | 3fc6c082 | bellard | void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value) |
1536 | 3fc6c082 | bellard | { |
1537 | 3fc6c082 | bellard | target_ulong mask; |
1538 | 3fc6c082 | bellard | |
1539 | 3fc6c082 | bellard | dump_store_bat(env, 'D', 0, nr, value); |
1540 | 3fc6c082 | bellard | if (env->DBAT[0][nr] != value) { |
1541 | 3fc6c082 | bellard | /* When storing valid upper BAT, mask BEPI and BRPN
|
1542 | 3fc6c082 | bellard | * and invalidate all TLBs covered by this BAT
|
1543 | 3fc6c082 | bellard | */
|
1544 | 3fc6c082 | bellard | mask = (value << 15) & 0x0FFE0000UL; |
1545 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS)
|
1546 | 3fc6c082 | bellard | do_invalidate_BAT(env, env->DBAT[0][nr], mask);
|
1547 | 3fc6c082 | bellard | #endif
|
1548 | 3fc6c082 | bellard | mask = (value << 15) & 0x0FFE0000UL; |
1549 | 3fc6c082 | bellard | env->DBAT[0][nr] = (value & 0x00001FFFUL) | |
1550 | 3fc6c082 | bellard | (value & ~0x0001FFFFUL & ~mask);
|
1551 | 3fc6c082 | bellard | env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) | |
1552 | 3fc6c082 | bellard | (env->DBAT[1][nr] & ~0x0001FFFF & ~mask); |
1553 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS)
|
1554 | 3fc6c082 | bellard | do_invalidate_BAT(env, env->DBAT[0][nr], mask);
|
1555 | 3fc6c082 | bellard | #else
|
1556 | 3fc6c082 | bellard | tlb_flush(env, 1);
|
1557 | 3fc6c082 | bellard | #endif
|
1558 | 3fc6c082 | bellard | } |
1559 | 3fc6c082 | bellard | } |
1560 | 3fc6c082 | bellard | |
1561 | 3fc6c082 | bellard | void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value) |
1562 | 3fc6c082 | bellard | { |
1563 | 3fc6c082 | bellard | dump_store_bat(env, 'D', 1, nr, value); |
1564 | 3fc6c082 | bellard | env->DBAT[1][nr] = value;
|
1565 | 3fc6c082 | bellard | } |
1566 | 3fc6c082 | bellard | |
1567 | 0a032cbe | j_mayer | |
1568 | 0a032cbe | j_mayer | /*****************************************************************************/
|
1569 | 0a032cbe | j_mayer | /* TLB management */
|
1570 | 0a032cbe | j_mayer | void ppc_tlb_invalidate_all (CPUPPCState *env)
|
1571 | 0a032cbe | j_mayer | { |
1572 | a750fc0b | j_mayer | if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx)) {
|
1573 | 0a032cbe | j_mayer | ppc6xx_tlb_invalidate_all(env); |
1574 | a750fc0b | j_mayer | } else if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_4xx)) { |
1575 | 0a032cbe | j_mayer | ppc4xx_tlb_invalidate_all(env); |
1576 | 0a032cbe | j_mayer | } else {
|
1577 | 0a032cbe | j_mayer | tlb_flush(env, 1);
|
1578 | 0a032cbe | j_mayer | } |
1579 | 0a032cbe | j_mayer | } |
1580 | 0a032cbe | j_mayer | |
1581 | 3fc6c082 | bellard | /*****************************************************************************/
|
1582 | 3fc6c082 | bellard | /* Special registers manipulation */
|
1583 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1584 | d9bce9d9 | j_mayer | target_ulong ppc_load_asr (CPUPPCState *env) |
1585 | d9bce9d9 | j_mayer | { |
1586 | d9bce9d9 | j_mayer | return env->asr;
|
1587 | d9bce9d9 | j_mayer | } |
1588 | d9bce9d9 | j_mayer | |
1589 | d9bce9d9 | j_mayer | void ppc_store_asr (CPUPPCState *env, target_ulong value)
|
1590 | d9bce9d9 | j_mayer | { |
1591 | d9bce9d9 | j_mayer | if (env->asr != value) {
|
1592 | d9bce9d9 | j_mayer | env->asr = value; |
1593 | d9bce9d9 | j_mayer | tlb_flush(env, 1);
|
1594 | d9bce9d9 | j_mayer | } |
1595 | d9bce9d9 | j_mayer | } |
1596 | d9bce9d9 | j_mayer | #endif
|
1597 | d9bce9d9 | j_mayer | |
1598 | 3fc6c082 | bellard | target_ulong do_load_sdr1 (CPUPPCState *env) |
1599 | 3fc6c082 | bellard | { |
1600 | 3fc6c082 | bellard | return env->sdr1;
|
1601 | 3fc6c082 | bellard | } |
1602 | 3fc6c082 | bellard | |
1603 | 3fc6c082 | bellard | void do_store_sdr1 (CPUPPCState *env, target_ulong value)
|
1604 | 3fc6c082 | bellard | { |
1605 | 3fc6c082 | bellard | #if defined (DEBUG_MMU)
|
1606 | 3fc6c082 | bellard | if (loglevel != 0) { |
1607 | 1b9eb036 | j_mayer | fprintf(logfile, "%s: 0x" ADDRX "\n", __func__, value); |
1608 | 3fc6c082 | bellard | } |
1609 | 3fc6c082 | bellard | #endif
|
1610 | 3fc6c082 | bellard | if (env->sdr1 != value) {
|
1611 | 3fc6c082 | bellard | env->sdr1 = value; |
1612 | 76a66253 | j_mayer | tlb_flush(env, 1);
|
1613 | 3fc6c082 | bellard | } |
1614 | 3fc6c082 | bellard | } |
1615 | 3fc6c082 | bellard | |
1616 | 3fc6c082 | bellard | target_ulong do_load_sr (CPUPPCState *env, int srnum)
|
1617 | 3fc6c082 | bellard | { |
1618 | 3fc6c082 | bellard | return env->sr[srnum];
|
1619 | 3fc6c082 | bellard | } |
1620 | 3fc6c082 | bellard | |
1621 | 3fc6c082 | bellard | void do_store_sr (CPUPPCState *env, int srnum, target_ulong value) |
1622 | 3fc6c082 | bellard | { |
1623 | 3fc6c082 | bellard | #if defined (DEBUG_MMU)
|
1624 | 3fc6c082 | bellard | if (loglevel != 0) { |
1625 | 1b9eb036 | j_mayer | fprintf(logfile, "%s: reg=%d 0x" ADDRX " " ADDRX "\n", |
1626 | 1b9eb036 | j_mayer | __func__, srnum, value, env->sr[srnum]); |
1627 | 3fc6c082 | bellard | } |
1628 | 3fc6c082 | bellard | #endif
|
1629 | 3fc6c082 | bellard | if (env->sr[srnum] != value) {
|
1630 | 3fc6c082 | bellard | env->sr[srnum] = value; |
1631 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS) && 0 |
1632 | 3fc6c082 | bellard | { |
1633 | 3fc6c082 | bellard | target_ulong page, end; |
1634 | 3fc6c082 | bellard | /* Invalidate 256 MB of virtual memory */
|
1635 | 3fc6c082 | bellard | page = (16 << 20) * srnum; |
1636 | 3fc6c082 | bellard | end = page + (16 << 20); |
1637 | 3fc6c082 | bellard | for (; page != end; page += TARGET_PAGE_SIZE)
|
1638 | 3fc6c082 | bellard | tlb_flush_page(env, page); |
1639 | 3fc6c082 | bellard | } |
1640 | 3fc6c082 | bellard | #else
|
1641 | 76a66253 | j_mayer | tlb_flush(env, 1);
|
1642 | 3fc6c082 | bellard | #endif
|
1643 | 3fc6c082 | bellard | } |
1644 | 3fc6c082 | bellard | } |
1645 | 76a66253 | j_mayer | #endif /* !defined (CONFIG_USER_ONLY) */ |
1646 | 3fc6c082 | bellard | |
1647 | bfa1e5cf | j_mayer | target_ulong ppc_load_xer (CPUPPCState *env) |
1648 | 79aceca5 | bellard | { |
1649 | 79aceca5 | bellard | return (xer_so << XER_SO) |
|
1650 | 79aceca5 | bellard | (xer_ov << XER_OV) | |
1651 | 79aceca5 | bellard | (xer_ca << XER_CA) | |
1652 | 3fc6c082 | bellard | (xer_bc << XER_BC) | |
1653 | 3fc6c082 | bellard | (xer_cmp << XER_CMP); |
1654 | 79aceca5 | bellard | } |
1655 | 79aceca5 | bellard | |
1656 | bfa1e5cf | j_mayer | void ppc_store_xer (CPUPPCState *env, target_ulong value)
|
1657 | 79aceca5 | bellard | { |
1658 | 79aceca5 | bellard | xer_so = (value >> XER_SO) & 0x01;
|
1659 | 79aceca5 | bellard | xer_ov = (value >> XER_OV) & 0x01;
|
1660 | 79aceca5 | bellard | xer_ca = (value >> XER_CA) & 0x01;
|
1661 | 3fc6c082 | bellard | xer_cmp = (value >> XER_CMP) & 0xFF;
|
1662 | d9bce9d9 | j_mayer | xer_bc = (value >> XER_BC) & 0x7F;
|
1663 | 79aceca5 | bellard | } |
1664 | 79aceca5 | bellard | |
1665 | 76a66253 | j_mayer | /* Swap temporary saved registers with GPRs */
|
1666 | 76a66253 | j_mayer | static inline void swap_gpr_tgpr (CPUPPCState *env) |
1667 | 79aceca5 | bellard | { |
1668 | 76a66253 | j_mayer | ppc_gpr_t tmp; |
1669 | 76a66253 | j_mayer | |
1670 | 76a66253 | j_mayer | tmp = env->gpr[0];
|
1671 | 76a66253 | j_mayer | env->gpr[0] = env->tgpr[0]; |
1672 | 76a66253 | j_mayer | env->tgpr[0] = tmp;
|
1673 | 76a66253 | j_mayer | tmp = env->gpr[1];
|
1674 | 76a66253 | j_mayer | env->gpr[1] = env->tgpr[1]; |
1675 | 76a66253 | j_mayer | env->tgpr[1] = tmp;
|
1676 | 76a66253 | j_mayer | tmp = env->gpr[2];
|
1677 | 76a66253 | j_mayer | env->gpr[2] = env->tgpr[2]; |
1678 | 76a66253 | j_mayer | env->tgpr[2] = tmp;
|
1679 | 76a66253 | j_mayer | tmp = env->gpr[3];
|
1680 | 76a66253 | j_mayer | env->gpr[3] = env->tgpr[3]; |
1681 | 76a66253 | j_mayer | env->tgpr[3] = tmp;
|
1682 | 79aceca5 | bellard | } |
1683 | 79aceca5 | bellard | |
1684 | 76a66253 | j_mayer | /* GDBstub can read and write MSR... */
|
1685 | 76a66253 | j_mayer | target_ulong do_load_msr (CPUPPCState *env) |
1686 | 79aceca5 | bellard | { |
1687 | 76a66253 | j_mayer | return
|
1688 | 76a66253 | j_mayer | #if defined (TARGET_PPC64)
|
1689 | d9bce9d9 | j_mayer | ((target_ulong)msr_sf << MSR_SF) | |
1690 | d9bce9d9 | j_mayer | ((target_ulong)msr_isf << MSR_ISF) | |
1691 | d9bce9d9 | j_mayer | ((target_ulong)msr_hv << MSR_HV) | |
1692 | 76a66253 | j_mayer | #endif
|
1693 | d9bce9d9 | j_mayer | ((target_ulong)msr_ucle << MSR_UCLE) | |
1694 | d9bce9d9 | j_mayer | ((target_ulong)msr_vr << MSR_VR) | /* VR / SPE */
|
1695 | d9bce9d9 | j_mayer | ((target_ulong)msr_ap << MSR_AP) | |
1696 | d9bce9d9 | j_mayer | ((target_ulong)msr_sa << MSR_SA) | |
1697 | d9bce9d9 | j_mayer | ((target_ulong)msr_key << MSR_KEY) | |
1698 | d9bce9d9 | j_mayer | ((target_ulong)msr_pow << MSR_POW) | /* POW / WE */
|
1699 | d9bce9d9 | j_mayer | ((target_ulong)msr_tlb << MSR_TLB) | /* TLB / TGPE / CE */
|
1700 | d9bce9d9 | j_mayer | ((target_ulong)msr_ile << MSR_ILE) | |
1701 | d9bce9d9 | j_mayer | ((target_ulong)msr_ee << MSR_EE) | |
1702 | d9bce9d9 | j_mayer | ((target_ulong)msr_pr << MSR_PR) | |
1703 | d9bce9d9 | j_mayer | ((target_ulong)msr_fp << MSR_FP) | |
1704 | d9bce9d9 | j_mayer | ((target_ulong)msr_me << MSR_ME) | |
1705 | d9bce9d9 | j_mayer | ((target_ulong)msr_fe0 << MSR_FE0) | |
1706 | d9bce9d9 | j_mayer | ((target_ulong)msr_se << MSR_SE) | /* SE / DWE / UBLE */
|
1707 | d9bce9d9 | j_mayer | ((target_ulong)msr_be << MSR_BE) | /* BE / DE */
|
1708 | d9bce9d9 | j_mayer | ((target_ulong)msr_fe1 << MSR_FE1) | |
1709 | d9bce9d9 | j_mayer | ((target_ulong)msr_al << MSR_AL) | |
1710 | d9bce9d9 | j_mayer | ((target_ulong)msr_ip << MSR_IP) | |
1711 | d9bce9d9 | j_mayer | ((target_ulong)msr_ir << MSR_IR) | /* IR / IS */
|
1712 | d9bce9d9 | j_mayer | ((target_ulong)msr_dr << MSR_DR) | /* DR / DS */
|
1713 | d9bce9d9 | j_mayer | ((target_ulong)msr_pe << MSR_PE) | /* PE / EP */
|
1714 | d9bce9d9 | j_mayer | ((target_ulong)msr_px << MSR_PX) | /* PX / PMM */
|
1715 | d9bce9d9 | j_mayer | ((target_ulong)msr_ri << MSR_RI) | |
1716 | d9bce9d9 | j_mayer | ((target_ulong)msr_le << MSR_LE); |
1717 | 3fc6c082 | bellard | } |
1718 | 3fc6c082 | bellard | |
1719 | 3fc6c082 | bellard | void do_store_msr (CPUPPCState *env, target_ulong value)
|
1720 | 313adae9 | bellard | { |
1721 | 50443c98 | bellard | int enter_pm;
|
1722 | 50443c98 | bellard | |
1723 | 3fc6c082 | bellard | value &= env->msr_mask; |
1724 | 3fc6c082 | bellard | if (((value >> MSR_IR) & 1) != msr_ir || |
1725 | 3fc6c082 | bellard | ((value >> MSR_DR) & 1) != msr_dr) {
|
1726 | 76a66253 | j_mayer | /* Flush all tlb when changing translation mode */
|
1727 | d094807b | bellard | tlb_flush(env, 1);
|
1728 | 3fc6c082 | bellard | env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
1729 | a541f297 | bellard | } |
1730 | 3fc6c082 | bellard | #if 0
|
1731 | 3fc6c082 | bellard | if (loglevel != 0) {
|
1732 | 3fc6c082 | bellard | fprintf(logfile, "%s: T0 %08lx\n", __func__, value);
|
1733 | 3fc6c082 | bellard | }
|
1734 | 3fc6c082 | bellard | #endif
|
1735 | a750fc0b | j_mayer | switch (env->excp_model) {
|
1736 | a750fc0b | j_mayer | case POWERPC_EXCP_602:
|
1737 | a750fc0b | j_mayer | case POWERPC_EXCP_603:
|
1738 | a750fc0b | j_mayer | case POWERPC_EXCP_603E:
|
1739 | a750fc0b | j_mayer | case POWERPC_EXCP_G2:
|
1740 | 76a66253 | j_mayer | if (((value >> MSR_TGPR) & 1) != msr_tgpr) { |
1741 | 76a66253 | j_mayer | /* Swap temporary saved registers with GPRs */
|
1742 | 76a66253 | j_mayer | swap_gpr_tgpr(env); |
1743 | 76a66253 | j_mayer | } |
1744 | 76a66253 | j_mayer | break;
|
1745 | 76a66253 | j_mayer | default:
|
1746 | 76a66253 | j_mayer | break;
|
1747 | 76a66253 | j_mayer | } |
1748 | 76a66253 | j_mayer | #if defined (TARGET_PPC64)
|
1749 | 76a66253 | j_mayer | msr_sf = (value >> MSR_SF) & 1;
|
1750 | 76a66253 | j_mayer | msr_isf = (value >> MSR_ISF) & 1;
|
1751 | 76a66253 | j_mayer | msr_hv = (value >> MSR_HV) & 1;
|
1752 | 76a66253 | j_mayer | #endif
|
1753 | 76a66253 | j_mayer | msr_ucle = (value >> MSR_UCLE) & 1;
|
1754 | 76a66253 | j_mayer | msr_vr = (value >> MSR_VR) & 1; /* VR / SPE */ |
1755 | 76a66253 | j_mayer | msr_ap = (value >> MSR_AP) & 1;
|
1756 | 76a66253 | j_mayer | msr_sa = (value >> MSR_SA) & 1;
|
1757 | 76a66253 | j_mayer | msr_key = (value >> MSR_KEY) & 1;
|
1758 | 76a66253 | j_mayer | msr_pow = (value >> MSR_POW) & 1; /* POW / WE */ |
1759 | 76a66253 | j_mayer | msr_tlb = (value >> MSR_TLB) & 1; /* TLB / TGPR / CE */ |
1760 | 76a66253 | j_mayer | msr_ile = (value >> MSR_ILE) & 1;
|
1761 | 76a66253 | j_mayer | msr_ee = (value >> MSR_EE) & 1;
|
1762 | 76a66253 | j_mayer | msr_pr = (value >> MSR_PR) & 1;
|
1763 | 76a66253 | j_mayer | msr_fp = (value >> MSR_FP) & 1;
|
1764 | 76a66253 | j_mayer | msr_me = (value >> MSR_ME) & 1;
|
1765 | 76a66253 | j_mayer | msr_fe0 = (value >> MSR_FE0) & 1;
|
1766 | 76a66253 | j_mayer | msr_se = (value >> MSR_SE) & 1; /* SE / DWE / UBLE */ |
1767 | 76a66253 | j_mayer | msr_be = (value >> MSR_BE) & 1; /* BE / DE */ |
1768 | 76a66253 | j_mayer | msr_fe1 = (value >> MSR_FE1) & 1;
|
1769 | 76a66253 | j_mayer | msr_al = (value >> MSR_AL) & 1;
|
1770 | 76a66253 | j_mayer | msr_ip = (value >> MSR_IP) & 1;
|
1771 | 76a66253 | j_mayer | msr_ir = (value >> MSR_IR) & 1; /* IR / IS */ |
1772 | 76a66253 | j_mayer | msr_dr = (value >> MSR_DR) & 1; /* DR / DS */ |
1773 | 76a66253 | j_mayer | msr_pe = (value >> MSR_PE) & 1; /* PE / EP */ |
1774 | 76a66253 | j_mayer | msr_px = (value >> MSR_PX) & 1; /* PX / PMM */ |
1775 | 76a66253 | j_mayer | msr_ri = (value >> MSR_RI) & 1;
|
1776 | 76a66253 | j_mayer | msr_le = (value >> MSR_LE) & 1;
|
1777 | 3fc6c082 | bellard | do_compute_hflags(env); |
1778 | 50443c98 | bellard | |
1779 | 50443c98 | bellard | enter_pm = 0;
|
1780 | a750fc0b | j_mayer | switch (env->excp_model) {
|
1781 | a750fc0b | j_mayer | case POWERPC_EXCP_603:
|
1782 | a750fc0b | j_mayer | case POWERPC_EXCP_603E:
|
1783 | a750fc0b | j_mayer | case POWERPC_EXCP_G2:
|
1784 | d9bce9d9 | j_mayer | /* Don't handle SLEEP mode: we should disable all clocks...
|
1785 | d9bce9d9 | j_mayer | * No dynamic power-management.
|
1786 | d9bce9d9 | j_mayer | */
|
1787 | d9bce9d9 | j_mayer | if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00C00000) != 0) |
1788 | d9bce9d9 | j_mayer | enter_pm = 1;
|
1789 | d9bce9d9 | j_mayer | break;
|
1790 | a750fc0b | j_mayer | case POWERPC_EXCP_604:
|
1791 | d9bce9d9 | j_mayer | if (msr_pow == 1) |
1792 | d9bce9d9 | j_mayer | enter_pm = 1;
|
1793 | d9bce9d9 | j_mayer | break;
|
1794 | a750fc0b | j_mayer | case POWERPC_EXCP_7x0:
|
1795 | 76a66253 | j_mayer | if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00E00000) != 0) |
1796 | 50443c98 | bellard | enter_pm = 1;
|
1797 | 50443c98 | bellard | break;
|
1798 | 50443c98 | bellard | default:
|
1799 | 50443c98 | bellard | break;
|
1800 | 50443c98 | bellard | } |
1801 | 50443c98 | bellard | if (enter_pm) {
|
1802 | c19dbb94 | ths | if (likely(!env->halted)) {
|
1803 | c19dbb94 | ths | /* power save: exit cpu loop */
|
1804 | c19dbb94 | ths | env->halted = 1;
|
1805 | c19dbb94 | ths | env->exception_index = EXCP_HLT; |
1806 | c19dbb94 | ths | cpu_loop_exit(); |
1807 | c19dbb94 | ths | } |
1808 | e80e1cc4 | bellard | } |
1809 | 3fc6c082 | bellard | } |
1810 | 3fc6c082 | bellard | |
1811 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1812 | 426613db | j_mayer | void ppc_store_msr_32 (CPUPPCState *env, uint32_t value)
|
1813 | d9bce9d9 | j_mayer | { |
1814 | 426613db | j_mayer | do_store_msr(env, |
1815 | 426613db | j_mayer | (do_load_msr(env) & ~0xFFFFFFFFULL) | (value & 0xFFFFFFFF)); |
1816 | d9bce9d9 | j_mayer | } |
1817 | d9bce9d9 | j_mayer | #endif
|
1818 | d9bce9d9 | j_mayer | |
1819 | 76a66253 | j_mayer | void do_compute_hflags (CPUPPCState *env)
|
1820 | 3fc6c082 | bellard | { |
1821 | 76a66253 | j_mayer | /* Compute current hflags */
|
1822 | 4296f459 | j_mayer | env->hflags = (msr_vr << MSR_VR) | |
1823 | c62db105 | j_mayer | (msr_ap << MSR_AP) | (msr_sa << MSR_SA) | (msr_pr << MSR_PR) | |
1824 | c62db105 | j_mayer | (msr_fp << MSR_FP) | (msr_fe0 << MSR_FE0) | (msr_se << MSR_SE) | |
1825 | c62db105 | j_mayer | (msr_be << MSR_BE) | (msr_fe1 << MSR_FE1) | (msr_le << MSR_LE); |
1826 | 76a66253 | j_mayer | #if defined (TARGET_PPC64)
|
1827 | 4296f459 | j_mayer | env->hflags |= msr_cm << MSR_CM; |
1828 | 4296f459 | j_mayer | env->hflags |= (uint64_t)msr_sf << MSR_SF; |
1829 | 4296f459 | j_mayer | env->hflags |= (uint64_t)msr_hv << MSR_HV; |
1830 | 4b3686fa | bellard | #endif
|
1831 | 3fc6c082 | bellard | } |
1832 | 3fc6c082 | bellard | |
1833 | 3fc6c082 | bellard | /*****************************************************************************/
|
1834 | 3fc6c082 | bellard | /* Exception processing */
|
1835 | 18fba28c | bellard | #if defined (CONFIG_USER_ONLY)
|
1836 | 9a64fbe4 | bellard | void do_interrupt (CPUState *env)
|
1837 | 79aceca5 | bellard | { |
1838 | e1833e1f | j_mayer | env->exception_index = POWERPC_EXCP_NONE; |
1839 | e1833e1f | j_mayer | env->error_code = 0;
|
1840 | 18fba28c | bellard | } |
1841 | 47103572 | j_mayer | |
1842 | e9df014c | j_mayer | void ppc_hw_interrupt (CPUState *env)
|
1843 | 47103572 | j_mayer | { |
1844 | e1833e1f | j_mayer | env->exception_index = POWERPC_EXCP_NONE; |
1845 | e1833e1f | j_mayer | env->error_code = 0;
|
1846 | 47103572 | j_mayer | } |
1847 | 76a66253 | j_mayer | #else /* defined (CONFIG_USER_ONLY) */ |
1848 | 36081602 | j_mayer | static void dump_syscall (CPUState *env) |
1849 | d094807b | bellard | { |
1850 | d9bce9d9 | j_mayer | fprintf(logfile, "syscall r0=0x" REGX " r3=0x" REGX " r4=0x" REGX |
1851 | 1b9eb036 | j_mayer | " r5=0x" REGX " r6=0x" REGX " nip=0x" ADDRX "\n", |
1852 | d094807b | bellard | env->gpr[0], env->gpr[3], env->gpr[4], |
1853 | d094807b | bellard | env->gpr[5], env->gpr[6], env->nip); |
1854 | d094807b | bellard | } |
1855 | d094807b | bellard | |
1856 | e1833e1f | j_mayer | /* Note that this function should be greatly optimized
|
1857 | e1833e1f | j_mayer | * when called with a constant excp, from ppc_hw_interrupt
|
1858 | e1833e1f | j_mayer | */
|
1859 | e1833e1f | j_mayer | static always_inline void powerpc_excp (CPUState *env, |
1860 | e1833e1f | j_mayer | int excp_model, int excp) |
1861 | 18fba28c | bellard | { |
1862 | e1833e1f | j_mayer | target_ulong msr, vector; |
1863 | e1833e1f | j_mayer | int srr0, srr1, asrr0, asrr1;
|
1864 | 79aceca5 | bellard | |
1865 | b769d8fe | bellard | if (loglevel & CPU_LOG_INT) {
|
1866 | 1b9eb036 | j_mayer | fprintf(logfile, "Raise exception at 0x" ADDRX " => 0x%08x (%02x)\n", |
1867 | 1b9eb036 | j_mayer | env->nip, excp, env->error_code); |
1868 | b769d8fe | bellard | } |
1869 | e1833e1f | j_mayer | msr = do_load_msr(env); |
1870 | e1833e1f | j_mayer | srr0 = SPR_SRR0; |
1871 | e1833e1f | j_mayer | srr1 = SPR_SRR1; |
1872 | e1833e1f | j_mayer | asrr0 = -1;
|
1873 | e1833e1f | j_mayer | asrr1 = -1;
|
1874 | e1833e1f | j_mayer | msr &= ~((target_ulong)0x783F0000);
|
1875 | 9a64fbe4 | bellard | switch (excp) {
|
1876 | e1833e1f | j_mayer | case POWERPC_EXCP_NONE:
|
1877 | e1833e1f | j_mayer | /* Should never happen */
|
1878 | e1833e1f | j_mayer | return;
|
1879 | e1833e1f | j_mayer | case POWERPC_EXCP_CRITICAL: /* Critical input */ |
1880 | e1833e1f | j_mayer | msr_ri = 0; /* XXX: check this */ |
1881 | e1833e1f | j_mayer | switch (excp_model) {
|
1882 | a750fc0b | j_mayer | case POWERPC_EXCP_40x:
|
1883 | e1833e1f | j_mayer | srr0 = SPR_40x_SRR2; |
1884 | e1833e1f | j_mayer | srr1 = SPR_40x_SRR3; |
1885 | c62db105 | j_mayer | break;
|
1886 | a750fc0b | j_mayer | case POWERPC_EXCP_BOOKE:
|
1887 | e1833e1f | j_mayer | srr0 = SPR_BOOKE_CSRR0; |
1888 | e1833e1f | j_mayer | srr1 = SPR_BOOKE_CSRR1; |
1889 | c62db105 | j_mayer | break;
|
1890 | e1833e1f | j_mayer | case POWERPC_EXCP_G2:
|
1891 | c62db105 | j_mayer | break;
|
1892 | e1833e1f | j_mayer | default:
|
1893 | e1833e1f | j_mayer | goto excp_invalid;
|
1894 | 2be0071f | bellard | } |
1895 | 9a64fbe4 | bellard | goto store_next;
|
1896 | e1833e1f | j_mayer | case POWERPC_EXCP_MCHECK: /* Machine check exception */ |
1897 | e1833e1f | j_mayer | if (msr_me == 0) { |
1898 | e1833e1f | j_mayer | /* Machine check exception is not enabled */
|
1899 | e1833e1f | j_mayer | /* XXX: we may just stop the processor here, to allow debugging */
|
1900 | e1833e1f | j_mayer | excp = POWERPC_EXCP_RESET; |
1901 | e1833e1f | j_mayer | goto excp_reset;
|
1902 | e1833e1f | j_mayer | } |
1903 | e1833e1f | j_mayer | msr_ri = 0;
|
1904 | e1833e1f | j_mayer | msr_me = 0;
|
1905 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
1906 | e1833e1f | j_mayer | msr_hv = 1;
|
1907 | e1833e1f | j_mayer | #endif
|
1908 | e1833e1f | j_mayer | /* XXX: should also have something loaded in DAR / DSISR */
|
1909 | e1833e1f | j_mayer | switch (excp_model) {
|
1910 | a750fc0b | j_mayer | case POWERPC_EXCP_40x:
|
1911 | e1833e1f | j_mayer | srr0 = SPR_40x_SRR2; |
1912 | e1833e1f | j_mayer | srr1 = SPR_40x_SRR3; |
1913 | c62db105 | j_mayer | break;
|
1914 | a750fc0b | j_mayer | case POWERPC_EXCP_BOOKE:
|
1915 | e1833e1f | j_mayer | srr0 = SPR_BOOKE_MCSRR0; |
1916 | e1833e1f | j_mayer | srr1 = SPR_BOOKE_MCSRR1; |
1917 | e1833e1f | j_mayer | asrr0 = SPR_BOOKE_CSRR0; |
1918 | e1833e1f | j_mayer | asrr1 = SPR_BOOKE_CSRR1; |
1919 | c62db105 | j_mayer | break;
|
1920 | c62db105 | j_mayer | default:
|
1921 | c62db105 | j_mayer | break;
|
1922 | 2be0071f | bellard | } |
1923 | e1833e1f | j_mayer | goto store_next;
|
1924 | e1833e1f | j_mayer | case POWERPC_EXCP_DSI: /* Data storage exception */ |
1925 | a541f297 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
1926 | 4a057712 | j_mayer | if (loglevel != 0) { |
1927 | 1b9eb036 | j_mayer | fprintf(logfile, "DSI exception: DSISR=0x" ADDRX" DAR=0x" ADDRX |
1928 | 1b9eb036 | j_mayer | "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
|
1929 | 76a66253 | j_mayer | } |
1930 | a541f297 | bellard | #endif
|
1931 | e1833e1f | j_mayer | msr_ri = 0;
|
1932 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
1933 | e1833e1f | j_mayer | if (lpes1 == 0) |
1934 | e1833e1f | j_mayer | msr_hv = 1;
|
1935 | e1833e1f | j_mayer | #endif
|
1936 | a541f297 | bellard | goto store_next;
|
1937 | e1833e1f | j_mayer | case POWERPC_EXCP_ISI: /* Instruction storage exception */ |
1938 | a541f297 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
1939 | 76a66253 | j_mayer | if (loglevel != 0) { |
1940 | 1b9eb036 | j_mayer | fprintf(logfile, "ISI exception: msr=0x" ADDRX ", nip=0x" ADDRX |
1941 | 1b9eb036 | j_mayer | "\n", msr, env->nip);
|
1942 | 76a66253 | j_mayer | } |
1943 | a541f297 | bellard | #endif
|
1944 | e1833e1f | j_mayer | msr_ri = 0;
|
1945 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
1946 | e1833e1f | j_mayer | if (lpes1 == 0) |
1947 | e1833e1f | j_mayer | msr_hv = 1;
|
1948 | e1833e1f | j_mayer | #endif
|
1949 | e1833e1f | j_mayer | msr |= env->error_code; |
1950 | 9a64fbe4 | bellard | goto store_next;
|
1951 | e1833e1f | j_mayer | case POWERPC_EXCP_EXTERNAL: /* External input */ |
1952 | e1833e1f | j_mayer | msr_ri = 0;
|
1953 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
1954 | e1833e1f | j_mayer | if (lpes0 == 1) |
1955 | e1833e1f | j_mayer | msr_hv = 1;
|
1956 | e1833e1f | j_mayer | #endif
|
1957 | 9a64fbe4 | bellard | goto store_next;
|
1958 | e1833e1f | j_mayer | case POWERPC_EXCP_ALIGN: /* Alignment exception */ |
1959 | e1833e1f | j_mayer | msr_ri = 0;
|
1960 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
1961 | e1833e1f | j_mayer | if (lpes1 == 0) |
1962 | e1833e1f | j_mayer | msr_hv = 1;
|
1963 | e1833e1f | j_mayer | #endif
|
1964 | e1833e1f | j_mayer | /* XXX: this is false */
|
1965 | e1833e1f | j_mayer | /* Get rS/rD and rA from faulting opcode */
|
1966 | e1833e1f | j_mayer | env->spr[SPR_DSISR] |= (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16; |
1967 | 9a64fbe4 | bellard | goto store_current;
|
1968 | e1833e1f | j_mayer | case POWERPC_EXCP_PROGRAM: /* Program exception */ |
1969 | 9a64fbe4 | bellard | switch (env->error_code & ~0xF) { |
1970 | e1833e1f | j_mayer | case POWERPC_EXCP_FP:
|
1971 | e1833e1f | j_mayer | if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) { |
1972 | 9a64fbe4 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
1973 | 4a057712 | j_mayer | if (loglevel != 0) { |
1974 | a496775f | j_mayer | fprintf(logfile, "Ignore floating point exception\n");
|
1975 | a496775f | j_mayer | } |
1976 | 9a64fbe4 | bellard | #endif
|
1977 | 9a64fbe4 | bellard | return;
|
1978 | 76a66253 | j_mayer | } |
1979 | e1833e1f | j_mayer | msr_ri = 0;
|
1980 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
1981 | e1833e1f | j_mayer | if (lpes1 == 0) |
1982 | e1833e1f | j_mayer | msr_hv = 1;
|
1983 | e1833e1f | j_mayer | #endif
|
1984 | 9a64fbe4 | bellard | msr |= 0x00100000;
|
1985 | 9a64fbe4 | bellard | /* Set FX */
|
1986 | 9a64fbe4 | bellard | env->fpscr[7] |= 0x8; |
1987 | 9a64fbe4 | bellard | /* Finally, update FEX */
|
1988 | 9a64fbe4 | bellard | if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) & |
1989 | 9a64fbe4 | bellard | ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3))) |
1990 | 9a64fbe4 | bellard | env->fpscr[7] |= 0x4; |
1991 | e1833e1f | j_mayer | if (msr_fe0 != msr_fe1) {
|
1992 | e1833e1f | j_mayer | msr |= 0x00010000;
|
1993 | e1833e1f | j_mayer | goto store_current;
|
1994 | e1833e1f | j_mayer | } |
1995 | 76a66253 | j_mayer | break;
|
1996 | e1833e1f | j_mayer | case POWERPC_EXCP_INVAL:
|
1997 | a496775f | j_mayer | #if defined (DEBUG_EXCEPTIONS)
|
1998 | 4a057712 | j_mayer | if (loglevel != 0) { |
1999 | a496775f | j_mayer | fprintf(logfile, "Invalid instruction at 0x" ADDRX "\n", |
2000 | a496775f | j_mayer | env->nip); |
2001 | a496775f | j_mayer | } |
2002 | a496775f | j_mayer | #endif
|
2003 | e1833e1f | j_mayer | msr_ri = 0;
|
2004 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2005 | e1833e1f | j_mayer | if (lpes1 == 0) |
2006 | e1833e1f | j_mayer | msr_hv = 1;
|
2007 | e1833e1f | j_mayer | #endif
|
2008 | 9a64fbe4 | bellard | msr |= 0x00080000;
|
2009 | 76a66253 | j_mayer | break;
|
2010 | e1833e1f | j_mayer | case POWERPC_EXCP_PRIV:
|
2011 | e1833e1f | j_mayer | msr_ri = 0;
|
2012 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2013 | e1833e1f | j_mayer | if (lpes1 == 0) |
2014 | e1833e1f | j_mayer | msr_hv = 1;
|
2015 | e1833e1f | j_mayer | #endif
|
2016 | 9a64fbe4 | bellard | msr |= 0x00040000;
|
2017 | 76a66253 | j_mayer | break;
|
2018 | e1833e1f | j_mayer | case POWERPC_EXCP_TRAP:
|
2019 | e1833e1f | j_mayer | msr_ri = 0;
|
2020 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2021 | e1833e1f | j_mayer | if (lpes1 == 0) |
2022 | e1833e1f | j_mayer | msr_hv = 1;
|
2023 | e1833e1f | j_mayer | #endif
|
2024 | 9a64fbe4 | bellard | msr |= 0x00020000;
|
2025 | 9a64fbe4 | bellard | break;
|
2026 | 9a64fbe4 | bellard | default:
|
2027 | 9a64fbe4 | bellard | /* Should never occur */
|
2028 | e1833e1f | j_mayer | cpu_abort(env, "Invalid program exception %d. Aborting\n",
|
2029 | e1833e1f | j_mayer | env->error_code); |
2030 | 76a66253 | j_mayer | break;
|
2031 | 76a66253 | j_mayer | } |
2032 | 9a64fbe4 | bellard | goto store_next;
|
2033 | e1833e1f | j_mayer | case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ |
2034 | e1833e1f | j_mayer | msr_ri = 0;
|
2035 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2036 | e1833e1f | j_mayer | if (lpes1 == 0) |
2037 | e1833e1f | j_mayer | msr_hv = 1;
|
2038 | e1833e1f | j_mayer | #endif
|
2039 | e1833e1f | j_mayer | goto store_current;
|
2040 | e1833e1f | j_mayer | case POWERPC_EXCP_SYSCALL: /* System call exception */ |
2041 | d094807b | bellard | /* NOTE: this is a temporary hack to support graphics OSI
|
2042 | d094807b | bellard | calls from the MOL driver */
|
2043 | e1833e1f | j_mayer | /* XXX: To be removed */
|
2044 | d094807b | bellard | if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b && |
2045 | d094807b | bellard | env->osi_call) { |
2046 | d094807b | bellard | if (env->osi_call(env) != 0) |
2047 | d094807b | bellard | return;
|
2048 | d094807b | bellard | } |
2049 | b769d8fe | bellard | if (loglevel & CPU_LOG_INT) {
|
2050 | d094807b | bellard | dump_syscall(env); |
2051 | b769d8fe | bellard | } |
2052 | e1833e1f | j_mayer | msr_ri = 0;
|
2053 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2054 | e1833e1f | j_mayer | if (lev == 1 || (lpes0 == 0 && lpes1 == 0)) |
2055 | e1833e1f | j_mayer | msr_hv = 1;
|
2056 | e1833e1f | j_mayer | #endif
|
2057 | e1833e1f | j_mayer | goto store_next;
|
2058 | e1833e1f | j_mayer | case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ |
2059 | e1833e1f | j_mayer | msr_ri = 0;
|
2060 | e1833e1f | j_mayer | goto store_current;
|
2061 | e1833e1f | j_mayer | case POWERPC_EXCP_DECR: /* Decrementer exception */ |
2062 | e1833e1f | j_mayer | msr_ri = 0;
|
2063 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2064 | e1833e1f | j_mayer | if (lpes1 == 0) |
2065 | e1833e1f | j_mayer | msr_hv = 1;
|
2066 | e1833e1f | j_mayer | #endif
|
2067 | e1833e1f | j_mayer | goto store_next;
|
2068 | e1833e1f | j_mayer | case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ |
2069 | e1833e1f | j_mayer | /* FIT on 4xx */
|
2070 | e1833e1f | j_mayer | #if defined (DEBUG_EXCEPTIONS)
|
2071 | e1833e1f | j_mayer | if (loglevel != 0) |
2072 | e1833e1f | j_mayer | fprintf(logfile, "FIT exception\n");
|
2073 | e1833e1f | j_mayer | #endif
|
2074 | e1833e1f | j_mayer | msr_ri = 0; /* XXX: check this */ |
2075 | 9a64fbe4 | bellard | goto store_next;
|
2076 | e1833e1f | j_mayer | case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ |
2077 | e1833e1f | j_mayer | #if defined (DEBUG_EXCEPTIONS)
|
2078 | e1833e1f | j_mayer | if (loglevel != 0) |
2079 | e1833e1f | j_mayer | fprintf(logfile, "WDT exception\n");
|
2080 | e1833e1f | j_mayer | #endif
|
2081 | e1833e1f | j_mayer | switch (excp_model) {
|
2082 | e1833e1f | j_mayer | case POWERPC_EXCP_BOOKE:
|
2083 | e1833e1f | j_mayer | srr0 = SPR_BOOKE_CSRR0; |
2084 | e1833e1f | j_mayer | srr1 = SPR_BOOKE_CSRR1; |
2085 | e1833e1f | j_mayer | break;
|
2086 | e1833e1f | j_mayer | default:
|
2087 | e1833e1f | j_mayer | break;
|
2088 | e1833e1f | j_mayer | } |
2089 | e1833e1f | j_mayer | msr_ri = 0; /* XXX: check this */ |
2090 | 2be0071f | bellard | goto store_next;
|
2091 | e1833e1f | j_mayer | case POWERPC_EXCP_DTLB: /* Data TLB error */ |
2092 | e1833e1f | j_mayer | msr_ri = 0; /* XXX: check this */ |
2093 | e1833e1f | j_mayer | goto store_next;
|
2094 | e1833e1f | j_mayer | case POWERPC_EXCP_ITLB: /* Instruction TLB error */ |
2095 | e1833e1f | j_mayer | msr_ri = 0; /* XXX: check this */ |
2096 | e1833e1f | j_mayer | goto store_next;
|
2097 | e1833e1f | j_mayer | case POWERPC_EXCP_DEBUG: /* Debug interrupt */ |
2098 | e1833e1f | j_mayer | switch (excp_model) {
|
2099 | e1833e1f | j_mayer | case POWERPC_EXCP_BOOKE:
|
2100 | e1833e1f | j_mayer | srr0 = SPR_BOOKE_DSRR0; |
2101 | e1833e1f | j_mayer | srr1 = SPR_BOOKE_DSRR1; |
2102 | e1833e1f | j_mayer | asrr0 = SPR_BOOKE_CSRR0; |
2103 | e1833e1f | j_mayer | asrr1 = SPR_BOOKE_CSRR1; |
2104 | e1833e1f | j_mayer | break;
|
2105 | e1833e1f | j_mayer | default:
|
2106 | e1833e1f | j_mayer | break;
|
2107 | e1833e1f | j_mayer | } |
2108 | 2be0071f | bellard | /* XXX: TODO */
|
2109 | e1833e1f | j_mayer | cpu_abort(env, "Debug exception is not implemented yet !\n");
|
2110 | 2be0071f | bellard | goto store_next;
|
2111 | e1833e1f | j_mayer | #if defined(TARGET_PPCEMB)
|
2112 | e1833e1f | j_mayer | case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */ |
2113 | e1833e1f | j_mayer | msr_ri = 0; /* XXX: check this */ |
2114 | e1833e1f | j_mayer | goto store_current;
|
2115 | e1833e1f | j_mayer | case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */ |
2116 | 2be0071f | bellard | /* XXX: TODO */
|
2117 | e1833e1f | j_mayer | cpu_abort(env, "Embedded floating point data exception "
|
2118 | 2be0071f | bellard | "is not implemented yet !\n");
|
2119 | 2be0071f | bellard | goto store_next;
|
2120 | e1833e1f | j_mayer | case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */ |
2121 | 2be0071f | bellard | /* XXX: TODO */
|
2122 | e1833e1f | j_mayer | cpu_abort(env, "Embedded floating point round exception "
|
2123 | e1833e1f | j_mayer | "is not implemented yet !\n");
|
2124 | 9a64fbe4 | bellard | goto store_next;
|
2125 | e1833e1f | j_mayer | case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */ |
2126 | e1833e1f | j_mayer | msr_ri = 0;
|
2127 | 2be0071f | bellard | /* XXX: TODO */
|
2128 | 2be0071f | bellard | cpu_abort(env, |
2129 | e1833e1f | j_mayer | "Performance counter exception is not implemented yet !\n");
|
2130 | 9a64fbe4 | bellard | goto store_next;
|
2131 | e1833e1f | j_mayer | case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ |
2132 | 76a66253 | j_mayer | /* XXX: TODO */
|
2133 | e1833e1f | j_mayer | cpu_abort(env, |
2134 | e1833e1f | j_mayer | "Embedded doorbell interrupt is not implemented yet !\n");
|
2135 | 2be0071f | bellard | goto store_next;
|
2136 | e1833e1f | j_mayer | case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */ |
2137 | e1833e1f | j_mayer | switch (excp_model) {
|
2138 | e1833e1f | j_mayer | case POWERPC_EXCP_BOOKE:
|
2139 | e1833e1f | j_mayer | srr0 = SPR_BOOKE_CSRR0; |
2140 | e1833e1f | j_mayer | srr1 = SPR_BOOKE_CSRR1; |
2141 | a750fc0b | j_mayer | break;
|
2142 | 2be0071f | bellard | default:
|
2143 | 2be0071f | bellard | break;
|
2144 | 2be0071f | bellard | } |
2145 | e1833e1f | j_mayer | /* XXX: TODO */
|
2146 | e1833e1f | j_mayer | cpu_abort(env, "Embedded doorbell critical interrupt "
|
2147 | e1833e1f | j_mayer | "is not implemented yet !\n");
|
2148 | e1833e1f | j_mayer | goto store_next;
|
2149 | e1833e1f | j_mayer | #endif /* defined(TARGET_PPCEMB) */ |
2150 | e1833e1f | j_mayer | case POWERPC_EXCP_RESET: /* System reset exception */ |
2151 | e1833e1f | j_mayer | msr_ri = 0;
|
2152 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2153 | e1833e1f | j_mayer | msr_hv = 1;
|
2154 | e1833e1f | j_mayer | #endif
|
2155 | e1833e1f | j_mayer | excp_reset:
|
2156 | e1833e1f | j_mayer | goto store_next;
|
2157 | e1833e1f | j_mayer | #if defined(TARGET_PPC64)
|
2158 | e1833e1f | j_mayer | case POWERPC_EXCP_DSEG: /* Data segment exception */ |
2159 | e1833e1f | j_mayer | msr_ri = 0;
|
2160 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2161 | e1833e1f | j_mayer | if (lpes1 == 0) |
2162 | e1833e1f | j_mayer | msr_hv = 1;
|
2163 | e1833e1f | j_mayer | #endif
|
2164 | e1833e1f | j_mayer | /* XXX: TODO */
|
2165 | e1833e1f | j_mayer | cpu_abort(env, "Data segment exception is not implemented yet !\n");
|
2166 | e1833e1f | j_mayer | goto store_next;
|
2167 | e1833e1f | j_mayer | case POWERPC_EXCP_ISEG: /* Instruction segment exception */ |
2168 | e1833e1f | j_mayer | msr_ri = 0;
|
2169 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2170 | e1833e1f | j_mayer | if (lpes1 == 0) |
2171 | e1833e1f | j_mayer | msr_hv = 1;
|
2172 | e1833e1f | j_mayer | #endif
|
2173 | e1833e1f | j_mayer | /* XXX: TODO */
|
2174 | e1833e1f | j_mayer | cpu_abort(env, |
2175 | e1833e1f | j_mayer | "Instruction segment exception is not implemented yet !\n");
|
2176 | e1833e1f | j_mayer | goto store_next;
|
2177 | e1833e1f | j_mayer | #endif /* defined(TARGET_PPC64) */ |
2178 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2179 | e1833e1f | j_mayer | case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ |
2180 | e1833e1f | j_mayer | srr0 = SPR_HSRR0; |
2181 | e1833e1f | j_mayer | srr1 = SPR_HSSR1; |
2182 | e1833e1f | j_mayer | msr_hv = 1;
|
2183 | e1833e1f | j_mayer | goto store_next;
|
2184 | e1833e1f | j_mayer | #endif
|
2185 | e1833e1f | j_mayer | case POWERPC_EXCP_TRACE: /* Trace exception */ |
2186 | e1833e1f | j_mayer | msr_ri = 0;
|
2187 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2188 | e1833e1f | j_mayer | if (lpes1 == 0) |
2189 | e1833e1f | j_mayer | msr_hv = 1;
|
2190 | e1833e1f | j_mayer | #endif
|
2191 | e1833e1f | j_mayer | goto store_next;
|
2192 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2193 | e1833e1f | j_mayer | case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ |
2194 | e1833e1f | j_mayer | srr0 = SPR_HSRR0; |
2195 | e1833e1f | j_mayer | srr1 = SPR_HSSR1; |
2196 | e1833e1f | j_mayer | msr_hv = 1;
|
2197 | e1833e1f | j_mayer | goto store_next;
|
2198 | e1833e1f | j_mayer | case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */ |
2199 | e1833e1f | j_mayer | srr0 = SPR_HSRR0; |
2200 | e1833e1f | j_mayer | srr1 = SPR_HSSR1; |
2201 | e1833e1f | j_mayer | msr_hv = 1;
|
2202 | e1833e1f | j_mayer | /* XXX: TODO */
|
2203 | e1833e1f | j_mayer | cpu_abort(env, "Hypervisor instruction storage exception "
|
2204 | e1833e1f | j_mayer | "is not implemented yet !\n");
|
2205 | e1833e1f | j_mayer | goto store_next;
|
2206 | e1833e1f | j_mayer | case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */ |
2207 | e1833e1f | j_mayer | srr0 = SPR_HSRR0; |
2208 | e1833e1f | j_mayer | srr1 = SPR_HSSR1; |
2209 | e1833e1f | j_mayer | msr_hv = 1;
|
2210 | e1833e1f | j_mayer | goto store_next;
|
2211 | e1833e1f | j_mayer | case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */ |
2212 | e1833e1f | j_mayer | srr0 = SPR_HSRR0; |
2213 | e1833e1f | j_mayer | srr1 = SPR_HSSR1; |
2214 | e1833e1f | j_mayer | msr_hv = 1;
|
2215 | e1833e1f | j_mayer | goto store_next;
|
2216 | e1833e1f | j_mayer | #endif /* defined(TARGET_PPC64H) */ |
2217 | e1833e1f | j_mayer | case POWERPC_EXCP_VPU: /* Vector unavailable exception */ |
2218 | e1833e1f | j_mayer | msr_ri = 0;
|
2219 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2220 | e1833e1f | j_mayer | if (lpes1 == 0) |
2221 | e1833e1f | j_mayer | msr_hv = 1;
|
2222 | e1833e1f | j_mayer | #endif
|
2223 | e1833e1f | j_mayer | goto store_current;
|
2224 | e1833e1f | j_mayer | case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */ |
2225 | a496775f | j_mayer | #if defined (DEBUG_EXCEPTIONS)
|
2226 | e1833e1f | j_mayer | if (loglevel != 0) |
2227 | e1833e1f | j_mayer | fprintf(logfile, "PIT exception\n");
|
2228 | e1833e1f | j_mayer | #endif
|
2229 | e1833e1f | j_mayer | msr_ri = 0; /* XXX: check this */ |
2230 | e1833e1f | j_mayer | goto store_next;
|
2231 | e1833e1f | j_mayer | case POWERPC_EXCP_IO: /* IO error exception */ |
2232 | e1833e1f | j_mayer | /* XXX: TODO */
|
2233 | e1833e1f | j_mayer | cpu_abort(env, "601 IO error exception is not implemented yet !\n");
|
2234 | e1833e1f | j_mayer | goto store_next;
|
2235 | e1833e1f | j_mayer | case POWERPC_EXCP_RUNM: /* Run mode exception */ |
2236 | e1833e1f | j_mayer | /* XXX: TODO */
|
2237 | e1833e1f | j_mayer | cpu_abort(env, "601 run mode exception is not implemented yet !\n");
|
2238 | e1833e1f | j_mayer | goto store_next;
|
2239 | e1833e1f | j_mayer | case POWERPC_EXCP_EMUL: /* Emulation trap exception */ |
2240 | e1833e1f | j_mayer | /* XXX: TODO */
|
2241 | e1833e1f | j_mayer | cpu_abort(env, "602 emulation trap exception "
|
2242 | e1833e1f | j_mayer | "is not implemented yet !\n");
|
2243 | e1833e1f | j_mayer | goto store_next;
|
2244 | e1833e1f | j_mayer | case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ |
2245 | e1833e1f | j_mayer | msr_ri = 0; /* XXX: check this */ |
2246 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H) /* XXX: check this */ |
2247 | e1833e1f | j_mayer | if (lpes1 == 0) |
2248 | e1833e1f | j_mayer | msr_hv = 1;
|
2249 | a496775f | j_mayer | #endif
|
2250 | e1833e1f | j_mayer | switch (excp_model) {
|
2251 | a750fc0b | j_mayer | case POWERPC_EXCP_602:
|
2252 | a750fc0b | j_mayer | case POWERPC_EXCP_603:
|
2253 | a750fc0b | j_mayer | case POWERPC_EXCP_603E:
|
2254 | a750fc0b | j_mayer | case POWERPC_EXCP_G2:
|
2255 | e1833e1f | j_mayer | goto tlb_miss_tgpr;
|
2256 | a750fc0b | j_mayer | case POWERPC_EXCP_7x5:
|
2257 | 76a66253 | j_mayer | goto tlb_miss;
|
2258 | 2be0071f | bellard | default:
|
2259 | e1833e1f | j_mayer | cpu_abort(env, "Invalid instruction TLB miss exception\n");
|
2260 | 2be0071f | bellard | break;
|
2261 | 2be0071f | bellard | } |
2262 | e1833e1f | j_mayer | break;
|
2263 | e1833e1f | j_mayer | case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ |
2264 | e1833e1f | j_mayer | msr_ri = 0; /* XXX: check this */ |
2265 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H) /* XXX: check this */ |
2266 | e1833e1f | j_mayer | if (lpes1 == 0) |
2267 | e1833e1f | j_mayer | msr_hv = 1;
|
2268 | a496775f | j_mayer | #endif
|
2269 | e1833e1f | j_mayer | switch (excp_model) {
|
2270 | a750fc0b | j_mayer | case POWERPC_EXCP_602:
|
2271 | a750fc0b | j_mayer | case POWERPC_EXCP_603:
|
2272 | a750fc0b | j_mayer | case POWERPC_EXCP_603E:
|
2273 | a750fc0b | j_mayer | case POWERPC_EXCP_G2:
|
2274 | e1833e1f | j_mayer | goto tlb_miss_tgpr;
|
2275 | a750fc0b | j_mayer | case POWERPC_EXCP_7x5:
|
2276 | 76a66253 | j_mayer | goto tlb_miss;
|
2277 | 2be0071f | bellard | default:
|
2278 | e1833e1f | j_mayer | cpu_abort(env, "Invalid data load TLB miss exception\n");
|
2279 | 2be0071f | bellard | break;
|
2280 | 2be0071f | bellard | } |
2281 | e1833e1f | j_mayer | break;
|
2282 | e1833e1f | j_mayer | case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ |
2283 | e1833e1f | j_mayer | msr_ri = 0; /* XXX: check this */ |
2284 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H) /* XXX: check this */ |
2285 | e1833e1f | j_mayer | if (lpes1 == 0) |
2286 | e1833e1f | j_mayer | msr_hv = 1;
|
2287 | e1833e1f | j_mayer | #endif
|
2288 | e1833e1f | j_mayer | switch (excp_model) {
|
2289 | a750fc0b | j_mayer | case POWERPC_EXCP_602:
|
2290 | a750fc0b | j_mayer | case POWERPC_EXCP_603:
|
2291 | a750fc0b | j_mayer | case POWERPC_EXCP_603E:
|
2292 | a750fc0b | j_mayer | case POWERPC_EXCP_G2:
|
2293 | e1833e1f | j_mayer | tlb_miss_tgpr:
|
2294 | 76a66253 | j_mayer | /* Swap temporary saved registers with GPRs */
|
2295 | 76a66253 | j_mayer | swap_gpr_tgpr(env); |
2296 | 76a66253 | j_mayer | msr_tgpr = 1;
|
2297 | e1833e1f | j_mayer | goto tlb_miss;
|
2298 | e1833e1f | j_mayer | case POWERPC_EXCP_7x5:
|
2299 | e1833e1f | j_mayer | tlb_miss:
|
2300 | 2be0071f | bellard | #if defined (DEBUG_SOFTWARE_TLB)
|
2301 | 2be0071f | bellard | if (loglevel != 0) { |
2302 | 76a66253 | j_mayer | const unsigned char *es; |
2303 | 76a66253 | j_mayer | target_ulong *miss, *cmp; |
2304 | 76a66253 | j_mayer | int en;
|
2305 | 76a66253 | j_mayer | if (excp == 0x1000) { |
2306 | 76a66253 | j_mayer | es = "I";
|
2307 | 76a66253 | j_mayer | en = 'I';
|
2308 | 76a66253 | j_mayer | miss = &env->spr[SPR_IMISS]; |
2309 | 76a66253 | j_mayer | cmp = &env->spr[SPR_ICMP]; |
2310 | 76a66253 | j_mayer | } else {
|
2311 | 76a66253 | j_mayer | if (excp == 0x1100) |
2312 | 76a66253 | j_mayer | es = "DL";
|
2313 | 76a66253 | j_mayer | else
|
2314 | 76a66253 | j_mayer | es = "DS";
|
2315 | 76a66253 | j_mayer | en = 'D';
|
2316 | 76a66253 | j_mayer | miss = &env->spr[SPR_DMISS]; |
2317 | 76a66253 | j_mayer | cmp = &env->spr[SPR_DCMP]; |
2318 | 76a66253 | j_mayer | } |
2319 | 1b9eb036 | j_mayer | fprintf(logfile, "6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX |
2320 | 4a057712 | j_mayer | " H1 " ADDRX " H2 " ADDRX " %08x\n", |
2321 | 1b9eb036 | j_mayer | es, en, *miss, en, *cmp, |
2322 | 76a66253 | j_mayer | env->spr[SPR_HASH1], env->spr[SPR_HASH2], |
2323 | 2be0071f | bellard | env->error_code); |
2324 | 2be0071f | bellard | } |
2325 | 9a64fbe4 | bellard | #endif
|
2326 | 2be0071f | bellard | msr |= env->crf[0] << 28; |
2327 | 2be0071f | bellard | msr |= env->error_code; /* key, D/I, S/L bits */
|
2328 | 2be0071f | bellard | /* Set way using a LRU mechanism */
|
2329 | 76a66253 | j_mayer | msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17; |
2330 | c62db105 | j_mayer | break;
|
2331 | 2be0071f | bellard | default:
|
2332 | e1833e1f | j_mayer | cpu_abort(env, "Invalid data store TLB miss exception\n");
|
2333 | 2be0071f | bellard | break;
|
2334 | 2be0071f | bellard | } |
2335 | e1833e1f | j_mayer | goto store_next;
|
2336 | e1833e1f | j_mayer | case POWERPC_EXCP_FPA: /* Floating-point assist exception */ |
2337 | e1833e1f | j_mayer | /* XXX: TODO */
|
2338 | e1833e1f | j_mayer | cpu_abort(env, "Floating point assist exception "
|
2339 | e1833e1f | j_mayer | "is not implemented yet !\n");
|
2340 | e1833e1f | j_mayer | goto store_next;
|
2341 | e1833e1f | j_mayer | case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ |
2342 | e1833e1f | j_mayer | /* XXX: TODO */
|
2343 | e1833e1f | j_mayer | cpu_abort(env, "IABR exception is not implemented yet !\n");
|
2344 | e1833e1f | j_mayer | goto store_next;
|
2345 | e1833e1f | j_mayer | case POWERPC_EXCP_SMI: /* System management interrupt */ |
2346 | e1833e1f | j_mayer | /* XXX: TODO */
|
2347 | e1833e1f | j_mayer | cpu_abort(env, "SMI exception is not implemented yet !\n");
|
2348 | e1833e1f | j_mayer | goto store_next;
|
2349 | e1833e1f | j_mayer | case POWERPC_EXCP_THERM: /* Thermal interrupt */ |
2350 | e1833e1f | j_mayer | /* XXX: TODO */
|
2351 | e1833e1f | j_mayer | cpu_abort(env, "Thermal management exception "
|
2352 | e1833e1f | j_mayer | "is not implemented yet !\n");
|
2353 | e1833e1f | j_mayer | goto store_next;
|
2354 | e1833e1f | j_mayer | case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */ |
2355 | e1833e1f | j_mayer | msr_ri = 0;
|
2356 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2357 | e1833e1f | j_mayer | if (lpes1 == 0) |
2358 | e1833e1f | j_mayer | msr_hv = 1;
|
2359 | e1833e1f | j_mayer | #endif
|
2360 | e1833e1f | j_mayer | /* XXX: TODO */
|
2361 | e1833e1f | j_mayer | cpu_abort(env, |
2362 | e1833e1f | j_mayer | "Performance counter exception is not implemented yet !\n");
|
2363 | e1833e1f | j_mayer | goto store_next;
|
2364 | e1833e1f | j_mayer | case POWERPC_EXCP_VPUA: /* Vector assist exception */ |
2365 | e1833e1f | j_mayer | /* XXX: TODO */
|
2366 | e1833e1f | j_mayer | cpu_abort(env, "VPU assist exception is not implemented yet !\n");
|
2367 | e1833e1f | j_mayer | goto store_next;
|
2368 | e1833e1f | j_mayer | case POWERPC_EXCP_SOFTP: /* Soft patch exception */ |
2369 | e1833e1f | j_mayer | /* XXX: TODO */
|
2370 | e1833e1f | j_mayer | cpu_abort(env, |
2371 | e1833e1f | j_mayer | "970 soft-patch exception is not implemented yet !\n");
|
2372 | e1833e1f | j_mayer | goto store_next;
|
2373 | e1833e1f | j_mayer | case POWERPC_EXCP_MAINT: /* Maintenance exception */ |
2374 | e1833e1f | j_mayer | /* XXX: TODO */
|
2375 | e1833e1f | j_mayer | cpu_abort(env, |
2376 | e1833e1f | j_mayer | "970 maintenance exception is not implemented yet !\n");
|
2377 | e1833e1f | j_mayer | goto store_next;
|
2378 | 2be0071f | bellard | default:
|
2379 | e1833e1f | j_mayer | excp_invalid:
|
2380 | e1833e1f | j_mayer | cpu_abort(env, "Invalid PowerPC exception %d. Aborting\n", excp);
|
2381 | e1833e1f | j_mayer | break;
|
2382 | 9a64fbe4 | bellard | store_current:
|
2383 | 2be0071f | bellard | /* save current instruction location */
|
2384 | e1833e1f | j_mayer | env->spr[srr0] = env->nip - 4;
|
2385 | 9a64fbe4 | bellard | break;
|
2386 | 9a64fbe4 | bellard | store_next:
|
2387 | 2be0071f | bellard | /* save next instruction location */
|
2388 | e1833e1f | j_mayer | env->spr[srr0] = env->nip; |
2389 | 9a64fbe4 | bellard | break;
|
2390 | 9a64fbe4 | bellard | } |
2391 | e1833e1f | j_mayer | /* Save MSR */
|
2392 | e1833e1f | j_mayer | env->spr[srr1] = msr; |
2393 | e1833e1f | j_mayer | /* If any alternate SRR register are defined, duplicate saved values */
|
2394 | e1833e1f | j_mayer | if (asrr0 != -1) |
2395 | e1833e1f | j_mayer | env->spr[asrr0] = env->spr[srr0]; |
2396 | e1833e1f | j_mayer | if (asrr1 != -1) |
2397 | e1833e1f | j_mayer | env->spr[asrr1] = env->spr[srr1]; |
2398 | 2be0071f | bellard | /* If we disactivated any translation, flush TLBs */
|
2399 | e1833e1f | j_mayer | if (msr_ir || msr_dr)
|
2400 | 2be0071f | bellard | tlb_flush(env, 1);
|
2401 | 9a64fbe4 | bellard | /* reload MSR with correct bits */
|
2402 | 9a64fbe4 | bellard | msr_ee = 0;
|
2403 | 9a64fbe4 | bellard | msr_pr = 0;
|
2404 | 9a64fbe4 | bellard | msr_fp = 0;
|
2405 | 9a64fbe4 | bellard | msr_fe0 = 0;
|
2406 | 9a64fbe4 | bellard | msr_se = 0;
|
2407 | 9a64fbe4 | bellard | msr_be = 0;
|
2408 | 9a64fbe4 | bellard | msr_fe1 = 0;
|
2409 | 9a64fbe4 | bellard | msr_ir = 0;
|
2410 | 9a64fbe4 | bellard | msr_dr = 0;
|
2411 | e1833e1f | j_mayer | #if 0 /* Fix this: not on all targets */
|
2412 | e1833e1f | j_mayer | msr_pmm = 0;
|
2413 | e1833e1f | j_mayer | #endif
|
2414 | 9a64fbe4 | bellard | msr_le = msr_ile; |
2415 | e1833e1f | j_mayer | do_compute_hflags(env); |
2416 | e1833e1f | j_mayer | /* Jump to handler */
|
2417 | e1833e1f | j_mayer | vector = env->excp_vectors[excp]; |
2418 | e1833e1f | j_mayer | if (vector == (target_ulong)-1) { |
2419 | e1833e1f | j_mayer | cpu_abort(env, "Raised an exception without defined vector %d\n",
|
2420 | e1833e1f | j_mayer | excp); |
2421 | e1833e1f | j_mayer | } |
2422 | e1833e1f | j_mayer | vector |= env->excp_prefix; |
2423 | c62db105 | j_mayer | #if defined(TARGET_PPC64)
|
2424 | e1833e1f | j_mayer | if (excp_model == POWERPC_EXCP_BOOKE) {
|
2425 | e1833e1f | j_mayer | msr_cm = msr_icm; |
2426 | e1833e1f | j_mayer | if (!msr_cm)
|
2427 | e1833e1f | j_mayer | vector = (uint32_t)vector; |
2428 | c62db105 | j_mayer | } else {
|
2429 | c62db105 | j_mayer | msr_sf = msr_isf; |
2430 | e1833e1f | j_mayer | if (!msr_sf)
|
2431 | e1833e1f | j_mayer | vector = (uint32_t)vector; |
2432 | c62db105 | j_mayer | } |
2433 | e1833e1f | j_mayer | #endif
|
2434 | e1833e1f | j_mayer | env->nip = vector; |
2435 | e1833e1f | j_mayer | /* Reset exception state */
|
2436 | e1833e1f | j_mayer | env->exception_index = POWERPC_EXCP_NONE; |
2437 | e1833e1f | j_mayer | env->error_code = 0;
|
2438 | fb0eaffc | bellard | } |
2439 | 47103572 | j_mayer | |
2440 | e1833e1f | j_mayer | void do_interrupt (CPUState *env)
|
2441 | 47103572 | j_mayer | { |
2442 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, env->exception_index); |
2443 | e1833e1f | j_mayer | } |
2444 | 47103572 | j_mayer | |
2445 | e1833e1f | j_mayer | void ppc_hw_interrupt (CPUPPCState *env)
|
2446 | e1833e1f | j_mayer | { |
2447 | a496775f | j_mayer | #if 1 |
2448 | a496775f | j_mayer | if (loglevel & CPU_LOG_INT) {
|
2449 | a496775f | j_mayer | fprintf(logfile, "%s: %p pending %08x req %08x me %d ee %d\n",
|
2450 | a496775f | j_mayer | __func__, env, env->pending_interrupts, |
2451 | a496775f | j_mayer | env->interrupt_request, msr_me, msr_ee); |
2452 | a496775f | j_mayer | } |
2453 | 47103572 | j_mayer | #endif
|
2454 | e1833e1f | j_mayer | /* External reset */
|
2455 | 47103572 | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) { |
2456 | 47103572 | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
|
2457 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_RESET); |
2458 | e1833e1f | j_mayer | return;
|
2459 | e1833e1f | j_mayer | } |
2460 | e1833e1f | j_mayer | /* Machine check exception */
|
2461 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) { |
2462 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
|
2463 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_MCHECK); |
2464 | e1833e1f | j_mayer | return;
|
2465 | 47103572 | j_mayer | } |
2466 | e1833e1f | j_mayer | #if 0 /* TODO */
|
2467 | e1833e1f | j_mayer | /* External debug exception */
|
2468 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
|
2469 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
|
2470 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DEBUG);
|
2471 | e1833e1f | j_mayer | return;
|
2472 | e1833e1f | j_mayer | }
|
2473 | e1833e1f | j_mayer | #endif
|
2474 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2475 | e1833e1f | j_mayer | if ((msr_ee != 0 || msr_hv == 0 || msr_pr == 1) & hdice != 0) { |
2476 | 47103572 | j_mayer | /* Hypervisor decrementer exception */
|
2477 | 47103572 | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) { |
2478 | 47103572 | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
|
2479 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_HDECR); |
2480 | e1833e1f | j_mayer | return;
|
2481 | e1833e1f | j_mayer | } |
2482 | e1833e1f | j_mayer | } |
2483 | e1833e1f | j_mayer | #endif
|
2484 | e1833e1f | j_mayer | if (msr_ce != 0) { |
2485 | e1833e1f | j_mayer | /* External critical interrupt */
|
2486 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) { |
2487 | e1833e1f | j_mayer | /* Taking a critical external interrupt does not clear the external
|
2488 | e1833e1f | j_mayer | * critical interrupt status
|
2489 | e1833e1f | j_mayer | */
|
2490 | e1833e1f | j_mayer | #if 0
|
2491 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CEXT);
|
2492 | 47103572 | j_mayer | #endif
|
2493 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_CRITICAL); |
2494 | e1833e1f | j_mayer | return;
|
2495 | e1833e1f | j_mayer | } |
2496 | e1833e1f | j_mayer | } |
2497 | e1833e1f | j_mayer | if (msr_ee != 0) { |
2498 | e1833e1f | j_mayer | /* Watchdog timer on embedded PowerPC */
|
2499 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) { |
2500 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
|
2501 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_WDT); |
2502 | e1833e1f | j_mayer | return;
|
2503 | e1833e1f | j_mayer | } |
2504 | e1833e1f | j_mayer | #if defined(TARGET_PPCEMB)
|
2505 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) { |
2506 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL);
|
2507 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORCI); |
2508 | e1833e1f | j_mayer | return;
|
2509 | e1833e1f | j_mayer | } |
2510 | e1833e1f | j_mayer | #endif
|
2511 | e1833e1f | j_mayer | #if defined(TARGET_PPCEMB)
|
2512 | e1833e1f | j_mayer | /* External interrupt */
|
2513 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) { |
2514 | e1833e1f | j_mayer | /* Taking an external interrupt does not clear the external
|
2515 | e1833e1f | j_mayer | * interrupt status
|
2516 | e1833e1f | j_mayer | */
|
2517 | e1833e1f | j_mayer | #if 0
|
2518 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
|
2519 | e1833e1f | j_mayer | #endif
|
2520 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL); |
2521 | e1833e1f | j_mayer | return;
|
2522 | e1833e1f | j_mayer | } |
2523 | e1833e1f | j_mayer | #endif
|
2524 | e1833e1f | j_mayer | /* Fixed interval timer on embedded PowerPC */
|
2525 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) { |
2526 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
|
2527 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_FIT); |
2528 | e1833e1f | j_mayer | return;
|
2529 | e1833e1f | j_mayer | } |
2530 | e1833e1f | j_mayer | /* Programmable interval timer on embedded PowerPC */
|
2531 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) { |
2532 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
|
2533 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_PIT); |
2534 | e1833e1f | j_mayer | return;
|
2535 | e1833e1f | j_mayer | } |
2536 | 47103572 | j_mayer | /* Decrementer exception */
|
2537 | 47103572 | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) { |
2538 | 47103572 | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
|
2539 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DECR); |
2540 | e1833e1f | j_mayer | return;
|
2541 | e1833e1f | j_mayer | } |
2542 | e1833e1f | j_mayer | #if !defined(TARGET_PPCEMB)
|
2543 | 47103572 | j_mayer | /* External interrupt */
|
2544 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) { |
2545 | e9df014c | j_mayer | /* Taking an external interrupt does not clear the external
|
2546 | e9df014c | j_mayer | * interrupt status
|
2547 | e9df014c | j_mayer | */
|
2548 | e9df014c | j_mayer | #if 0
|
2549 | 47103572 | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
|
2550 | e9df014c | j_mayer | #endif
|
2551 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL); |
2552 | e1833e1f | j_mayer | return;
|
2553 | e1833e1f | j_mayer | } |
2554 | d0dfae6e | j_mayer | #endif
|
2555 | e1833e1f | j_mayer | #if defined(TARGET_PPCEMB)
|
2556 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) { |
2557 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
|
2558 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORI); |
2559 | e1833e1f | j_mayer | return;
|
2560 | 47103572 | j_mayer | } |
2561 | 47103572 | j_mayer | #endif
|
2562 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) { |
2563 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM);
|
2564 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_PERFM); |
2565 | e1833e1f | j_mayer | return;
|
2566 | e1833e1f | j_mayer | } |
2567 | e1833e1f | j_mayer | /* Thermal interrupt */
|
2568 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) { |
2569 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
|
2570 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_THERM); |
2571 | e1833e1f | j_mayer | return;
|
2572 | e1833e1f | j_mayer | } |
2573 | 47103572 | j_mayer | } |
2574 | 47103572 | j_mayer | } |
2575 | 18fba28c | bellard | #endif /* !CONFIG_USER_ONLY */ |
2576 | a496775f | j_mayer | |
2577 | a496775f | j_mayer | void cpu_dump_EA (target_ulong EA)
|
2578 | a496775f | j_mayer | { |
2579 | a496775f | j_mayer | FILE *f; |
2580 | a496775f | j_mayer | |
2581 | a496775f | j_mayer | if (logfile) {
|
2582 | a496775f | j_mayer | f = logfile; |
2583 | a496775f | j_mayer | } else {
|
2584 | a496775f | j_mayer | f = stdout; |
2585 | a496775f | j_mayer | return;
|
2586 | a496775f | j_mayer | } |
2587 | 4a057712 | j_mayer | fprintf(f, "Memory access at address " ADDRX "\n", EA); |
2588 | 4a057712 | j_mayer | } |
2589 | 4a057712 | j_mayer | |
2590 | 4a057712 | j_mayer | void cpu_dump_rfi (target_ulong RA, target_ulong msr)
|
2591 | 4a057712 | j_mayer | { |
2592 | 4a057712 | j_mayer | FILE *f; |
2593 | 4a057712 | j_mayer | |
2594 | 4a057712 | j_mayer | if (logfile) {
|
2595 | 4a057712 | j_mayer | f = logfile; |
2596 | 4a057712 | j_mayer | } else {
|
2597 | 4a057712 | j_mayer | f = stdout; |
2598 | 4a057712 | j_mayer | return;
|
2599 | 4a057712 | j_mayer | } |
2600 | 4a057712 | j_mayer | fprintf(f, "Return from exception at " ADDRX " with flags " ADDRX "\n", |
2601 | 4a057712 | j_mayer | RA, msr); |
2602 | a496775f | j_mayer | } |
2603 | a496775f | j_mayer | |
2604 | 0a032cbe | j_mayer | void cpu_ppc_reset (void *opaque) |
2605 | 0a032cbe | j_mayer | { |
2606 | 0a032cbe | j_mayer | CPUPPCState *env; |
2607 | 5eb7995e | j_mayer | int i;
|
2608 | 0a032cbe | j_mayer | |
2609 | 0a032cbe | j_mayer | env = opaque; |
2610 | 5eb7995e | j_mayer | /* XXX: some of those flags initialisation values could depend
|
2611 | 5eb7995e | j_mayer | * on the actual PowerPC implementation
|
2612 | 5eb7995e | j_mayer | */
|
2613 | 5eb7995e | j_mayer | for (i = 0; i < 63; i++) |
2614 | 5eb7995e | j_mayer | env->msr[i] = 0;
|
2615 | 5eb7995e | j_mayer | #if defined(TARGET_PPC64)
|
2616 | 5eb7995e | j_mayer | msr_hv = 0; /* Should be 1... */ |
2617 | 5eb7995e | j_mayer | #endif
|
2618 | 5eb7995e | j_mayer | msr_ap = 0; /* TO BE CHECKED */ |
2619 | 5eb7995e | j_mayer | msr_sa = 0; /* TO BE CHECKED */ |
2620 | 5eb7995e | j_mayer | msr_ip = 0; /* TO BE CHECKED */ |
2621 | 0a032cbe | j_mayer | #if defined (DO_SINGLE_STEP) && 0 |
2622 | 0a032cbe | j_mayer | /* Single step trace mode */
|
2623 | 0a032cbe | j_mayer | msr_se = 1;
|
2624 | 0a032cbe | j_mayer | msr_be = 1;
|
2625 | 0a032cbe | j_mayer | #endif
|
2626 | 0a032cbe | j_mayer | #if defined(CONFIG_USER_ONLY)
|
2627 | 5eb7995e | j_mayer | msr_fp = 1; /* Allow floating point exceptions */ |
2628 | 0a032cbe | j_mayer | msr_pr = 1;
|
2629 | 0a032cbe | j_mayer | #else
|
2630 | 0a032cbe | j_mayer | env->nip = 0xFFFFFFFC;
|
2631 | 0a032cbe | j_mayer | ppc_tlb_invalidate_all(env); |
2632 | 0a032cbe | j_mayer | #endif
|
2633 | 0a032cbe | j_mayer | do_compute_hflags(env); |
2634 | 0a032cbe | j_mayer | env->reserve = -1;
|
2635 | 5eb7995e | j_mayer | /* Be sure no exception or interrupt is pending */
|
2636 | 5eb7995e | j_mayer | env->pending_interrupts = 0;
|
2637 | e1833e1f | j_mayer | env->exception_index = POWERPC_EXCP_NONE; |
2638 | e1833e1f | j_mayer | env->error_code = 0;
|
2639 | 5eb7995e | j_mayer | /* Flush all TLBs */
|
2640 | 5eb7995e | j_mayer | tlb_flush(env, 1);
|
2641 | 0a032cbe | j_mayer | } |
2642 | 0a032cbe | j_mayer | |
2643 | 0a032cbe | j_mayer | CPUPPCState *cpu_ppc_init (void)
|
2644 | 0a032cbe | j_mayer | { |
2645 | 0a032cbe | j_mayer | CPUPPCState *env; |
2646 | 0a032cbe | j_mayer | |
2647 | 0a032cbe | j_mayer | env = qemu_mallocz(sizeof(CPUPPCState));
|
2648 | 0a032cbe | j_mayer | if (!env)
|
2649 | 0a032cbe | j_mayer | return NULL; |
2650 | 0a032cbe | j_mayer | cpu_exec_init(env); |
2651 | 0a032cbe | j_mayer | cpu_ppc_reset(env); |
2652 | 0a032cbe | j_mayer | |
2653 | 0a032cbe | j_mayer | return env;
|
2654 | 0a032cbe | j_mayer | } |
2655 | 0a032cbe | j_mayer | |
2656 | 0a032cbe | j_mayer | void cpu_ppc_close (CPUPPCState *env)
|
2657 | 0a032cbe | j_mayer | { |
2658 | 0a032cbe | j_mayer | /* Should also remove all opcode tables... */
|
2659 | 0a032cbe | j_mayer | free(env); |
2660 | 0a032cbe | j_mayer | } |