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1 | 3475187d | bellard | /*
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2 | c7ba218d | blueswir1 | * QEMU Sun4u/Sun4v System Emulator
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3 | 5fafdf24 | ths | *
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4 | 3475187d | bellard | * Copyright (c) 2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 3475187d | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 3475187d | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 3475187d | bellard | * in the Software without restriction, including without limitation the rights
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9 | 3475187d | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 3475187d | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 3475187d | bellard | * furnished to do so, subject to the following conditions:
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12 | 3475187d | bellard | *
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13 | 3475187d | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 3475187d | bellard | * all copies or substantial portions of the Software.
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15 | 3475187d | bellard | *
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16 | 3475187d | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 3475187d | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 3475187d | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 3475187d | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 3475187d | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 3475187d | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 3475187d | bellard | * THE SOFTWARE.
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23 | 3475187d | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "pci.h" |
26 | 18e08a55 | Michael S. Tsirkin | #include "apb_pci.h" |
27 | 87ecb68b | pbrook | #include "pc.h" |
28 | 87ecb68b | pbrook | #include "nvram.h" |
29 | 87ecb68b | pbrook | #include "fdc.h" |
30 | 87ecb68b | pbrook | #include "net.h" |
31 | 87ecb68b | pbrook | #include "qemu-timer.h" |
32 | 87ecb68b | pbrook | #include "sysemu.h" |
33 | 87ecb68b | pbrook | #include "boards.h" |
34 | d2c63fc1 | blueswir1 | #include "firmware_abi.h" |
35 | 3cce6243 | blueswir1 | #include "fw_cfg.h" |
36 | 1baffa46 | Blue Swirl | #include "sysbus.h" |
37 | 977e1244 | Gerd Hoffmann | #include "ide.h" |
38 | ca20cf32 | Blue Swirl | #include "loader.h" |
39 | ca20cf32 | Blue Swirl | #include "elf.h" |
40 | 2446333c | Blue Swirl | #include "blockdev.h" |
41 | 39186d8a | Richard Henderson | #include "exec-memory.h" |
42 | 3475187d | bellard | |
43 | 9d926598 | blueswir1 | //#define DEBUG_IRQ
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44 | b430a225 | Blue Swirl | //#define DEBUG_EBUS
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45 | 8f4efc55 | Igor V. Kovalenko | //#define DEBUG_TIMER
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46 | 9d926598 | blueswir1 | |
47 | 9d926598 | blueswir1 | #ifdef DEBUG_IRQ
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48 | b430a225 | Blue Swirl | #define CPUIRQ_DPRINTF(fmt, ...) \
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49 | 001faf32 | Blue Swirl | do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) |
50 | 9d926598 | blueswir1 | #else
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51 | b430a225 | Blue Swirl | #define CPUIRQ_DPRINTF(fmt, ...)
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52 | b430a225 | Blue Swirl | #endif
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53 | b430a225 | Blue Swirl | |
54 | b430a225 | Blue Swirl | #ifdef DEBUG_EBUS
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55 | b430a225 | Blue Swirl | #define EBUS_DPRINTF(fmt, ...) \
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56 | b430a225 | Blue Swirl | do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0) |
57 | b430a225 | Blue Swirl | #else
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58 | b430a225 | Blue Swirl | #define EBUS_DPRINTF(fmt, ...)
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59 | 9d926598 | blueswir1 | #endif
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60 | 9d926598 | blueswir1 | |
61 | 8f4efc55 | Igor V. Kovalenko | #ifdef DEBUG_TIMER
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62 | 8f4efc55 | Igor V. Kovalenko | #define TIMER_DPRINTF(fmt, ...) \
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63 | 8f4efc55 | Igor V. Kovalenko | do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0) |
64 | 8f4efc55 | Igor V. Kovalenko | #else
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65 | 8f4efc55 | Igor V. Kovalenko | #define TIMER_DPRINTF(fmt, ...)
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66 | 8f4efc55 | Igor V. Kovalenko | #endif
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67 | 8f4efc55 | Igor V. Kovalenko | |
68 | 83469015 | bellard | #define KERNEL_LOAD_ADDR 0x00404000 |
69 | 83469015 | bellard | #define CMDLINE_ADDR 0x003ff000 |
70 | ac2e9d66 | blueswir1 | #define PROM_SIZE_MAX (4 * 1024 * 1024) |
71 | f930d07e | blueswir1 | #define PROM_VADDR 0x000ffd00000ULL |
72 | 83469015 | bellard | #define APB_SPECIAL_BASE 0x1fe00000000ULL |
73 | f930d07e | blueswir1 | #define APB_MEM_BASE 0x1ff00000000ULL |
74 | d63baf92 | Igor V. Kovalenko | #define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL) |
75 | f930d07e | blueswir1 | #define PROM_FILENAME "openbios-sparc64" |
76 | 83469015 | bellard | #define NVRAM_SIZE 0x2000 |
77 | e4bcb14c | ths | #define MAX_IDE_BUS 2 |
78 | 3cce6243 | blueswir1 | #define BIOS_CFG_IOPORT 0x510 |
79 | 7589690c | Blue Swirl | #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) |
80 | 7589690c | Blue Swirl | #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) |
81 | 7589690c | Blue Swirl | #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) |
82 | 3475187d | bellard | |
83 | 361dea40 | Blue Swirl | #define IVEC_MAX 0x30 |
84 | 9d926598 | blueswir1 | |
85 | 8fa211e8 | blueswir1 | #define TICK_MAX 0x7fffffffffffffffULL |
86 | 8fa211e8 | blueswir1 | |
87 | c7ba218d | blueswir1 | struct hwdef {
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88 | c7ba218d | blueswir1 | const char * const default_cpu_model; |
89 | 905fdcb5 | blueswir1 | uint16_t machine_id; |
90 | e87231d4 | blueswir1 | uint64_t prom_addr; |
91 | e87231d4 | blueswir1 | uint64_t console_serial_base; |
92 | c7ba218d | blueswir1 | }; |
93 | c7ba218d | blueswir1 | |
94 | c5e6fb7e | Avi Kivity | typedef struct EbusState { |
95 | c5e6fb7e | Avi Kivity | PCIDevice pci_dev; |
96 | c5e6fb7e | Avi Kivity | MemoryRegion bar0; |
97 | c5e6fb7e | Avi Kivity | MemoryRegion bar1; |
98 | c5e6fb7e | Avi Kivity | } EbusState; |
99 | c5e6fb7e | Avi Kivity | |
100 | 3475187d | bellard | int DMA_get_channel_mode (int nchan) |
101 | 3475187d | bellard | { |
102 | 3475187d | bellard | return 0; |
103 | 3475187d | bellard | } |
104 | 3475187d | bellard | int DMA_read_memory (int nchan, void *buf, int pos, int size) |
105 | 3475187d | bellard | { |
106 | 3475187d | bellard | return 0; |
107 | 3475187d | bellard | } |
108 | 3475187d | bellard | int DMA_write_memory (int nchan, void *buf, int pos, int size) |
109 | 3475187d | bellard | { |
110 | 3475187d | bellard | return 0; |
111 | 3475187d | bellard | } |
112 | 3475187d | bellard | void DMA_hold_DREQ (int nchan) {} |
113 | 3475187d | bellard | void DMA_release_DREQ (int nchan) {} |
114 | 3475187d | bellard | void DMA_schedule(int nchan) {} |
115 | 4556bd8b | Blue Swirl | |
116 | 4556bd8b | Blue Swirl | void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit) |
117 | 4556bd8b | Blue Swirl | { |
118 | 4556bd8b | Blue Swirl | } |
119 | 4556bd8b | Blue Swirl | |
120 | 3475187d | bellard | void DMA_register_channel (int nchan, |
121 | 3475187d | bellard | DMA_transfer_handler transfer_handler, |
122 | 3475187d | bellard | void *opaque)
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123 | 3475187d | bellard | { |
124 | 3475187d | bellard | } |
125 | 3475187d | bellard | |
126 | 513f789f | blueswir1 | static int fw_cfg_boot_set(void *opaque, const char *boot_device) |
127 | 81864572 | blueswir1 | { |
128 | 513f789f | blueswir1 | fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
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129 | 81864572 | blueswir1 | return 0; |
130 | 81864572 | blueswir1 | } |
131 | 81864572 | blueswir1 | |
132 | 43a34704 | Blue Swirl | static int sun4u_NVRAM_set_params(M48t59State *nvram, uint16_t NVRAM_size, |
133 | 43a34704 | Blue Swirl | const char *arch, ram_addr_t RAM_size, |
134 | 43a34704 | Blue Swirl | const char *boot_devices, |
135 | 43a34704 | Blue Swirl | uint32_t kernel_image, uint32_t kernel_size, |
136 | 43a34704 | Blue Swirl | const char *cmdline, |
137 | 43a34704 | Blue Swirl | uint32_t initrd_image, uint32_t initrd_size, |
138 | 43a34704 | Blue Swirl | uint32_t NVRAM_image, |
139 | 43a34704 | Blue Swirl | int width, int height, int depth, |
140 | 43a34704 | Blue Swirl | const uint8_t *macaddr)
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141 | 83469015 | bellard | { |
142 | 66508601 | blueswir1 | unsigned int i; |
143 | 66508601 | blueswir1 | uint32_t start, end; |
144 | d2c63fc1 | blueswir1 | uint8_t image[0x1ff0];
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145 | d2c63fc1 | blueswir1 | struct OpenBIOS_nvpart_v1 *part_header;
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146 | d2c63fc1 | blueswir1 | |
147 | d2c63fc1 | blueswir1 | memset(image, '\0', sizeof(image)); |
148 | d2c63fc1 | blueswir1 | |
149 | 513f789f | blueswir1 | start = 0;
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150 | 83469015 | bellard | |
151 | 66508601 | blueswir1 | // OpenBIOS nvram variables
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152 | 66508601 | blueswir1 | // Variable partition
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153 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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154 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_SYSTEM; |
155 | 363a37d5 | blueswir1 | pstrcpy(part_header->name, sizeof(part_header->name), "system"); |
156 | 66508601 | blueswir1 | |
157 | d2c63fc1 | blueswir1 | end = start + sizeof(struct OpenBIOS_nvpart_v1); |
158 | 66508601 | blueswir1 | for (i = 0; i < nb_prom_envs; i++) |
159 | d2c63fc1 | blueswir1 | end = OpenBIOS_set_var(image, end, prom_envs[i]); |
160 | d2c63fc1 | blueswir1 | |
161 | d2c63fc1 | blueswir1 | // End marker
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162 | d2c63fc1 | blueswir1 | image[end++] = '\0';
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163 | 66508601 | blueswir1 | |
164 | 66508601 | blueswir1 | end = start + ((end - start + 15) & ~15); |
165 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
166 | 66508601 | blueswir1 | |
167 | 66508601 | blueswir1 | // free partition
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168 | 66508601 | blueswir1 | start = end; |
169 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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170 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_FREE; |
171 | 363a37d5 | blueswir1 | pstrcpy(part_header->name, sizeof(part_header->name), "free"); |
172 | 66508601 | blueswir1 | |
173 | 66508601 | blueswir1 | end = 0x1fd0;
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174 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
175 | d2c63fc1 | blueswir1 | |
176 | 0d31cb99 | blueswir1 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); |
177 | 0d31cb99 | blueswir1 | |
178 | d2c63fc1 | blueswir1 | for (i = 0; i < sizeof(image); i++) |
179 | d2c63fc1 | blueswir1 | m48t59_write(nvram, i, image[i]); |
180 | 66508601 | blueswir1 | |
181 | 83469015 | bellard | return 0; |
182 | 3475187d | bellard | } |
183 | 5f2bf0fe | Blue Swirl | |
184 | 5f2bf0fe | Blue Swirl | static uint64_t sun4u_load_kernel(const char *kernel_filename, |
185 | 5f2bf0fe | Blue Swirl | const char *initrd_filename, |
186 | 5f2bf0fe | Blue Swirl | ram_addr_t RAM_size, uint64_t *initrd_size, |
187 | 5f2bf0fe | Blue Swirl | uint64_t *initrd_addr, uint64_t *kernel_addr, |
188 | 5f2bf0fe | Blue Swirl | uint64_t *kernel_entry) |
189 | 636aa70a | Blue Swirl | { |
190 | 636aa70a | Blue Swirl | int linux_boot;
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191 | 636aa70a | Blue Swirl | unsigned int i; |
192 | 636aa70a | Blue Swirl | long kernel_size;
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193 | 6908d9ce | Blue Swirl | uint8_t *ptr; |
194 | 5f2bf0fe | Blue Swirl | uint64_t kernel_top; |
195 | 636aa70a | Blue Swirl | |
196 | 636aa70a | Blue Swirl | linux_boot = (kernel_filename != NULL);
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197 | 636aa70a | Blue Swirl | |
198 | 636aa70a | Blue Swirl | kernel_size = 0;
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199 | 636aa70a | Blue Swirl | if (linux_boot) {
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200 | ca20cf32 | Blue Swirl | int bswap_needed;
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201 | ca20cf32 | Blue Swirl | |
202 | ca20cf32 | Blue Swirl | #ifdef BSWAP_NEEDED
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203 | ca20cf32 | Blue Swirl | bswap_needed = 1;
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204 | ca20cf32 | Blue Swirl | #else
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205 | ca20cf32 | Blue Swirl | bswap_needed = 0;
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206 | ca20cf32 | Blue Swirl | #endif
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207 | 5f2bf0fe | Blue Swirl | kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry, |
208 | 5f2bf0fe | Blue Swirl | kernel_addr, &kernel_top, 1, ELF_MACHINE, 0); |
209 | 5f2bf0fe | Blue Swirl | if (kernel_size < 0) { |
210 | 5f2bf0fe | Blue Swirl | *kernel_addr = KERNEL_LOAD_ADDR; |
211 | 5f2bf0fe | Blue Swirl | *kernel_entry = KERNEL_LOAD_ADDR; |
212 | 636aa70a | Blue Swirl | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
213 | ca20cf32 | Blue Swirl | RAM_size - KERNEL_LOAD_ADDR, bswap_needed, |
214 | ca20cf32 | Blue Swirl | TARGET_PAGE_SIZE); |
215 | 5f2bf0fe | Blue Swirl | } |
216 | 5f2bf0fe | Blue Swirl | if (kernel_size < 0) { |
217 | 636aa70a | Blue Swirl | kernel_size = load_image_targphys(kernel_filename, |
218 | 636aa70a | Blue Swirl | KERNEL_LOAD_ADDR, |
219 | 636aa70a | Blue Swirl | RAM_size - KERNEL_LOAD_ADDR); |
220 | 5f2bf0fe | Blue Swirl | } |
221 | 636aa70a | Blue Swirl | if (kernel_size < 0) { |
222 | 636aa70a | Blue Swirl | fprintf(stderr, "qemu: could not load kernel '%s'\n",
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223 | 636aa70a | Blue Swirl | kernel_filename); |
224 | 636aa70a | Blue Swirl | exit(1);
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225 | 636aa70a | Blue Swirl | } |
226 | 5f2bf0fe | Blue Swirl | /* load initrd above kernel */
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227 | 636aa70a | Blue Swirl | *initrd_size = 0;
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228 | 636aa70a | Blue Swirl | if (initrd_filename) {
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229 | 5f2bf0fe | Blue Swirl | *initrd_addr = TARGET_PAGE_ALIGN(kernel_top); |
230 | 5f2bf0fe | Blue Swirl | |
231 | 636aa70a | Blue Swirl | *initrd_size = load_image_targphys(initrd_filename, |
232 | 5f2bf0fe | Blue Swirl | *initrd_addr, |
233 | 5f2bf0fe | Blue Swirl | RAM_size - *initrd_addr); |
234 | 5f2bf0fe | Blue Swirl | if ((int)*initrd_size < 0) { |
235 | 636aa70a | Blue Swirl | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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236 | 636aa70a | Blue Swirl | initrd_filename); |
237 | 636aa70a | Blue Swirl | exit(1);
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238 | 636aa70a | Blue Swirl | } |
239 | 636aa70a | Blue Swirl | } |
240 | 636aa70a | Blue Swirl | if (*initrd_size > 0) { |
241 | 636aa70a | Blue Swirl | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
242 | 5f2bf0fe | Blue Swirl | ptr = rom_ptr(*kernel_addr + i); |
243 | 6908d9ce | Blue Swirl | if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */ |
244 | 5f2bf0fe | Blue Swirl | stl_p(ptr + 24, *initrd_addr + *kernel_addr);
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245 | 6908d9ce | Blue Swirl | stl_p(ptr + 28, *initrd_size);
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246 | 636aa70a | Blue Swirl | break;
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247 | 636aa70a | Blue Swirl | } |
248 | 636aa70a | Blue Swirl | } |
249 | 636aa70a | Blue Swirl | } |
250 | 636aa70a | Blue Swirl | } |
251 | 636aa70a | Blue Swirl | return kernel_size;
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252 | 636aa70a | Blue Swirl | } |
253 | 3475187d | bellard | |
254 | 98cec4a2 | Andreas Färber | void cpu_check_irqs(CPUSPARCState *env)
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255 | 9d926598 | blueswir1 | { |
256 | d532b26c | Igor V. Kovalenko | uint32_t pil = env->pil_in | |
257 | d532b26c | Igor V. Kovalenko | (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER)); |
258 | d532b26c | Igor V. Kovalenko | |
259 | a7be9bad | Artyom Tarasenko | /* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */
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260 | a7be9bad | Artyom Tarasenko | if (env->ivec_status & 0x20) { |
261 | a7be9bad | Artyom Tarasenko | return;
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262 | a7be9bad | Artyom Tarasenko | } |
263 | d532b26c | Igor V. Kovalenko | /* check if TM or SM in SOFTINT are set
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264 | d532b26c | Igor V. Kovalenko | setting these also causes interrupt 14 */
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265 | d532b26c | Igor V. Kovalenko | if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
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266 | d532b26c | Igor V. Kovalenko | pil |= 1 << 14; |
267 | d532b26c | Igor V. Kovalenko | } |
268 | d532b26c | Igor V. Kovalenko | |
269 | 9f94778c | Artyom Tarasenko | /* The bit corresponding to psrpil is (1<< psrpil), the next bit
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270 | 9f94778c | Artyom Tarasenko | is (2 << psrpil). */
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271 | 9f94778c | Artyom Tarasenko | if (pil < (2 << env->psrpil)){ |
272 | d532b26c | Igor V. Kovalenko | if (env->interrupt_request & CPU_INTERRUPT_HARD) {
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273 | d532b26c | Igor V. Kovalenko | CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
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274 | d532b26c | Igor V. Kovalenko | env->interrupt_index); |
275 | d532b26c | Igor V. Kovalenko | env->interrupt_index = 0;
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276 | d532b26c | Igor V. Kovalenko | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
277 | d532b26c | Igor V. Kovalenko | } |
278 | d532b26c | Igor V. Kovalenko | return;
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279 | d532b26c | Igor V. Kovalenko | } |
280 | d532b26c | Igor V. Kovalenko | |
281 | d532b26c | Igor V. Kovalenko | if (cpu_interrupts_enabled(env)) {
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282 | 9d926598 | blueswir1 | |
283 | 9d926598 | blueswir1 | unsigned int i; |
284 | 9d926598 | blueswir1 | |
285 | d532b26c | Igor V. Kovalenko | for (i = 15; i > env->psrpil; i--) { |
286 | 9d926598 | blueswir1 | if (pil & (1 << i)) { |
287 | 9d926598 | blueswir1 | int old_interrupt = env->interrupt_index;
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288 | d532b26c | Igor V. Kovalenko | int new_interrupt = TT_EXTINT | i;
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289 | d532b26c | Igor V. Kovalenko | |
290 | a7be9bad | Artyom Tarasenko | if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt |
291 | a7be9bad | Artyom Tarasenko | && ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) {
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292 | d532b26c | Igor V. Kovalenko | CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
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293 | d532b26c | Igor V. Kovalenko | "current %x >= pending %x\n",
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294 | d532b26c | Igor V. Kovalenko | env->tl, cpu_tsptr(env)->tt, new_interrupt); |
295 | d532b26c | Igor V. Kovalenko | } else if (old_interrupt != new_interrupt) { |
296 | d532b26c | Igor V. Kovalenko | env->interrupt_index = new_interrupt; |
297 | d532b26c | Igor V. Kovalenko | CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i,
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298 | d532b26c | Igor V. Kovalenko | old_interrupt, new_interrupt); |
299 | 9d926598 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
300 | 9d926598 | blueswir1 | } |
301 | 9d926598 | blueswir1 | break;
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302 | 9d926598 | blueswir1 | } |
303 | 9d926598 | blueswir1 | } |
304 | 9f94778c | Artyom Tarasenko | } else if (env->interrupt_request & CPU_INTERRUPT_HARD) { |
305 | d532b26c | Igor V. Kovalenko | CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
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306 | d532b26c | Igor V. Kovalenko | "current interrupt %x\n",
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307 | d532b26c | Igor V. Kovalenko | pil, env->pil_in, env->softint, env->interrupt_index); |
308 | 9f94778c | Artyom Tarasenko | env->interrupt_index = 0;
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309 | 9f94778c | Artyom Tarasenko | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
310 | 9d926598 | blueswir1 | } |
311 | 9d926598 | blueswir1 | } |
312 | 9d926598 | blueswir1 | |
313 | 98cec4a2 | Andreas Färber | static void cpu_kick_irq(CPUSPARCState *env) |
314 | 8f4efc55 | Igor V. Kovalenko | { |
315 | 8f4efc55 | Igor V. Kovalenko | env->halted = 0;
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316 | 8f4efc55 | Igor V. Kovalenko | cpu_check_irqs(env); |
317 | 94ad5b00 | Paolo Bonzini | qemu_cpu_kick(env); |
318 | 8f4efc55 | Igor V. Kovalenko | } |
319 | 8f4efc55 | Igor V. Kovalenko | |
320 | 361dea40 | Blue Swirl | static void cpu_set_ivec_irq(void *opaque, int irq, int level) |
321 | 9d926598 | blueswir1 | { |
322 | 98cec4a2 | Andreas Färber | CPUSPARCState *env = opaque; |
323 | 9d926598 | blueswir1 | |
324 | 9d926598 | blueswir1 | if (level) {
|
325 | 23cf96e1 | Artyom Tarasenko | if (!(env->ivec_status & 0x20)) { |
326 | 23cf96e1 | Artyom Tarasenko | CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq);
|
327 | 23cf96e1 | Artyom Tarasenko | env->halted = 0;
|
328 | 23cf96e1 | Artyom Tarasenko | env->interrupt_index = TT_IVEC; |
329 | 23cf96e1 | Artyom Tarasenko | env->ivec_status |= 0x20;
|
330 | 23cf96e1 | Artyom Tarasenko | env->ivec_data[0] = (0x1f << 6) | irq; |
331 | 23cf96e1 | Artyom Tarasenko | env->ivec_data[1] = 0; |
332 | 23cf96e1 | Artyom Tarasenko | env->ivec_data[2] = 0; |
333 | 23cf96e1 | Artyom Tarasenko | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
334 | 23cf96e1 | Artyom Tarasenko | } |
335 | 23cf96e1 | Artyom Tarasenko | } else {
|
336 | 23cf96e1 | Artyom Tarasenko | if (env->ivec_status & 0x20) { |
337 | 23cf96e1 | Artyom Tarasenko | CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq);
|
338 | 23cf96e1 | Artyom Tarasenko | env->ivec_status &= ~0x20;
|
339 | 23cf96e1 | Artyom Tarasenko | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
340 | 23cf96e1 | Artyom Tarasenko | } |
341 | 9d926598 | blueswir1 | } |
342 | 9d926598 | blueswir1 | } |
343 | 9d926598 | blueswir1 | |
344 | e87231d4 | blueswir1 | typedef struct ResetData { |
345 | 403d7a2d | Andreas Färber | SPARCCPU *cpu; |
346 | 44a99354 | Blue Swirl | uint64_t prom_addr; |
347 | e87231d4 | blueswir1 | } ResetData; |
348 | e87231d4 | blueswir1 | |
349 | 8f4efc55 | Igor V. Kovalenko | void cpu_put_timer(QEMUFile *f, CPUTimer *s)
|
350 | 8f4efc55 | Igor V. Kovalenko | { |
351 | 8f4efc55 | Igor V. Kovalenko | qemu_put_be32s(f, &s->frequency); |
352 | 8f4efc55 | Igor V. Kovalenko | qemu_put_be32s(f, &s->disabled); |
353 | 8f4efc55 | Igor V. Kovalenko | qemu_put_be64s(f, &s->disabled_mask); |
354 | 8f4efc55 | Igor V. Kovalenko | qemu_put_sbe64s(f, &s->clock_offset); |
355 | 8f4efc55 | Igor V. Kovalenko | |
356 | 8f4efc55 | Igor V. Kovalenko | qemu_put_timer(f, s->qtimer); |
357 | 8f4efc55 | Igor V. Kovalenko | } |
358 | 8f4efc55 | Igor V. Kovalenko | |
359 | 8f4efc55 | Igor V. Kovalenko | void cpu_get_timer(QEMUFile *f, CPUTimer *s)
|
360 | 8f4efc55 | Igor V. Kovalenko | { |
361 | 8f4efc55 | Igor V. Kovalenko | qemu_get_be32s(f, &s->frequency); |
362 | 8f4efc55 | Igor V. Kovalenko | qemu_get_be32s(f, &s->disabled); |
363 | 8f4efc55 | Igor V. Kovalenko | qemu_get_be64s(f, &s->disabled_mask); |
364 | 8f4efc55 | Igor V. Kovalenko | qemu_get_sbe64s(f, &s->clock_offset); |
365 | 8f4efc55 | Igor V. Kovalenko | |
366 | 8f4efc55 | Igor V. Kovalenko | qemu_get_timer(f, s->qtimer); |
367 | 8f4efc55 | Igor V. Kovalenko | } |
368 | 8f4efc55 | Igor V. Kovalenko | |
369 | 98cec4a2 | Andreas Färber | static CPUTimer* cpu_timer_create(const char* name, CPUSPARCState *env, |
370 | 8f4efc55 | Igor V. Kovalenko | QEMUBHFunc *cb, uint32_t frequency, |
371 | 8f4efc55 | Igor V. Kovalenko | uint64_t disabled_mask) |
372 | 8f4efc55 | Igor V. Kovalenko | { |
373 | 7267c094 | Anthony Liguori | CPUTimer *timer = g_malloc0(sizeof (CPUTimer));
|
374 | 8f4efc55 | Igor V. Kovalenko | |
375 | 8f4efc55 | Igor V. Kovalenko | timer->name = name; |
376 | 8f4efc55 | Igor V. Kovalenko | timer->frequency = frequency; |
377 | 8f4efc55 | Igor V. Kovalenko | timer->disabled_mask = disabled_mask; |
378 | 8f4efc55 | Igor V. Kovalenko | |
379 | 8f4efc55 | Igor V. Kovalenko | timer->disabled = 1;
|
380 | 74475455 | Paolo Bonzini | timer->clock_offset = qemu_get_clock_ns(vm_clock); |
381 | 8f4efc55 | Igor V. Kovalenko | |
382 | 74475455 | Paolo Bonzini | timer->qtimer = qemu_new_timer_ns(vm_clock, cb, env); |
383 | 8f4efc55 | Igor V. Kovalenko | |
384 | 8f4efc55 | Igor V. Kovalenko | return timer;
|
385 | 8f4efc55 | Igor V. Kovalenko | } |
386 | 8f4efc55 | Igor V. Kovalenko | |
387 | 8f4efc55 | Igor V. Kovalenko | static void cpu_timer_reset(CPUTimer *timer) |
388 | 8f4efc55 | Igor V. Kovalenko | { |
389 | 8f4efc55 | Igor V. Kovalenko | timer->disabled = 1;
|
390 | 74475455 | Paolo Bonzini | timer->clock_offset = qemu_get_clock_ns(vm_clock); |
391 | 8f4efc55 | Igor V. Kovalenko | |
392 | 8f4efc55 | Igor V. Kovalenko | qemu_del_timer(timer->qtimer); |
393 | 8f4efc55 | Igor V. Kovalenko | } |
394 | 8f4efc55 | Igor V. Kovalenko | |
395 | c68ea704 | bellard | static void main_cpu_reset(void *opaque) |
396 | c68ea704 | bellard | { |
397 | e87231d4 | blueswir1 | ResetData *s = (ResetData *)opaque; |
398 | 403d7a2d | Andreas Färber | CPUSPARCState *env = &s->cpu->env; |
399 | 44a99354 | Blue Swirl | static unsigned int nr_resets; |
400 | 20c9f095 | blueswir1 | |
401 | 403d7a2d | Andreas Färber | cpu_reset(CPU(s->cpu)); |
402 | 8f4efc55 | Igor V. Kovalenko | |
403 | 8f4efc55 | Igor V. Kovalenko | cpu_timer_reset(env->tick); |
404 | 8f4efc55 | Igor V. Kovalenko | cpu_timer_reset(env->stick); |
405 | 8f4efc55 | Igor V. Kovalenko | cpu_timer_reset(env->hstick); |
406 | 8f4efc55 | Igor V. Kovalenko | |
407 | e87231d4 | blueswir1 | env->gregs[1] = 0; // Memory start |
408 | e87231d4 | blueswir1 | env->gregs[2] = ram_size; // Memory size |
409 | e87231d4 | blueswir1 | env->gregs[3] = 0; // Machine description XXX |
410 | 44a99354 | Blue Swirl | if (nr_resets++ == 0) { |
411 | 44a99354 | Blue Swirl | /* Power on reset */
|
412 | 44a99354 | Blue Swirl | env->pc = s->prom_addr + 0x20ULL;
|
413 | 44a99354 | Blue Swirl | } else {
|
414 | 44a99354 | Blue Swirl | env->pc = s->prom_addr + 0x40ULL;
|
415 | 44a99354 | Blue Swirl | } |
416 | e87231d4 | blueswir1 | env->npc = env->pc + 4;
|
417 | 20c9f095 | blueswir1 | } |
418 | 20c9f095 | blueswir1 | |
419 | 22548760 | blueswir1 | static void tick_irq(void *opaque) |
420 | 20c9f095 | blueswir1 | { |
421 | 98cec4a2 | Andreas Färber | CPUSPARCState *env = opaque; |
422 | 20c9f095 | blueswir1 | |
423 | 8f4efc55 | Igor V. Kovalenko | CPUTimer* timer = env->tick; |
424 | 8f4efc55 | Igor V. Kovalenko | |
425 | 8f4efc55 | Igor V. Kovalenko | if (timer->disabled) {
|
426 | 8f4efc55 | Igor V. Kovalenko | CPUIRQ_DPRINTF("tick_irq: softint disabled\n");
|
427 | 8f4efc55 | Igor V. Kovalenko | return;
|
428 | 8f4efc55 | Igor V. Kovalenko | } else {
|
429 | 8f4efc55 | Igor V. Kovalenko | CPUIRQ_DPRINTF("tick: fire\n");
|
430 | 8fa211e8 | blueswir1 | } |
431 | 8f4efc55 | Igor V. Kovalenko | |
432 | 8f4efc55 | Igor V. Kovalenko | env->softint |= SOFTINT_TIMER; |
433 | 8f4efc55 | Igor V. Kovalenko | cpu_kick_irq(env); |
434 | 20c9f095 | blueswir1 | } |
435 | 20c9f095 | blueswir1 | |
436 | 22548760 | blueswir1 | static void stick_irq(void *opaque) |
437 | 20c9f095 | blueswir1 | { |
438 | 98cec4a2 | Andreas Färber | CPUSPARCState *env = opaque; |
439 | 20c9f095 | blueswir1 | |
440 | 8f4efc55 | Igor V. Kovalenko | CPUTimer* timer = env->stick; |
441 | 8f4efc55 | Igor V. Kovalenko | |
442 | 8f4efc55 | Igor V. Kovalenko | if (timer->disabled) {
|
443 | 8f4efc55 | Igor V. Kovalenko | CPUIRQ_DPRINTF("stick_irq: softint disabled\n");
|
444 | 8f4efc55 | Igor V. Kovalenko | return;
|
445 | 8f4efc55 | Igor V. Kovalenko | } else {
|
446 | 8f4efc55 | Igor V. Kovalenko | CPUIRQ_DPRINTF("stick: fire\n");
|
447 | 8fa211e8 | blueswir1 | } |
448 | 8f4efc55 | Igor V. Kovalenko | |
449 | 8f4efc55 | Igor V. Kovalenko | env->softint |= SOFTINT_STIMER; |
450 | 8f4efc55 | Igor V. Kovalenko | cpu_kick_irq(env); |
451 | 20c9f095 | blueswir1 | } |
452 | 20c9f095 | blueswir1 | |
453 | 22548760 | blueswir1 | static void hstick_irq(void *opaque) |
454 | 20c9f095 | blueswir1 | { |
455 | 98cec4a2 | Andreas Färber | CPUSPARCState *env = opaque; |
456 | 20c9f095 | blueswir1 | |
457 | 8f4efc55 | Igor V. Kovalenko | CPUTimer* timer = env->hstick; |
458 | 8f4efc55 | Igor V. Kovalenko | |
459 | 8f4efc55 | Igor V. Kovalenko | if (timer->disabled) {
|
460 | 8f4efc55 | Igor V. Kovalenko | CPUIRQ_DPRINTF("hstick_irq: softint disabled\n");
|
461 | 8f4efc55 | Igor V. Kovalenko | return;
|
462 | 8f4efc55 | Igor V. Kovalenko | } else {
|
463 | 8f4efc55 | Igor V. Kovalenko | CPUIRQ_DPRINTF("hstick: fire\n");
|
464 | 8fa211e8 | blueswir1 | } |
465 | 8f4efc55 | Igor V. Kovalenko | |
466 | 8f4efc55 | Igor V. Kovalenko | env->softint |= SOFTINT_STIMER; |
467 | 8f4efc55 | Igor V. Kovalenko | cpu_kick_irq(env); |
468 | 8f4efc55 | Igor V. Kovalenko | } |
469 | 8f4efc55 | Igor V. Kovalenko | |
470 | 8f4efc55 | Igor V. Kovalenko | static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency)
|
471 | 8f4efc55 | Igor V. Kovalenko | { |
472 | 8f4efc55 | Igor V. Kovalenko | return muldiv64(cpu_ticks, get_ticks_per_sec(), frequency);
|
473 | 8f4efc55 | Igor V. Kovalenko | } |
474 | 8f4efc55 | Igor V. Kovalenko | |
475 | 8f4efc55 | Igor V. Kovalenko | static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency)
|
476 | 8f4efc55 | Igor V. Kovalenko | { |
477 | 8f4efc55 | Igor V. Kovalenko | return muldiv64(timer_ticks, frequency, get_ticks_per_sec());
|
478 | c68ea704 | bellard | } |
479 | c68ea704 | bellard | |
480 | 8f4efc55 | Igor V. Kovalenko | void cpu_tick_set_count(CPUTimer *timer, uint64_t count)
|
481 | f4b1a842 | blueswir1 | { |
482 | 8f4efc55 | Igor V. Kovalenko | uint64_t real_count = count & ~timer->disabled_mask; |
483 | 8f4efc55 | Igor V. Kovalenko | uint64_t disabled_bit = count & timer->disabled_mask; |
484 | 8f4efc55 | Igor V. Kovalenko | |
485 | 74475455 | Paolo Bonzini | int64_t vm_clock_offset = qemu_get_clock_ns(vm_clock) - |
486 | 8f4efc55 | Igor V. Kovalenko | cpu_to_timer_ticks(real_count, timer->frequency); |
487 | 8f4efc55 | Igor V. Kovalenko | |
488 | 8f4efc55 | Igor V. Kovalenko | TIMER_DPRINTF("%s set_count count=0x%016lx (%s) p=%p\n",
|
489 | 8f4efc55 | Igor V. Kovalenko | timer->name, real_count, |
490 | 8f4efc55 | Igor V. Kovalenko | timer->disabled?"disabled":"enabled", timer); |
491 | 8f4efc55 | Igor V. Kovalenko | |
492 | 8f4efc55 | Igor V. Kovalenko | timer->disabled = disabled_bit ? 1 : 0; |
493 | 8f4efc55 | Igor V. Kovalenko | timer->clock_offset = vm_clock_offset; |
494 | f4b1a842 | blueswir1 | } |
495 | f4b1a842 | blueswir1 | |
496 | 8f4efc55 | Igor V. Kovalenko | uint64_t cpu_tick_get_count(CPUTimer *timer) |
497 | f4b1a842 | blueswir1 | { |
498 | 8f4efc55 | Igor V. Kovalenko | uint64_t real_count = timer_to_cpu_ticks( |
499 | 74475455 | Paolo Bonzini | qemu_get_clock_ns(vm_clock) - timer->clock_offset, |
500 | 8f4efc55 | Igor V. Kovalenko | timer->frequency); |
501 | 8f4efc55 | Igor V. Kovalenko | |
502 | 8f4efc55 | Igor V. Kovalenko | TIMER_DPRINTF("%s get_count count=0x%016lx (%s) p=%p\n",
|
503 | 8f4efc55 | Igor V. Kovalenko | timer->name, real_count, |
504 | 8f4efc55 | Igor V. Kovalenko | timer->disabled?"disabled":"enabled", timer); |
505 | 8f4efc55 | Igor V. Kovalenko | |
506 | 8f4efc55 | Igor V. Kovalenko | if (timer->disabled)
|
507 | 8f4efc55 | Igor V. Kovalenko | real_count |= timer->disabled_mask; |
508 | 8f4efc55 | Igor V. Kovalenko | |
509 | 8f4efc55 | Igor V. Kovalenko | return real_count;
|
510 | f4b1a842 | blueswir1 | } |
511 | f4b1a842 | blueswir1 | |
512 | 8f4efc55 | Igor V. Kovalenko | void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit)
|
513 | f4b1a842 | blueswir1 | { |
514 | 74475455 | Paolo Bonzini | int64_t now = qemu_get_clock_ns(vm_clock); |
515 | 8f4efc55 | Igor V. Kovalenko | |
516 | 8f4efc55 | Igor V. Kovalenko | uint64_t real_limit = limit & ~timer->disabled_mask; |
517 | 8f4efc55 | Igor V. Kovalenko | timer->disabled = (limit & timer->disabled_mask) ? 1 : 0; |
518 | 8f4efc55 | Igor V. Kovalenko | |
519 | 8f4efc55 | Igor V. Kovalenko | int64_t expires = cpu_to_timer_ticks(real_limit, timer->frequency) + |
520 | 8f4efc55 | Igor V. Kovalenko | timer->clock_offset; |
521 | 8f4efc55 | Igor V. Kovalenko | |
522 | 8f4efc55 | Igor V. Kovalenko | if (expires < now) {
|
523 | 8f4efc55 | Igor V. Kovalenko | expires = now + 1;
|
524 | 8f4efc55 | Igor V. Kovalenko | } |
525 | 8f4efc55 | Igor V. Kovalenko | |
526 | 8f4efc55 | Igor V. Kovalenko | TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p "
|
527 | 8f4efc55 | Igor V. Kovalenko | "called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n",
|
528 | 8f4efc55 | Igor V. Kovalenko | timer->name, real_limit, |
529 | 8f4efc55 | Igor V. Kovalenko | timer->disabled?"disabled":"enabled", |
530 | 8f4efc55 | Igor V. Kovalenko | timer, limit, |
531 | 8f4efc55 | Igor V. Kovalenko | timer_to_cpu_ticks(now - timer->clock_offset, |
532 | 8f4efc55 | Igor V. Kovalenko | timer->frequency), |
533 | 8f4efc55 | Igor V. Kovalenko | timer_to_cpu_ticks(expires - now, timer->frequency)); |
534 | 8f4efc55 | Igor V. Kovalenko | |
535 | 8f4efc55 | Igor V. Kovalenko | if (!real_limit) {
|
536 | 8f4efc55 | Igor V. Kovalenko | TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n",
|
537 | 8f4efc55 | Igor V. Kovalenko | timer->name); |
538 | 8f4efc55 | Igor V. Kovalenko | qemu_del_timer(timer->qtimer); |
539 | 8f4efc55 | Igor V. Kovalenko | } else if (timer->disabled) { |
540 | 8f4efc55 | Igor V. Kovalenko | qemu_del_timer(timer->qtimer); |
541 | 8f4efc55 | Igor V. Kovalenko | } else {
|
542 | 8f4efc55 | Igor V. Kovalenko | qemu_mod_timer(timer->qtimer, expires); |
543 | 8f4efc55 | Igor V. Kovalenko | } |
544 | f4b1a842 | blueswir1 | } |
545 | f4b1a842 | blueswir1 | |
546 | 361dea40 | Blue Swirl | static void isa_irq_handler(void *opaque, int n, int level) |
547 | 1387fe4a | Blue Swirl | { |
548 | 361dea40 | Blue Swirl | static const int isa_irq_to_ivec[16] = { |
549 | 361dea40 | Blue Swirl | [1] = 0x29, /* keyboard */ |
550 | 361dea40 | Blue Swirl | [4] = 0x2b, /* serial */ |
551 | 361dea40 | Blue Swirl | [6] = 0x27, /* floppy */ |
552 | 361dea40 | Blue Swirl | [7] = 0x22, /* parallel */ |
553 | 361dea40 | Blue Swirl | [12] = 0x2a, /* mouse */ |
554 | 361dea40 | Blue Swirl | }; |
555 | 361dea40 | Blue Swirl | qemu_irq *irqs = opaque; |
556 | 361dea40 | Blue Swirl | int ivec;
|
557 | 361dea40 | Blue Swirl | |
558 | 361dea40 | Blue Swirl | assert(n < 16);
|
559 | 361dea40 | Blue Swirl | ivec = isa_irq_to_ivec[n]; |
560 | 361dea40 | Blue Swirl | EBUS_DPRINTF("Set ISA IRQ %d level %d -> ivec 0x%x\n", n, level, ivec);
|
561 | 361dea40 | Blue Swirl | if (ivec) {
|
562 | 361dea40 | Blue Swirl | qemu_set_irq(irqs[ivec], level); |
563 | 361dea40 | Blue Swirl | } |
564 | 1387fe4a | Blue Swirl | } |
565 | 1387fe4a | Blue Swirl | |
566 | c190ea07 | blueswir1 | /* EBUS (Eight bit bus) bridge */
|
567 | 48a18b3c | Hervé Poussineau | static ISABus *
|
568 | 361dea40 | Blue Swirl | pci_ebus_init(PCIBus *bus, int devfn, qemu_irq *irqs)
|
569 | c190ea07 | blueswir1 | { |
570 | 1387fe4a | Blue Swirl | qemu_irq *isa_irq; |
571 | ab953e28 | Hervé Poussineau | PCIDevice *pci_dev; |
572 | 48a18b3c | Hervé Poussineau | ISABus *isa_bus; |
573 | 1387fe4a | Blue Swirl | |
574 | ab953e28 | Hervé Poussineau | pci_dev = pci_create_simple(bus, devfn, "ebus");
|
575 | ab953e28 | Hervé Poussineau | isa_bus = DO_UPCAST(ISABus, qbus, |
576 | ab953e28 | Hervé Poussineau | qdev_get_child_bus(&pci_dev->qdev, "isa.0"));
|
577 | 361dea40 | Blue Swirl | isa_irq = qemu_allocate_irqs(isa_irq_handler, irqs, 16);
|
578 | 48a18b3c | Hervé Poussineau | isa_bus_irqs(isa_bus, isa_irq); |
579 | 48a18b3c | Hervé Poussineau | return isa_bus;
|
580 | 53e3c4f9 | Blue Swirl | } |
581 | c190ea07 | blueswir1 | |
582 | 81a322d4 | Gerd Hoffmann | static int |
583 | c5e6fb7e | Avi Kivity | pci_ebus_init1(PCIDevice *pci_dev) |
584 | 53e3c4f9 | Blue Swirl | { |
585 | c5e6fb7e | Avi Kivity | EbusState *s = DO_UPCAST(EbusState, pci_dev, pci_dev); |
586 | c5e6fb7e | Avi Kivity | |
587 | c2d0d012 | Richard Henderson | isa_bus_new(&pci_dev->qdev, pci_address_space_io(pci_dev)); |
588 | c5e6fb7e | Avi Kivity | |
589 | c5e6fb7e | Avi Kivity | pci_dev->config[0x04] = 0x06; // command = bus master, pci mem |
590 | c5e6fb7e | Avi Kivity | pci_dev->config[0x05] = 0x00; |
591 | c5e6fb7e | Avi Kivity | pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error |
592 | c5e6fb7e | Avi Kivity | pci_dev->config[0x07] = 0x03; // status = medium devsel |
593 | c5e6fb7e | Avi Kivity | pci_dev->config[0x09] = 0x00; // programming i/f |
594 | c5e6fb7e | Avi Kivity | pci_dev->config[0x0D] = 0x0a; // latency_timer |
595 | c5e6fb7e | Avi Kivity | |
596 | c5e6fb7e | Avi Kivity | isa_mmio_setup(&s->bar0, 0x1000000);
|
597 | e824b2cc | Avi Kivity | pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
|
598 | c5e6fb7e | Avi Kivity | isa_mmio_setup(&s->bar1, 0x800000);
|
599 | e824b2cc | Avi Kivity | pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar1);
|
600 | 81a322d4 | Gerd Hoffmann | return 0; |
601 | c190ea07 | blueswir1 | } |
602 | c190ea07 | blueswir1 | |
603 | 40021f08 | Anthony Liguori | static void ebus_class_init(ObjectClass *klass, void *data) |
604 | 40021f08 | Anthony Liguori | { |
605 | 40021f08 | Anthony Liguori | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
606 | 40021f08 | Anthony Liguori | |
607 | 40021f08 | Anthony Liguori | k->init = pci_ebus_init1; |
608 | 40021f08 | Anthony Liguori | k->vendor_id = PCI_VENDOR_ID_SUN; |
609 | 40021f08 | Anthony Liguori | k->device_id = PCI_DEVICE_ID_SUN_EBUS; |
610 | 40021f08 | Anthony Liguori | k->revision = 0x01;
|
611 | 40021f08 | Anthony Liguori | k->class_id = PCI_CLASS_BRIDGE_OTHER; |
612 | 40021f08 | Anthony Liguori | } |
613 | 40021f08 | Anthony Liguori | |
614 | 39bffca2 | Anthony Liguori | static TypeInfo ebus_info = {
|
615 | 39bffca2 | Anthony Liguori | .name = "ebus",
|
616 | 39bffca2 | Anthony Liguori | .parent = TYPE_PCI_DEVICE, |
617 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(EbusState),
|
618 | 39bffca2 | Anthony Liguori | .class_init = ebus_class_init, |
619 | 53e3c4f9 | Blue Swirl | }; |
620 | 53e3c4f9 | Blue Swirl | |
621 | d4edce38 | Avi Kivity | typedef struct PROMState { |
622 | d4edce38 | Avi Kivity | SysBusDevice busdev; |
623 | d4edce38 | Avi Kivity | MemoryRegion prom; |
624 | d4edce38 | Avi Kivity | } PROMState; |
625 | d4edce38 | Avi Kivity | |
626 | 409dbce5 | Aurelien Jarno | static uint64_t translate_prom_address(void *opaque, uint64_t addr) |
627 | 409dbce5 | Aurelien Jarno | { |
628 | 409dbce5 | Aurelien Jarno | target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque; |
629 | 409dbce5 | Aurelien Jarno | return addr + *base_addr - PROM_VADDR;
|
630 | 409dbce5 | Aurelien Jarno | } |
631 | 409dbce5 | Aurelien Jarno | |
632 | 1baffa46 | Blue Swirl | /* Boot PROM (OpenBIOS) */
|
633 | c227f099 | Anthony Liguori | static void prom_init(target_phys_addr_t addr, const char *bios_name) |
634 | 1baffa46 | Blue Swirl | { |
635 | 1baffa46 | Blue Swirl | DeviceState *dev; |
636 | 1baffa46 | Blue Swirl | SysBusDevice *s; |
637 | 1baffa46 | Blue Swirl | char *filename;
|
638 | 1baffa46 | Blue Swirl | int ret;
|
639 | 1baffa46 | Blue Swirl | |
640 | 1baffa46 | Blue Swirl | dev = qdev_create(NULL, "openprom"); |
641 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
642 | 1baffa46 | Blue Swirl | s = sysbus_from_qdev(dev); |
643 | 1baffa46 | Blue Swirl | |
644 | 1baffa46 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
645 | 1baffa46 | Blue Swirl | |
646 | 1baffa46 | Blue Swirl | /* load boot prom */
|
647 | 1baffa46 | Blue Swirl | if (bios_name == NULL) { |
648 | 1baffa46 | Blue Swirl | bios_name = PROM_FILENAME; |
649 | 1baffa46 | Blue Swirl | } |
650 | 1baffa46 | Blue Swirl | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
651 | 1baffa46 | Blue Swirl | if (filename) {
|
652 | 409dbce5 | Aurelien Jarno | ret = load_elf(filename, translate_prom_address, &addr, |
653 | 409dbce5 | Aurelien Jarno | NULL, NULL, NULL, 1, ELF_MACHINE, 0); |
654 | 1baffa46 | Blue Swirl | if (ret < 0 || ret > PROM_SIZE_MAX) { |
655 | 1baffa46 | Blue Swirl | ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); |
656 | 1baffa46 | Blue Swirl | } |
657 | 7267c094 | Anthony Liguori | g_free(filename); |
658 | 1baffa46 | Blue Swirl | } else {
|
659 | 1baffa46 | Blue Swirl | ret = -1;
|
660 | 1baffa46 | Blue Swirl | } |
661 | 1baffa46 | Blue Swirl | if (ret < 0 || ret > PROM_SIZE_MAX) { |
662 | 1baffa46 | Blue Swirl | fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
|
663 | 1baffa46 | Blue Swirl | exit(1);
|
664 | 1baffa46 | Blue Swirl | } |
665 | 1baffa46 | Blue Swirl | } |
666 | 1baffa46 | Blue Swirl | |
667 | 81a322d4 | Gerd Hoffmann | static int prom_init1(SysBusDevice *dev) |
668 | 1baffa46 | Blue Swirl | { |
669 | d4edce38 | Avi Kivity | PROMState *s = FROM_SYSBUS(PROMState, dev); |
670 | 1baffa46 | Blue Swirl | |
671 | c5705a77 | Avi Kivity | memory_region_init_ram(&s->prom, "sun4u.prom", PROM_SIZE_MAX);
|
672 | c5705a77 | Avi Kivity | vmstate_register_ram_global(&s->prom); |
673 | d4edce38 | Avi Kivity | memory_region_set_readonly(&s->prom, true);
|
674 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, &s->prom); |
675 | 81a322d4 | Gerd Hoffmann | return 0; |
676 | 1baffa46 | Blue Swirl | } |
677 | 1baffa46 | Blue Swirl | |
678 | 999e12bb | Anthony Liguori | static Property prom_properties[] = {
|
679 | 999e12bb | Anthony Liguori | {/* end of property list */},
|
680 | 999e12bb | Anthony Liguori | }; |
681 | 999e12bb | Anthony Liguori | |
682 | 999e12bb | Anthony Liguori | static void prom_class_init(ObjectClass *klass, void *data) |
683 | 999e12bb | Anthony Liguori | { |
684 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
685 | 999e12bb | Anthony Liguori | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
686 | 999e12bb | Anthony Liguori | |
687 | 999e12bb | Anthony Liguori | k->init = prom_init1; |
688 | 39bffca2 | Anthony Liguori | dc->props = prom_properties; |
689 | 999e12bb | Anthony Liguori | } |
690 | 999e12bb | Anthony Liguori | |
691 | 39bffca2 | Anthony Liguori | static TypeInfo prom_info = {
|
692 | 39bffca2 | Anthony Liguori | .name = "openprom",
|
693 | 39bffca2 | Anthony Liguori | .parent = TYPE_SYS_BUS_DEVICE, |
694 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(PROMState),
|
695 | 39bffca2 | Anthony Liguori | .class_init = prom_class_init, |
696 | 1baffa46 | Blue Swirl | }; |
697 | 1baffa46 | Blue Swirl | |
698 | bda42033 | Blue Swirl | |
699 | bda42033 | Blue Swirl | typedef struct RamDevice |
700 | bda42033 | Blue Swirl | { |
701 | bda42033 | Blue Swirl | SysBusDevice busdev; |
702 | d4edce38 | Avi Kivity | MemoryRegion ram; |
703 | 04843626 | Blue Swirl | uint64_t size; |
704 | bda42033 | Blue Swirl | } RamDevice; |
705 | bda42033 | Blue Swirl | |
706 | bda42033 | Blue Swirl | /* System RAM */
|
707 | 81a322d4 | Gerd Hoffmann | static int ram_init1(SysBusDevice *dev) |
708 | bda42033 | Blue Swirl | { |
709 | bda42033 | Blue Swirl | RamDevice *d = FROM_SYSBUS(RamDevice, dev); |
710 | bda42033 | Blue Swirl | |
711 | c5705a77 | Avi Kivity | memory_region_init_ram(&d->ram, "sun4u.ram", d->size);
|
712 | c5705a77 | Avi Kivity | vmstate_register_ram_global(&d->ram); |
713 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, &d->ram); |
714 | 81a322d4 | Gerd Hoffmann | return 0; |
715 | bda42033 | Blue Swirl | } |
716 | bda42033 | Blue Swirl | |
717 | c227f099 | Anthony Liguori | static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size) |
718 | bda42033 | Blue Swirl | { |
719 | bda42033 | Blue Swirl | DeviceState *dev; |
720 | bda42033 | Blue Swirl | SysBusDevice *s; |
721 | bda42033 | Blue Swirl | RamDevice *d; |
722 | bda42033 | Blue Swirl | |
723 | bda42033 | Blue Swirl | /* allocate RAM */
|
724 | bda42033 | Blue Swirl | dev = qdev_create(NULL, "memory"); |
725 | bda42033 | Blue Swirl | s = sysbus_from_qdev(dev); |
726 | bda42033 | Blue Swirl | |
727 | bda42033 | Blue Swirl | d = FROM_SYSBUS(RamDevice, s); |
728 | bda42033 | Blue Swirl | d->size = RAM_size; |
729 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
730 | bda42033 | Blue Swirl | |
731 | bda42033 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
732 | bda42033 | Blue Swirl | } |
733 | bda42033 | Blue Swirl | |
734 | 999e12bb | Anthony Liguori | static Property ram_properties[] = {
|
735 | 999e12bb | Anthony Liguori | DEFINE_PROP_UINT64("size", RamDevice, size, 0), |
736 | 999e12bb | Anthony Liguori | DEFINE_PROP_END_OF_LIST(), |
737 | 999e12bb | Anthony Liguori | }; |
738 | 999e12bb | Anthony Liguori | |
739 | 999e12bb | Anthony Liguori | static void ram_class_init(ObjectClass *klass, void *data) |
740 | 999e12bb | Anthony Liguori | { |
741 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
742 | 999e12bb | Anthony Liguori | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
743 | 999e12bb | Anthony Liguori | |
744 | 999e12bb | Anthony Liguori | k->init = ram_init1; |
745 | 39bffca2 | Anthony Liguori | dc->props = ram_properties; |
746 | 999e12bb | Anthony Liguori | } |
747 | 999e12bb | Anthony Liguori | |
748 | 39bffca2 | Anthony Liguori | static TypeInfo ram_info = {
|
749 | 39bffca2 | Anthony Liguori | .name = "memory",
|
750 | 39bffca2 | Anthony Liguori | .parent = TYPE_SYS_BUS_DEVICE, |
751 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(RamDevice),
|
752 | 39bffca2 | Anthony Liguori | .class_init = ram_class_init, |
753 | bda42033 | Blue Swirl | }; |
754 | bda42033 | Blue Swirl | |
755 | f9d1465f | Andreas Färber | static SPARCCPU *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef) |
756 | 3475187d | bellard | { |
757 | 8ebdf9dc | Andreas Färber | SPARCCPU *cpu; |
758 | 98cec4a2 | Andreas Färber | CPUSPARCState *env; |
759 | e87231d4 | blueswir1 | ResetData *reset_info; |
760 | 3475187d | bellard | |
761 | 8f4efc55 | Igor V. Kovalenko | uint32_t tick_frequency = 100*1000000; |
762 | 8f4efc55 | Igor V. Kovalenko | uint32_t stick_frequency = 100*1000000; |
763 | 8f4efc55 | Igor V. Kovalenko | uint32_t hstick_frequency = 100*1000000; |
764 | 8f4efc55 | Igor V. Kovalenko | |
765 | 8ebdf9dc | Andreas Färber | if (cpu_model == NULL) { |
766 | c7ba218d | blueswir1 | cpu_model = hwdef->default_cpu_model; |
767 | 8ebdf9dc | Andreas Färber | } |
768 | 8ebdf9dc | Andreas Färber | cpu = cpu_sparc_init(cpu_model); |
769 | 8ebdf9dc | Andreas Färber | if (cpu == NULL) { |
770 | 62724a37 | blueswir1 | fprintf(stderr, "Unable to find Sparc CPU definition\n");
|
771 | 62724a37 | blueswir1 | exit(1);
|
772 | 62724a37 | blueswir1 | } |
773 | 8ebdf9dc | Andreas Färber | env = &cpu->env; |
774 | 20c9f095 | blueswir1 | |
775 | 8f4efc55 | Igor V. Kovalenko | env->tick = cpu_timer_create("tick", env, tick_irq,
|
776 | 8f4efc55 | Igor V. Kovalenko | tick_frequency, TICK_NPT_MASK); |
777 | 8f4efc55 | Igor V. Kovalenko | |
778 | 8f4efc55 | Igor V. Kovalenko | env->stick = cpu_timer_create("stick", env, stick_irq,
|
779 | 8f4efc55 | Igor V. Kovalenko | stick_frequency, TICK_INT_DIS); |
780 | 20c9f095 | blueswir1 | |
781 | 8f4efc55 | Igor V. Kovalenko | env->hstick = cpu_timer_create("hstick", env, hstick_irq,
|
782 | 8f4efc55 | Igor V. Kovalenko | hstick_frequency, TICK_INT_DIS); |
783 | e87231d4 | blueswir1 | |
784 | 7267c094 | Anthony Liguori | reset_info = g_malloc0(sizeof(ResetData));
|
785 | 403d7a2d | Andreas Färber | reset_info->cpu = cpu; |
786 | 44a99354 | Blue Swirl | reset_info->prom_addr = hwdef->prom_addr; |
787 | a08d4367 | Jan Kiszka | qemu_register_reset(main_cpu_reset, reset_info); |
788 | c68ea704 | bellard | |
789 | f9d1465f | Andreas Färber | return cpu;
|
790 | 7b833f5b | Blue Swirl | } |
791 | 7b833f5b | Blue Swirl | |
792 | 38bc50f7 | Richard Henderson | static void sun4uv_init(MemoryRegion *address_space_mem, |
793 | 38bc50f7 | Richard Henderson | ram_addr_t RAM_size, |
794 | 7b833f5b | Blue Swirl | const char *boot_devices, |
795 | 7b833f5b | Blue Swirl | const char *kernel_filename, const char *kernel_cmdline, |
796 | 7b833f5b | Blue Swirl | const char *initrd_filename, const char *cpu_model, |
797 | 7b833f5b | Blue Swirl | const struct hwdef *hwdef) |
798 | 7b833f5b | Blue Swirl | { |
799 | f9d1465f | Andreas Färber | SPARCCPU *cpu; |
800 | 98cec4a2 | Andreas Färber | CPUSPARCState *env; |
801 | 43a34704 | Blue Swirl | M48t59State *nvram; |
802 | 7b833f5b | Blue Swirl | unsigned int i; |
803 | 5f2bf0fe | Blue Swirl | uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry; |
804 | 7b833f5b | Blue Swirl | PCIBus *pci_bus, *pci_bus2, *pci_bus3; |
805 | 48a18b3c | Hervé Poussineau | ISABus *isa_bus; |
806 | 361dea40 | Blue Swirl | qemu_irq *ivec_irqs, *pbm_irqs; |
807 | f455e98c | Gerd Hoffmann | DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
808 | fd8014e1 | Gerd Hoffmann | DriveInfo *fd[MAX_FD]; |
809 | 7b833f5b | Blue Swirl | void *fw_cfg;
|
810 | 7b833f5b | Blue Swirl | |
811 | 7b833f5b | Blue Swirl | /* init CPUs */
|
812 | f9d1465f | Andreas Färber | cpu = cpu_devinit(cpu_model, hwdef); |
813 | f9d1465f | Andreas Färber | env = &cpu->env; |
814 | 7b833f5b | Blue Swirl | |
815 | bda42033 | Blue Swirl | /* set up devices */
|
816 | bda42033 | Blue Swirl | ram_init(0, RAM_size);
|
817 | 3475187d | bellard | |
818 | 1baffa46 | Blue Swirl | prom_init(hwdef->prom_addr, bios_name); |
819 | 3475187d | bellard | |
820 | 361dea40 | Blue Swirl | ivec_irqs = qemu_allocate_irqs(cpu_set_ivec_irq, env, IVEC_MAX); |
821 | 361dea40 | Blue Swirl | pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &pci_bus2, |
822 | 361dea40 | Blue Swirl | &pci_bus3, &pbm_irqs); |
823 | 78895427 | Gerd Hoffmann | pci_vga_init(pci_bus); |
824 | 83469015 | bellard | |
825 | c190ea07 | blueswir1 | // XXX Should be pci_bus3
|
826 | 361dea40 | Blue Swirl | isa_bus = pci_ebus_init(pci_bus, -1, pbm_irqs);
|
827 | c190ea07 | blueswir1 | |
828 | e87231d4 | blueswir1 | i = 0;
|
829 | e87231d4 | blueswir1 | if (hwdef->console_serial_base) {
|
830 | 38bc50f7 | Richard Henderson | serial_mm_init(address_space_mem, hwdef->console_serial_base, 0,
|
831 | 39186d8a | Richard Henderson | NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN); |
832 | e87231d4 | blueswir1 | i++; |
833 | e87231d4 | blueswir1 | } |
834 | e87231d4 | blueswir1 | for(; i < MAX_SERIAL_PORTS; i++) {
|
835 | 83469015 | bellard | if (serial_hds[i]) {
|
836 | 48a18b3c | Hervé Poussineau | serial_isa_init(isa_bus, i, serial_hds[i]); |
837 | 83469015 | bellard | } |
838 | 83469015 | bellard | } |
839 | 83469015 | bellard | |
840 | 83469015 | bellard | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { |
841 | 83469015 | bellard | if (parallel_hds[i]) {
|
842 | 48a18b3c | Hervé Poussineau | parallel_init(isa_bus, i, parallel_hds[i]); |
843 | 83469015 | bellard | } |
844 | 83469015 | bellard | } |
845 | 83469015 | bellard | |
846 | cb457d76 | aliguori | for(i = 0; i < nb_nics; i++) |
847 | 07caea31 | Markus Armbruster | pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL); |
848 | 83469015 | bellard | |
849 | 75717903 | Isaku Yamahata | ide_drive_get(hd, MAX_IDE_BUS); |
850 | e4bcb14c | ths | |
851 | 3b898dda | blueswir1 | pci_cmd646_ide_init(pci_bus, hd, 1);
|
852 | 3b898dda | blueswir1 | |
853 | 48a18b3c | Hervé Poussineau | isa_create_simple(isa_bus, "i8042");
|
854 | e4bcb14c | ths | for(i = 0; i < MAX_FD; i++) { |
855 | fd8014e1 | Gerd Hoffmann | fd[i] = drive_get(IF_FLOPPY, 0, i);
|
856 | e4bcb14c | ths | } |
857 | 48a18b3c | Hervé Poussineau | fdctrl_init_isa(isa_bus, fd); |
858 | 48a18b3c | Hervé Poussineau | nvram = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 59); |
859 | 636aa70a | Blue Swirl | |
860 | 636aa70a | Blue Swirl | initrd_size = 0;
|
861 | 5f2bf0fe | Blue Swirl | initrd_addr = 0;
|
862 | 636aa70a | Blue Swirl | kernel_size = sun4u_load_kernel(kernel_filename, initrd_filename, |
863 | 5f2bf0fe | Blue Swirl | ram_size, &initrd_size, &initrd_addr, |
864 | 5f2bf0fe | Blue Swirl | &kernel_addr, &kernel_entry); |
865 | 636aa70a | Blue Swirl | |
866 | 22548760 | blueswir1 | sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
|
867 | 5f2bf0fe | Blue Swirl | kernel_addr, kernel_size, |
868 | 0d31cb99 | blueswir1 | kernel_cmdline, |
869 | 5f2bf0fe | Blue Swirl | initrd_addr, initrd_size, |
870 | 0d31cb99 | blueswir1 | /* XXX: need an option to load a NVRAM image */
|
871 | 0d31cb99 | blueswir1 | 0,
|
872 | 0d31cb99 | blueswir1 | graphic_width, graphic_height, graphic_depth, |
873 | 0d31cb99 | blueswir1 | (uint8_t *)&nd_table[0].macaddr);
|
874 | 83469015 | bellard | |
875 | 3cce6243 | blueswir1 | fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); |
876 | 3cce6243 | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
877 | 905fdcb5 | blueswir1 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
878 | 905fdcb5 | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
879 | 5f2bf0fe | Blue Swirl | fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry); |
880 | 5f2bf0fe | Blue Swirl | fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
881 | 513f789f | blueswir1 | if (kernel_cmdline) {
|
882 | 9c9b0512 | Blue Swirl | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, |
883 | 9c9b0512 | Blue Swirl | strlen(kernel_cmdline) + 1);
|
884 | 6bb4ca57 | Blue Swirl | fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA, |
885 | 6bb4ca57 | Blue Swirl | (uint8_t*)strdup(kernel_cmdline), |
886 | 6bb4ca57 | Blue Swirl | strlen(kernel_cmdline) + 1);
|
887 | 513f789f | blueswir1 | } else {
|
888 | 9c9b0512 | Blue Swirl | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
|
889 | 513f789f | blueswir1 | } |
890 | 5f2bf0fe | Blue Swirl | fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); |
891 | 5f2bf0fe | Blue Swirl | fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); |
892 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]);
|
893 | 7589690c | Blue Swirl | |
894 | 7589690c | Blue Swirl | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); |
895 | 7589690c | Blue Swirl | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); |
896 | 7589690c | Blue Swirl | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); |
897 | 7589690c | Blue Swirl | |
898 | 513f789f | blueswir1 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
899 | 3475187d | bellard | } |
900 | 3475187d | bellard | |
901 | 905fdcb5 | blueswir1 | enum {
|
902 | 905fdcb5 | blueswir1 | sun4u_id = 0,
|
903 | 905fdcb5 | blueswir1 | sun4v_id = 64,
|
904 | e87231d4 | blueswir1 | niagara_id, |
905 | 905fdcb5 | blueswir1 | }; |
906 | 905fdcb5 | blueswir1 | |
907 | c7ba218d | blueswir1 | static const struct hwdef hwdefs[] = { |
908 | c7ba218d | blueswir1 | /* Sun4u generic PC-like machine */
|
909 | c7ba218d | blueswir1 | { |
910 | 5910b047 | Igor V. Kovalenko | .default_cpu_model = "TI UltraSparc IIi",
|
911 | 905fdcb5 | blueswir1 | .machine_id = sun4u_id, |
912 | e87231d4 | blueswir1 | .prom_addr = 0x1fff0000000ULL,
|
913 | e87231d4 | blueswir1 | .console_serial_base = 0,
|
914 | c7ba218d | blueswir1 | }, |
915 | c7ba218d | blueswir1 | /* Sun4v generic PC-like machine */
|
916 | c7ba218d | blueswir1 | { |
917 | c7ba218d | blueswir1 | .default_cpu_model = "Sun UltraSparc T1",
|
918 | 905fdcb5 | blueswir1 | .machine_id = sun4v_id, |
919 | e87231d4 | blueswir1 | .prom_addr = 0x1fff0000000ULL,
|
920 | e87231d4 | blueswir1 | .console_serial_base = 0,
|
921 | e87231d4 | blueswir1 | }, |
922 | e87231d4 | blueswir1 | /* Sun4v generic Niagara machine */
|
923 | e87231d4 | blueswir1 | { |
924 | e87231d4 | blueswir1 | .default_cpu_model = "Sun UltraSparc T1",
|
925 | e87231d4 | blueswir1 | .machine_id = niagara_id, |
926 | e87231d4 | blueswir1 | .prom_addr = 0xfff0000000ULL,
|
927 | e87231d4 | blueswir1 | .console_serial_base = 0xfff0c2c000ULL,
|
928 | c7ba218d | blueswir1 | }, |
929 | c7ba218d | blueswir1 | }; |
930 | c7ba218d | blueswir1 | |
931 | c7ba218d | blueswir1 | /* Sun4u hardware initialisation */
|
932 | c227f099 | Anthony Liguori | static void sun4u_init(ram_addr_t RAM_size, |
933 | 3023f332 | aliguori | const char *boot_devices, |
934 | c7ba218d | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
935 | c7ba218d | blueswir1 | const char *initrd_filename, const char *cpu_model) |
936 | c7ba218d | blueswir1 | { |
937 | 38bc50f7 | Richard Henderson | sun4uv_init(get_system_memory(), RAM_size, boot_devices, kernel_filename, |
938 | c7ba218d | blueswir1 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
|
939 | c7ba218d | blueswir1 | } |
940 | c7ba218d | blueswir1 | |
941 | c7ba218d | blueswir1 | /* Sun4v hardware initialisation */
|
942 | c227f099 | Anthony Liguori | static void sun4v_init(ram_addr_t RAM_size, |
943 | 3023f332 | aliguori | const char *boot_devices, |
944 | c7ba218d | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
945 | c7ba218d | blueswir1 | const char *initrd_filename, const char *cpu_model) |
946 | c7ba218d | blueswir1 | { |
947 | 38bc50f7 | Richard Henderson | sun4uv_init(get_system_memory(), RAM_size, boot_devices, kernel_filename, |
948 | c7ba218d | blueswir1 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
|
949 | c7ba218d | blueswir1 | } |
950 | c7ba218d | blueswir1 | |
951 | e87231d4 | blueswir1 | /* Niagara hardware initialisation */
|
952 | c227f099 | Anthony Liguori | static void niagara_init(ram_addr_t RAM_size, |
953 | 3023f332 | aliguori | const char *boot_devices, |
954 | e87231d4 | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
955 | e87231d4 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
956 | e87231d4 | blueswir1 | { |
957 | 38bc50f7 | Richard Henderson | sun4uv_init(get_system_memory(), RAM_size, boot_devices, kernel_filename, |
958 | e87231d4 | blueswir1 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
|
959 | e87231d4 | blueswir1 | } |
960 | e87231d4 | blueswir1 | |
961 | f80f9ec9 | Anthony Liguori | static QEMUMachine sun4u_machine = {
|
962 | 66de733b | blueswir1 | .name = "sun4u",
|
963 | 66de733b | blueswir1 | .desc = "Sun4u platform",
|
964 | 66de733b | blueswir1 | .init = sun4u_init, |
965 | 1bcee014 | blueswir1 | .max_cpus = 1, // XXX for now |
966 | 0c257437 | Anthony Liguori | .is_default = 1,
|
967 | 3475187d | bellard | }; |
968 | c7ba218d | blueswir1 | |
969 | f80f9ec9 | Anthony Liguori | static QEMUMachine sun4v_machine = {
|
970 | 66de733b | blueswir1 | .name = "sun4v",
|
971 | 66de733b | blueswir1 | .desc = "Sun4v platform",
|
972 | 66de733b | blueswir1 | .init = sun4v_init, |
973 | 1bcee014 | blueswir1 | .max_cpus = 1, // XXX for now |
974 | c7ba218d | blueswir1 | }; |
975 | e87231d4 | blueswir1 | |
976 | f80f9ec9 | Anthony Liguori | static QEMUMachine niagara_machine = {
|
977 | e87231d4 | blueswir1 | .name = "Niagara",
|
978 | e87231d4 | blueswir1 | .desc = "Sun4v platform, Niagara",
|
979 | e87231d4 | blueswir1 | .init = niagara_init, |
980 | 1bcee014 | blueswir1 | .max_cpus = 1, // XXX for now |
981 | e87231d4 | blueswir1 | }; |
982 | f80f9ec9 | Anthony Liguori | |
983 | 83f7d43a | Andreas Färber | static void sun4u_register_types(void) |
984 | 83f7d43a | Andreas Färber | { |
985 | 83f7d43a | Andreas Färber | type_register_static(&ebus_info); |
986 | 83f7d43a | Andreas Färber | type_register_static(&prom_info); |
987 | 83f7d43a | Andreas Färber | type_register_static(&ram_info); |
988 | 83f7d43a | Andreas Färber | } |
989 | 83f7d43a | Andreas Färber | |
990 | f80f9ec9 | Anthony Liguori | static void sun4u_machine_init(void) |
991 | f80f9ec9 | Anthony Liguori | { |
992 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&sun4u_machine); |
993 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&sun4v_machine); |
994 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&niagara_machine); |
995 | f80f9ec9 | Anthony Liguori | } |
996 | f80f9ec9 | Anthony Liguori | |
997 | 83f7d43a | Andreas Färber | type_init(sun4u_register_types) |
998 | f80f9ec9 | Anthony Liguori | machine_init(sun4u_machine_init); |