build: move other target-*/ objects to nested Makefile.objs
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
build: move libobj-y variable to nested Makefile.objs
build: move obj-TARGET-y variables to nested Makefile.objs
Also drop duplicate occurrence of device-hotplug.o.
Kill off cpu_state_reset()
In commit 1bba0dc932e8826a7d030df3767daf0bc339f9a2 cpu_reset()was renamed to cpu_state_reset(), to allow introducing a new cpu_reset()that would operate on QOM objects.
All callers have been updated except for one in target-mips, so drop all...
target-arm: Use cpu_reset() in cpu_arm_init()
Commit 3c30dd5a68e9fee6af67cfd0d14ed7520820f36a (target-arm: Move resethandling to arm_cpu_reset) QOM'ified CPU reset. Complete it by replacingcpu_state_reset() with cpu_reset().
Signed-off-by: Andreas Färber <afaerber@suse.de>...
target-arm/cpu.h: Make cpu_init("nonexistent cpu") return NULL
The macro definition of cpu_init meant that if cpu_arm_init()returned NULL this wouldn't result in cpu_init() itself returningNULL. This had the effect that "-cpu foo" for some unknown CPUname 'foo' would cause ARM targets to segfault rather than...
target-arm: When setting FPSCR.QC, don't clear other FPSCR bits
This patch fixes a bug affecting a variety of Neon instructions, such asVQADD.
Signed-off-by: Matt Craighead <mjcraighead@gmail.com>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Make SETEND respect bswap_code (BE8) setting
Make the SETEND instruction respect the setting of bswap_code,so that in BE8 mode we UNDEF for attempts to switch intolittle-endian mode and nop for attempts to stay in big-endianmode. (This is the inverse of the existing handling of SETEND...
target-arm: Move A9 config_base_address reset value to ARMCPU
Move the A9 config_base_address cp15 register reset value toARMCPU. This should become a QOM property so that the Highbankboard can set it without having to pull in cpu-qom.h, but atleast this avoids the implicit dependency on reset ordering...
target-arm: Change cpu_arm_init() return type to ARMCPU
Make cpu_arm_init() return a QOM ARMCPU, so that we don't need toobtain an ARMCPU through arm_env_get_cpu() in machine init code.This requires to adjust the inclusion site of cpu-qom.h and in turn,...
target-arm: Move reset handling to arm_cpu_reset
Now that cpu_reset_model_id() has gone we can move thereset code over to the class reset function and have cpu_state_resetsimply do a reset on the CPU QOM object.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: Drop cpu_reset_model_id()
cpu_reset_model_id() is now empty and we can remove it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Acked-by: Andreas Färber <afaerber@suse.de>
target-arm: Move cache ID register setup to cpu specific init fns
Move cache ID register reset out of cpu_reset_model_id() bycreating a field for the reset value in ARMCPU and setting itup in the cpu specific init functions.
target-arm: Move OMAP cp15_i_{max,min} reset to cpu_state_reset
Move the OMAP-specific cp15_i_{max,min} reset to cpu_state_reset;since these registers are only accessible on CPUs with theOMAPCP feature set there's no need to guard this reset witheither a CPUID or feature bit check....
target-arm: Move feature register setup to per-CPU init fns
Move feature register value setup to per-CPU init functions.
target-arm: Move iWMMXT wCID reset to cpu_state_reset
Move the iWMMXT wCID reset to cpu_state_reset(). Sincewe use the same value for all CPUs with this feature(with the major/minor revision fields set to the QEMUspecific 'Q' value) there's no need to create an ARMCPU...
target-arm: Drop JTAG_ID documentation
None of the machines in QEMU offer a JTAG debug interface, so this infowas unused. Further, the PXA250 ID contradicts the February 2002Developer's Manual, which has it as 0xn9264013 with n the MIDR Revision.
target-arm: Move SCTLR reset value setup to per cpu init fns
Move the reset value of SCTLR to ARMCPU, initialised inthe per-cpu init functions. It can then be reset by asimple copy, and we can drop the code from cpu_reset_model_id().
target-arm: Move CTR setup to per cpu init fns
Move CTR (cache type register) value to an ARMCPU fieldset up by per-cpu init fns.
target-arm: Move MVFR* setup to per cpu init fns
Move the MVFR* VFP feature register values to ARMCPU,so they are set up by the implementation-specific instanceinit functions rather than in cpu_reset_model_id().
target-arm: Move FPSID config to cpu init fns
Move the reset FPSID to the ARMCPU struct, and set it in theper-implementation instance init function. At reset we thenjust copy the reset value into the CPUARMState field.
target-arm: Move feature bit settings to CPU init fns
Move the setting of the feature bits from cpu_reset_model_id()to each CPU's instance init function. This requires us to movethe features field in CPUARMState so that it is not clearedon reset.
target-arm: Add QOM subclasses for each ARM cpu implementation
Register subclasses for each ARM CPU implementation.
Let arm_cpu_list() enumerate CPU subclasses in alphabetical order,except for special value "any".
Replace cpu_arm_find_by_name()'s string -> CPUID lookup by storing the...
target-arm: remind to keep arm features in sync with linux-user/elfload.c
Signed-off-by: Benoit Canet <benoit.canet@gmail.com>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Use uintptr_t for various op related functions
Use uintptr_t instead of void * or unsigned long inseveral op related functions, env->mem_io_pc andGETPC macro.
Reviewed-by: Stefan Weil <sw@weilnetz.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Userspace ARM BE8 support
Add support for ARM BE8 userspace binaries.i.e. big-endian data and little-endian code.In principle LE8 mode is also possible, but AFAIK has never actuallybeen implemented/used.
System emulation doesn't have any useable big-endian board models,...
ARM: Permit any ARMv6K CPU to read the MVFR0 and MVFR1 VFP registers.
This patch replaces the ARM_FEATURE_VFP3 test when reading MVFR registerswith a test for a new feature flag ARM_FEATURE_MVFR, and sets this featurefor all ARMv6K cores (ARM1156 is not a v6K core, yet supports MVFR; qemu...
target-arm: Minimalistic CPU QOM'ification
Introduce only one non-abstract type TYPE_ARM_CPU and do not touchcp15 registers to not interfere with Peter's ongoing remodelling.Embed CPUARMState as first (additional) field of ARMCPU.
Let CPUClass::reset() call cpu_state_reset() for now....
target-arm: Drop cpu_arm_close()
It's unused, so no need to QOM'ify it later.
Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Decode SETEND correctly in Thumb
Decode the SETEND instruction correctly in Thumb mode,rather than accidentally treating it like CPS. We don'tsupport BE8 mode, but this change brings the Thumb modein to line with behaviour in ARM mode: 'SETEND BE' is...
target-arm: Clear IT bits when taking exceptions in v7M
When taking an exception for an M profile core, we must clearthe IT bits. Since the IT bits are cached in env->condexec_bitswe must clear them there: writing the bits in env->uncached_cpsrhas no effect. (Reported as LP:944645.)...
target-arm: Fix typo in ARM946 cp15 c5 handling
Fix a typo in handling of the ARM946 cp15 c5 c0 0 1 handling(instruction access permission bits) that meant it wouldreturn the data access permission bits by mistake.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Rename CPUState -> CPUArchState
Scripted conversion: for file in .[hc] hw/.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do sed -i "s/CPUState/CPUArchState/g" $file done...
Rename cpu_reset() to cpu_state_reset()
Frees the identifier cpu_reset for QOM CPUs (manual rename).
Don't hide the parameter type behind explicit casts, use staticfunctions with strongly typed argument to indirect.
target-arm: Don't overuse CPUState
Scripted conversion: sed -i "s/CPUState/CPUARMState/g" target-arm/*.[hc] sed -i "s/#define CPUARMState/#define CPUState/" target-arm/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Anthony Liguori <aliguori@us.ibm.com>...
target-arm: Clean includes
Remove some include statements which are not needed.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Stefan Weil <sw@weilnetz.de>
target-arm/helper.c: tb_flush() on CPU reset
Since target-arm has some CPUState fields for which we take the approachof baking assumptions about them into translated code and then callingtb_flush() when the fields change, we must also tb_flush on CPU reset,...
target-arm/helper.c: Correct FPSID value for Cortex-A9
The correct FPSID for the Cortex-A9 (according to the TRM) is0x41033090 for the r0p0 that we claim to model.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
Add Cortex-A15 CPU definition
Add a definition of a Cortex-A15 CPU. Note that for the moment we donot implement any of: * Large Physical Address Extensions (LPAE) * Virtualization Extensions * Generic Timer * TrustZone (this is also true of our existing Cortex-A9 model, etc)...
Add dummy implementation of generic timer cp15 registers
Add a dummy implementation of the cp15 registers for the generictimer (found in the Cortex-A15), just sufficient for Linux todecide that it can't use it. This requires at least CNTP_CTL andCNTFRQ to be implemented as RAZ/WI; we RAZ/WI all of c14....
target-arm: Fix implementation of TLB invalidate operations
Fix some bugs in the implementation of the TLB invalidateoperations on ARM: * the 'invalidate all' op was not passing flush_global=1 to tlb_flush(); this doesn't have a practical effect since...
target-arm/helper.c: Don't assume softfloat int32 is 32 bits only
In the helper routines for VCVT float-to-int conversions, addan explicit cast rather than relying on the softfloat int32type being exactly 32 bits wide (which it is not guaranteed to be)....
arm: store the config_base_register during cpu_reset
Long term, the config_base_register will be a QDM parameter. In themeantime, models that use it need to be able to preserve it acrosscpu_reset() calls.
Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>...
target-arm: Fix errors in decode of M profile CPS
Fix errors in the decode of M profile CPS: * the decode of the I (affects PRIMASK) and F (affects FAULTMASK) bits was reversed * the FAULTMASK system register number is 19, not 17
This fixes an issue reported as LP:913925....
arm: Add dummy support for co-processor 15's secure config register
Signed-off-by: Rob Herring <rob.herring@calxeda.com>Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Don't use cpu_single_env in bank_number()
Avoid using cpu_single_env in bank_number() -- if we werecalled via the gdb stub reading or writing the CPSR thenit is NULL and we will segfault if we take the cpu_abort().
target-arm: Ignore attempts to set invalid modes in CPSR
Ignore attempts to set the CPSR mode field to an invalid value.This is UNPREDICTABLE, but we should not cpu_abort() for thingsa malicious guest (or a confused user on the gdbstub interface)can provoke....
arm: add dummy A9-specific cp15 registers
Add dummy register support for the cp15, CRn=c15 registers.
config_base_register and power_control_register currentlydefault to 0, but may have improved support after the QOMCPU patches are finished.
target-arm: Infer VFPv3 feature from VFPv4
VFP4 => VFP3
Signed-off-by: Andreas Färber <andreas.faerber@web.de>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Infer ARMv5 feature from ARMv6
V6 => V5
target-arm: Infer ARMv6 feature from v6K
V6K => V6
target-arm: Infer ARMv6(K) feature from ARMv7
V7 && M => V6V7 && !M => V6K
target-arm: Infer AUXCR feature from ARMv6
V6 && !M => AUXCR
target-arm: Infer Thumb2 feature from ARMv7
V7 => THUMB2
target-arm: Infer Thumb division feature from M profile
M => THUMB_DIV
target-arm: Infer VFP feature from VFPv3
VFP3 => VFP
arm: Fix CP15 FSR (C5) domain setting
Return the correct value in the domain field in the cp15 DFSR(C5) -- bug noticed during Xvisor development.
Signed-off-by: Jean-Christophe DUBOIS <jcd@tribudubois.net>[Peter Maydell: reworded commit message]Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Infer ARMv4T feature from ARMv5
V5 => V4T
target-arm/helper.c: Don't allocate TCG resources unless TCG enabled
Don't call arm_translate_init() (which allocates TCG resources)unless TCG is enabled.
target-arm/translate.c: Fix slightly misleading comment in Thumb decoder
Clarify some slightly misleading comments in the Thumb decoder'shandling of the memory hint space -- in particular one code pathmarked as 'UNPREDICTABLE or unallocated hint' also includes some...
target-arm: Fix use of free() in cpu_arm_close()
env is allocated in cpu_arm_init() with g_malloc0(), so free with g_free().
target-arm: Implement VFPv4 fused multiply-accumulate insns
Implement the fused multiply-accumulate instructions (VFMA, VFMS,VFNMA, VFNMS) which are new in VFPv4.
target-arm/machine.c: Restore VFP registers correctly
Fix the restoring of VFP registers on vmload.
Signed-off-by: Dmitry Koshelev <karaghiozis@gmail.com>Reviewed-by: Juan Quintela <quintela@redhat.com>[peter.maydell: improved commit message a little]...
target-arm: Rename ARM_FEATURE_DIV to _THUMB_DIV
Rename the ARM_FEATURE_DIV feature bit to _THUMB_DIV, tomake room for a new feature switch enabling DIV in the ARMencoding. (Cores may implement either (a) no divide insns(b) divide insns in Thumb encodings only (c) divide insns...
target-arm: Add ARM UDIV/SDIV support
Add support for UDIV and SDIV in ARM mode. This is a new optionalfeature for A profile cores (Thumb mode has had UDIV and SDIV forM profile cores for some time).
rsqrte_f32: No need to copy sign bit.
Indeed, the result is known to be always positive.
Signed-off-by: Christophe Lyon <christophe.lyon@st.com>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: v6 media multiply space: UNDEF on unassigned encodings
Clean up the decoding of the v6 media multiply space so that we UNDEFon unassigned encodings rather than randomly interpreting them assome instruction in this space.
Merge remote-tracking branch 'stefanha/trivial-patches' into staging
ARM: fix segfault
Fix a bug in bccd9ec5f098668576342c83d90d6d6833d61d33,target-arm/op_helper.c missed a change unlike all other targets.This lead to a NULL pointer dereferences.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-arm: Fix typo
The command line option is called -kernel, not -kenrel.
Cc: Paul Brook <paul@codesourcery.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Andreas Färber <andreas.faerber@web.de>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
softmmu_header: pass CPUState to tlb_fill
Pass CPUState pointer to tlb_fill() instead of architecture localcpu_single_env hacks.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Use glib memory allocation and free functions
qemu_malloc/qemu_free no longer exist after this commit.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Merge remote-tracking branch 'pm-arm/for-upstream' into pm
Remove unused is_softmmu parameter from cpu_handle_mmu_fault
Parameter is_softmmu (and its evil mutant twin brother is_softmuu)is not used in cpu_*_handle_mmu_fault() functions, remove themand adjust callers.
Acked-by: Richard Henderson <rth@twiddle.net>...
exec.h cleanup
Move softmmu_exec.h include directives from target-*/exec.h totarget-*/op_helper.c. Move also various other stuff only used inop_helper.c there.
Define global env in dyngen-exec.h.
For i386, move wrappers for segment and FPU helpers from user-exec.c...
target-arm: support for ARM1176JZF-s cores
Add support for v6K ARM1176JZF-S. This core includes the VA<->PAtranslation capability and security extensions.
Signed-off-by: Jamie Iles <jamie@jamieiles.com>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Mark 1136r1 as a v6K core
The 1136r1 is actually a v6K core (unlike the 1136r0); mark it as such,thus enabling the TLS registers, NOP hints, CLREX, half and byte wideexclusive load/stores, etc.
The VA-to-PA translation registers are not present on 1136r1, so...
target-arm: Support v6 barriers in linux-user mode
ARMv6 implemented various operations as special cases of cp15 accesseswhich are true instructions in v7; this includes barriers (DMB, DSB, ISB).Catch this special case at translate time, so that it works in linux-user...
target-arm: Handle UNDEF and UNPREDICTABLE cases for VLDM, VSTM
Handle the UNDEF and UNPREDICTABLE cases for VLDM and VSTM. Inparticular, we now generate an undef exception for overlarge imm8values rather than generating 1000+ TCG ops and hitting an assertion....
target-arm: UNDEF on a VCVTT/VCVTB UNPREDICTABLE to avoid TCG assert
VCVTT/VCVTB with bit 8 set is UNPREDICTABLE; we choose to UNDEF.This avoids a TCG assert later when the VCVTT/VCVTB code tries touse a source register that wasn't ever set up.
We pull the check for the presence of the half-precision extension...
target-arm: Don't print debug messages for various UNDEF cases
Remove some stray printfs for cases which don't generally happen(some VFP UNDEF cases, reads and writes to unknown cp14 registers);we should simply generate an UNDEF when the instruction is executed....
target-arm: make VMSAv7 remapping and AP dependent on V6K
The VMSAv7 remapping and access permissions were introduced in ARMv6Kand not ARMv7.
Correct spelling of licensed
Correct typos of "licenced" to "licensed".
Reviewed-by: Stefan Weil <weil@mail.berlios.de>Reviewed-by: Andreas F=E4rber <andreas.faerber@web.de>Signed-off-by: Matthew Fernandez <matthew.fernandez@gmail.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Merge branch 'for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm
arm: Add const attribute to some arm_boot_info pointers
Parameter 'info' is const, so add the missing attribute.
v2:Add 'const' to the local variable info in do_cpu_reset() and tothe boot_info field in CPUARMState (suggested by Peter Maydell).
Cc: Andrzej Zaborowski <balrogg@gmail.com>...
Remove exec-all.h include directives
Most exec-all.h include directives are now useless, remove them.
Move cpu_has_work and cpu_pc_from_tb to cpu.h
Move functions cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h. This isneeded by later patches.
exec.h: fix coding style and change cpu_has_work to return bool
Before the next patch, fix coding style of the areas affected.
Change the type of the return value from cpu_has_work() andqemu_cpu_has_work() to bool.
cpu_loop_exit: avoid using AREG0
Make cpu_loop_exit() take a parameter for CPUState instead of relyingon global env.
target-arm: Fix BASEPRI, BASEPRI_MAX, and FAULTMASK access
Correct the decode of the register numbers for BASEPRI, BASEPRI_MAXand FAULTMASK, according to "ARMv7-M Architecture Reference Manual" issue D section "B5.2.3 MRS" and "B5.2.3 MSR".
Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>...
target-arm: Minimal implementation of performance counters
Newer Linux kernels assume the existence of the performance countercp15 registers. Provide a minimal implementation of these registers.We support no events. This should be compliant with the ARM ARM,...
Revert "target-arm: Use global env in neon_helper.c helpers"
This effectively reverts commit 2a3f75b42ac255be09ec2939b96c549ec830efd3so that we return to passing CPUState to helpers as an explicit parameter.(There were a number of conflicts in target-arm/translate.c which had...
target-arm: Pass fp status pointer explicitly to neon fp helpers
Make the Neon helpers for various floating point operations take anexplicit pointer to the float_status they use, so they don't rely onthe global environment pointer any more. This also allows us to drop...
target-arm: Make VFP binop helpers take pointer to fpstatus, not CPUState
Make the VFP binop helper functions take a pointer to the fp status, notthe entire CPUState. This will allow us to use them for Neon operations too.
target-arm: Add helper function to generate code to get fpstatus pointer
Add and use a helper function which returns a TCGv which is a pointerto the fp_status for either Neon or VFP operations.
Revert "target-arm: Use global env in iwmmxt_helper.c helpers"
This reverts commit 947a2fa21b61703802a660a938cabd7b3600ee79,returning the iwmmxt helpers to passing env in as a parameter.
target-arm: BKPT instructions should raise prefetch aborts with IFSR type 00010
Signed-off-by: Alex Zuepke <azuepke@sysgo.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: Fix compilation failure for 64 bit hosts
Use the correct _ptr aliases for manipulating the pointer tothe fp_status; this fixes a compilation failure on 64 bit hosts.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Acked-by: Stefan Weil <weil@mail.berlios.de>...
target-arm/exec.h: Remove unused #define of M0
Remove a preprocessor #define which is never used.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: Signal InvalidOp for Neon GE and GT compares of QNaN
If the input to a Neon float comparison is a quiet NaN, the ARM ARMspecifies that we should raise InvalidOp if the comparison is GE or GTbut not for EQ. (Signaling NaNs raise InvalidOp regardless). This means...