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1 | 3cbee15b | j_mayer | /*
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2 | 3cbee15b | j_mayer | * PowerMac MacIO device emulation
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3 | 3cbee15b | j_mayer | *
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4 | 3cbee15b | j_mayer | * Copyright (c) 2005-2007 Fabrice Bellard
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5 | 3cbee15b | j_mayer | * Copyright (c) 2007 Jocelyn Mayer
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6 | 3cbee15b | j_mayer | *
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7 | 3cbee15b | j_mayer | * Permission is hereby granted, free of charge, to any person obtaining a copy
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8 | 3cbee15b | j_mayer | * of this software and associated documentation files (the "Software"), to deal
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9 | 3cbee15b | j_mayer | * in the Software without restriction, including without limitation the rights
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10 | 3cbee15b | j_mayer | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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11 | 3cbee15b | j_mayer | * copies of the Software, and to permit persons to whom the Software is
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12 | 3cbee15b | j_mayer | * furnished to do so, subject to the following conditions:
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13 | 3cbee15b | j_mayer | *
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14 | 3cbee15b | j_mayer | * The above copyright notice and this permission notice shall be included in
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15 | 3cbee15b | j_mayer | * all copies or substantial portions of the Software.
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16 | 3cbee15b | j_mayer | *
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17 | 3cbee15b | j_mayer | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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18 | 3cbee15b | j_mayer | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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19 | 3cbee15b | j_mayer | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 | 3cbee15b | j_mayer | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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21 | 3cbee15b | j_mayer | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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22 | 3cbee15b | j_mayer | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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23 | 3cbee15b | j_mayer | * THE SOFTWARE.
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24 | 3cbee15b | j_mayer | */
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25 | 87ecb68b | pbrook | #include "hw.h" |
26 | 3cbee15b | j_mayer | #include "ppc_mac.h" |
27 | 87ecb68b | pbrook | #include "pci.h" |
28 | 3cbee15b | j_mayer | |
29 | 3cbee15b | j_mayer | typedef struct macio_state_t macio_state_t; |
30 | 3cbee15b | j_mayer | struct macio_state_t {
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31 | 3cbee15b | j_mayer | int is_oldworld;
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32 | 3cbee15b | j_mayer | int pic_mem_index;
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33 | 3cbee15b | j_mayer | int dbdma_mem_index;
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34 | 3cbee15b | j_mayer | int cuda_mem_index;
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35 | 74e91155 | j_mayer | void *nvram;
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36 | 3cbee15b | j_mayer | int nb_ide;
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37 | 3cbee15b | j_mayer | int ide_mem_index[4]; |
38 | 3cbee15b | j_mayer | }; |
39 | 3cbee15b | j_mayer | |
40 | 3cbee15b | j_mayer | static void macio_map (PCIDevice *pci_dev, int region_num, |
41 | 3cbee15b | j_mayer | uint32_t addr, uint32_t size, int type)
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42 | 3cbee15b | j_mayer | { |
43 | 3cbee15b | j_mayer | macio_state_t *macio_state; |
44 | 3cbee15b | j_mayer | int i;
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45 | 3cbee15b | j_mayer | |
46 | 3cbee15b | j_mayer | macio_state = (macio_state_t *)(pci_dev + 1);
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47 | 3cbee15b | j_mayer | if (macio_state->pic_mem_index >= 0) { |
48 | 3cbee15b | j_mayer | if (macio_state->is_oldworld) {
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49 | 3cbee15b | j_mayer | /* Heathrow PIC */
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50 | 3cbee15b | j_mayer | cpu_register_physical_memory(addr + 0x00000, 0x1000, |
51 | 3cbee15b | j_mayer | macio_state->pic_mem_index); |
52 | 3cbee15b | j_mayer | } else {
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53 | 3cbee15b | j_mayer | /* OpenPIC */
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54 | 3cbee15b | j_mayer | cpu_register_physical_memory(addr + 0x40000, 0x40000, |
55 | 3cbee15b | j_mayer | macio_state->pic_mem_index); |
56 | 3cbee15b | j_mayer | } |
57 | 3cbee15b | j_mayer | } |
58 | 3cbee15b | j_mayer | if (macio_state->dbdma_mem_index >= 0) { |
59 | 3cbee15b | j_mayer | cpu_register_physical_memory(addr + 0x08000, 0x1000, |
60 | 3cbee15b | j_mayer | macio_state->dbdma_mem_index); |
61 | 3cbee15b | j_mayer | } |
62 | 3cbee15b | j_mayer | if (macio_state->cuda_mem_index >= 0) { |
63 | 3cbee15b | j_mayer | cpu_register_physical_memory(addr + 0x16000, 0x2000, |
64 | 3cbee15b | j_mayer | macio_state->cuda_mem_index); |
65 | 3cbee15b | j_mayer | } |
66 | 3cbee15b | j_mayer | for (i = 0; i < macio_state->nb_ide; i++) { |
67 | 3cbee15b | j_mayer | if (macio_state->ide_mem_index[i] >= 0) { |
68 | 3cbee15b | j_mayer | cpu_register_physical_memory(addr + 0x1f000 + (i * 0x1000), 0x1000, |
69 | 3cbee15b | j_mayer | macio_state->ide_mem_index[i]); |
70 | 3cbee15b | j_mayer | } |
71 | 3cbee15b | j_mayer | } |
72 | 74e91155 | j_mayer | if (macio_state->nvram != NULL) |
73 | 74e91155 | j_mayer | macio_nvram_map(macio_state->nvram, addr + 0x60000);
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74 | 3cbee15b | j_mayer | } |
75 | 3cbee15b | j_mayer | |
76 | 3cbee15b | j_mayer | void macio_init (PCIBus *bus, int device_id, int is_oldworld, int pic_mem_index, |
77 | 74e91155 | j_mayer | int dbdma_mem_index, int cuda_mem_index, void *nvram, |
78 | 3cbee15b | j_mayer | int nb_ide, int *ide_mem_index) |
79 | 3cbee15b | j_mayer | { |
80 | 3cbee15b | j_mayer | PCIDevice *d; |
81 | 3cbee15b | j_mayer | macio_state_t *macio_state; |
82 | 3cbee15b | j_mayer | int i;
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83 | 3cbee15b | j_mayer | |
84 | 3cbee15b | j_mayer | d = pci_register_device(bus, "macio",
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85 | 3cbee15b | j_mayer | sizeof(PCIDevice) + sizeof(macio_state_t), |
86 | 3cbee15b | j_mayer | -1, NULL, NULL); |
87 | 3cbee15b | j_mayer | macio_state = (macio_state_t *)(d + 1);
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88 | 3cbee15b | j_mayer | macio_state->is_oldworld = is_oldworld; |
89 | 3cbee15b | j_mayer | macio_state->pic_mem_index = pic_mem_index; |
90 | 3cbee15b | j_mayer | macio_state->dbdma_mem_index = dbdma_mem_index; |
91 | 3cbee15b | j_mayer | macio_state->cuda_mem_index = cuda_mem_index; |
92 | 74e91155 | j_mayer | macio_state->nvram = nvram; |
93 | 3cbee15b | j_mayer | if (nb_ide > 4) |
94 | 3cbee15b | j_mayer | nb_ide = 4;
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95 | 3cbee15b | j_mayer | macio_state->nb_ide = nb_ide; |
96 | 3cbee15b | j_mayer | for (i = 0; i < nb_ide; i++) |
97 | 3cbee15b | j_mayer | macio_state->ide_mem_index[i] = ide_mem_index[i]; |
98 | 3cbee15b | j_mayer | for (; i < 4; i++) |
99 | 3cbee15b | j_mayer | macio_state->ide_mem_index[i] = -1;
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100 | 3cbee15b | j_mayer | /* Note: this code is strongly inspirated from the corresponding code
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101 | 3cbee15b | j_mayer | in PearPC */
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102 | 3cbee15b | j_mayer | d->config[0x00] = 0x6b; // vendor_id |
103 | 3cbee15b | j_mayer | d->config[0x01] = 0x10; |
104 | 3cbee15b | j_mayer | d->config[0x02] = device_id;
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105 | 3cbee15b | j_mayer | d->config[0x03] = device_id >> 8; |
106 | 3cbee15b | j_mayer | |
107 | 3cbee15b | j_mayer | d->config[0x0a] = 0x00; // class_sub = pci2pci |
108 | 3cbee15b | j_mayer | d->config[0x0b] = 0xff; // class_base = bridge |
109 | 3cbee15b | j_mayer | d->config[0x0e] = 0x00; // header_type |
110 | 3cbee15b | j_mayer | |
111 | 3cbee15b | j_mayer | d->config[0x3d] = 0x01; // interrupt on pin 1 |
112 | 3cbee15b | j_mayer | |
113 | 3cbee15b | j_mayer | pci_register_io_region(d, 0, 0x80000, |
114 | 3cbee15b | j_mayer | PCI_ADDRESS_SPACE_MEM, macio_map); |
115 | 3cbee15b | j_mayer | } |