root / hw / ppc405_boards.c @ c75a823c
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1 | 1a6c0886 | j_mayer | /*
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2 | 1a6c0886 | j_mayer | * QEMU PowerPC 405 evaluation boards emulation
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3 | 5fafdf24 | ths | *
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4 | 1a6c0886 | j_mayer | * Copyright (c) 2007 Jocelyn Mayer
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5 | 5fafdf24 | ths | *
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6 | 1a6c0886 | j_mayer | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 1a6c0886 | j_mayer | * of this software and associated documentation files (the "Software"), to deal
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8 | 1a6c0886 | j_mayer | * in the Software without restriction, including without limitation the rights
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9 | 1a6c0886 | j_mayer | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 1a6c0886 | j_mayer | * copies of the Software, and to permit persons to whom the Software is
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11 | 1a6c0886 | j_mayer | * furnished to do so, subject to the following conditions:
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12 | 1a6c0886 | j_mayer | *
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13 | 1a6c0886 | j_mayer | * The above copyright notice and this permission notice shall be included in
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14 | 1a6c0886 | j_mayer | * all copies or substantial portions of the Software.
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15 | 1a6c0886 | j_mayer | *
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16 | 1a6c0886 | j_mayer | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 1a6c0886 | j_mayer | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 1a6c0886 | j_mayer | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 1a6c0886 | j_mayer | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 1a6c0886 | j_mayer | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 1a6c0886 | j_mayer | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 1a6c0886 | j_mayer | * THE SOFTWARE.
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23 | 1a6c0886 | j_mayer | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "ppc.h" |
26 | 1a6c0886 | j_mayer | #include "ppc405.h" |
27 | 87ecb68b | pbrook | #include "nvram.h" |
28 | 87ecb68b | pbrook | #include "flash.h" |
29 | 87ecb68b | pbrook | #include "sysemu.h" |
30 | 87ecb68b | pbrook | #include "block.h" |
31 | 87ecb68b | pbrook | #include "boards.h" |
32 | 1a6c0886 | j_mayer | |
33 | 1a6c0886 | j_mayer | extern int loglevel; |
34 | 1a6c0886 | j_mayer | extern FILE *logfile;
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35 | 1a6c0886 | j_mayer | |
36 | 1a6c0886 | j_mayer | #define BIOS_FILENAME "ppc405_rom.bin" |
37 | 1a6c0886 | j_mayer | #undef BIOS_SIZE
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38 | 1a6c0886 | j_mayer | #define BIOS_SIZE (2048 * 1024) |
39 | 1a6c0886 | j_mayer | |
40 | 1a6c0886 | j_mayer | #define KERNEL_LOAD_ADDR 0x00000000 |
41 | 1a6c0886 | j_mayer | #define INITRD_LOAD_ADDR 0x01800000 |
42 | 1a6c0886 | j_mayer | |
43 | 1a6c0886 | j_mayer | #define USE_FLASH_BIOS
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44 | 1a6c0886 | j_mayer | |
45 | 1a6c0886 | j_mayer | #define DEBUG_BOARD_INIT
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46 | 1a6c0886 | j_mayer | |
47 | 1a6c0886 | j_mayer | /*****************************************************************************/
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48 | 1a6c0886 | j_mayer | /* PPC405EP reference board (IBM) */
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49 | 1a6c0886 | j_mayer | /* Standalone board with:
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50 | 1a6c0886 | j_mayer | * - PowerPC 405EP CPU
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51 | 1a6c0886 | j_mayer | * - SDRAM (0x00000000)
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52 | 1a6c0886 | j_mayer | * - Flash (0xFFF80000)
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53 | 1a6c0886 | j_mayer | * - SRAM (0xFFF00000)
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54 | 1a6c0886 | j_mayer | * - NVRAM (0xF0000000)
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55 | 1a6c0886 | j_mayer | * - FPGA (0xF0300000)
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56 | 1a6c0886 | j_mayer | */
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57 | 1a6c0886 | j_mayer | typedef struct ref405ep_fpga_t ref405ep_fpga_t; |
58 | 1a6c0886 | j_mayer | struct ref405ep_fpga_t {
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59 | 1a6c0886 | j_mayer | uint32_t base; |
60 | 1a6c0886 | j_mayer | uint8_t reg0; |
61 | 1a6c0886 | j_mayer | uint8_t reg1; |
62 | 1a6c0886 | j_mayer | }; |
63 | 1a6c0886 | j_mayer | |
64 | 1a6c0886 | j_mayer | static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr) |
65 | 1a6c0886 | j_mayer | { |
66 | 1a6c0886 | j_mayer | ref405ep_fpga_t *fpga; |
67 | 1a6c0886 | j_mayer | uint32_t ret; |
68 | 1a6c0886 | j_mayer | |
69 | 1a6c0886 | j_mayer | fpga = opaque; |
70 | 1a6c0886 | j_mayer | addr -= fpga->base; |
71 | 1a6c0886 | j_mayer | switch (addr) {
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72 | 1a6c0886 | j_mayer | case 0x0: |
73 | 1a6c0886 | j_mayer | ret = fpga->reg0; |
74 | 1a6c0886 | j_mayer | break;
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75 | 1a6c0886 | j_mayer | case 0x1: |
76 | 1a6c0886 | j_mayer | ret = fpga->reg1; |
77 | 1a6c0886 | j_mayer | break;
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78 | 1a6c0886 | j_mayer | default:
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79 | 1a6c0886 | j_mayer | ret = 0;
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80 | 1a6c0886 | j_mayer | break;
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81 | 1a6c0886 | j_mayer | } |
82 | 1a6c0886 | j_mayer | |
83 | 1a6c0886 | j_mayer | return ret;
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84 | 1a6c0886 | j_mayer | } |
85 | 1a6c0886 | j_mayer | |
86 | 1a6c0886 | j_mayer | static void ref405ep_fpga_writeb (void *opaque, |
87 | 1a6c0886 | j_mayer | target_phys_addr_t addr, uint32_t value) |
88 | 1a6c0886 | j_mayer | { |
89 | 1a6c0886 | j_mayer | ref405ep_fpga_t *fpga; |
90 | 1a6c0886 | j_mayer | |
91 | 1a6c0886 | j_mayer | fpga = opaque; |
92 | 1a6c0886 | j_mayer | addr -= fpga->base; |
93 | 1a6c0886 | j_mayer | switch (addr) {
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94 | 1a6c0886 | j_mayer | case 0x0: |
95 | 1a6c0886 | j_mayer | /* Read only */
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96 | 1a6c0886 | j_mayer | break;
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97 | 1a6c0886 | j_mayer | case 0x1: |
98 | 1a6c0886 | j_mayer | fpga->reg1 = value; |
99 | 1a6c0886 | j_mayer | break;
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100 | 1a6c0886 | j_mayer | default:
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101 | 1a6c0886 | j_mayer | break;
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102 | 1a6c0886 | j_mayer | } |
103 | 1a6c0886 | j_mayer | } |
104 | 1a6c0886 | j_mayer | |
105 | 1a6c0886 | j_mayer | static uint32_t ref405ep_fpga_readw (void *opaque, target_phys_addr_t addr) |
106 | 1a6c0886 | j_mayer | { |
107 | 1a6c0886 | j_mayer | uint32_t ret; |
108 | 1a6c0886 | j_mayer | |
109 | 1a6c0886 | j_mayer | ret = ref405ep_fpga_readb(opaque, addr) << 8;
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110 | 1a6c0886 | j_mayer | ret |= ref405ep_fpga_readb(opaque, addr + 1);
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111 | 1a6c0886 | j_mayer | |
112 | 1a6c0886 | j_mayer | return ret;
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113 | 1a6c0886 | j_mayer | } |
114 | 1a6c0886 | j_mayer | |
115 | 1a6c0886 | j_mayer | static void ref405ep_fpga_writew (void *opaque, |
116 | 1a6c0886 | j_mayer | target_phys_addr_t addr, uint32_t value) |
117 | 1a6c0886 | j_mayer | { |
118 | 1a6c0886 | j_mayer | ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF); |
119 | 1a6c0886 | j_mayer | ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF); |
120 | 1a6c0886 | j_mayer | } |
121 | 1a6c0886 | j_mayer | |
122 | 1a6c0886 | j_mayer | static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr) |
123 | 1a6c0886 | j_mayer | { |
124 | 1a6c0886 | j_mayer | uint32_t ret; |
125 | 1a6c0886 | j_mayer | |
126 | 1a6c0886 | j_mayer | ret = ref405ep_fpga_readb(opaque, addr) << 24;
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127 | 1a6c0886 | j_mayer | ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16; |
128 | 1a6c0886 | j_mayer | ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8; |
129 | 1a6c0886 | j_mayer | ret |= ref405ep_fpga_readb(opaque, addr + 3);
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130 | 1a6c0886 | j_mayer | |
131 | 1a6c0886 | j_mayer | return ret;
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132 | 1a6c0886 | j_mayer | } |
133 | 1a6c0886 | j_mayer | |
134 | 1a6c0886 | j_mayer | static void ref405ep_fpga_writel (void *opaque, |
135 | 1a6c0886 | j_mayer | target_phys_addr_t addr, uint32_t value) |
136 | 1a6c0886 | j_mayer | { |
137 | 1a6c0886 | j_mayer | ref405ep_fpga_writel(opaque, addr, (value >> 24) & 0xFF); |
138 | 1a6c0886 | j_mayer | ref405ep_fpga_writel(opaque, addr + 1, (value >> 16) & 0xFF); |
139 | 1a6c0886 | j_mayer | ref405ep_fpga_writel(opaque, addr + 2, (value >> 8) & 0xFF); |
140 | 1a6c0886 | j_mayer | ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF); |
141 | 1a6c0886 | j_mayer | } |
142 | 1a6c0886 | j_mayer | |
143 | 1a6c0886 | j_mayer | static CPUReadMemoryFunc *ref405ep_fpga_read[] = {
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144 | 1a6c0886 | j_mayer | &ref405ep_fpga_readb, |
145 | 1a6c0886 | j_mayer | &ref405ep_fpga_readw, |
146 | 1a6c0886 | j_mayer | &ref405ep_fpga_readl, |
147 | 1a6c0886 | j_mayer | }; |
148 | 1a6c0886 | j_mayer | |
149 | 1a6c0886 | j_mayer | static CPUWriteMemoryFunc *ref405ep_fpga_write[] = {
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150 | 1a6c0886 | j_mayer | &ref405ep_fpga_writeb, |
151 | 1a6c0886 | j_mayer | &ref405ep_fpga_writew, |
152 | 1a6c0886 | j_mayer | &ref405ep_fpga_writel, |
153 | 1a6c0886 | j_mayer | }; |
154 | 1a6c0886 | j_mayer | |
155 | 1a6c0886 | j_mayer | static void ref405ep_fpga_reset (void *opaque) |
156 | 1a6c0886 | j_mayer | { |
157 | 1a6c0886 | j_mayer | ref405ep_fpga_t *fpga; |
158 | 1a6c0886 | j_mayer | |
159 | 1a6c0886 | j_mayer | fpga = opaque; |
160 | 1a6c0886 | j_mayer | fpga->reg0 = 0x00;
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161 | 1a6c0886 | j_mayer | fpga->reg1 = 0x0F;
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162 | 1a6c0886 | j_mayer | } |
163 | 1a6c0886 | j_mayer | |
164 | 1a6c0886 | j_mayer | static void ref405ep_fpga_init (uint32_t base) |
165 | 1a6c0886 | j_mayer | { |
166 | 1a6c0886 | j_mayer | ref405ep_fpga_t *fpga; |
167 | 1a6c0886 | j_mayer | int fpga_memory;
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168 | 1a6c0886 | j_mayer | |
169 | 1a6c0886 | j_mayer | fpga = qemu_mallocz(sizeof(ref405ep_fpga_t));
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170 | 1a6c0886 | j_mayer | if (fpga != NULL) { |
171 | 1a6c0886 | j_mayer | fpga->base = base; |
172 | 1a6c0886 | j_mayer | fpga_memory = cpu_register_io_memory(0, ref405ep_fpga_read,
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173 | 1a6c0886 | j_mayer | ref405ep_fpga_write, fpga); |
174 | 1a6c0886 | j_mayer | cpu_register_physical_memory(base, 0x00000100, fpga_memory);
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175 | 1a6c0886 | j_mayer | ref405ep_fpga_reset(fpga); |
176 | 1a6c0886 | j_mayer | qemu_register_reset(&ref405ep_fpga_reset, fpga); |
177 | 1a6c0886 | j_mayer | } |
178 | 1a6c0886 | j_mayer | } |
179 | 1a6c0886 | j_mayer | |
180 | 00f82b8a | aurel32 | static void ref405ep_init (ram_addr_t ram_size, int vga_ram_size, |
181 | 6ac0e82d | balrog | const char *boot_device, DisplayState *ds, |
182 | 5fafdf24 | ths | const char *kernel_filename, |
183 | 1a6c0886 | j_mayer | const char *kernel_cmdline, |
184 | 1a6c0886 | j_mayer | const char *initrd_filename, |
185 | 1a6c0886 | j_mayer | const char *cpu_model) |
186 | 1a6c0886 | j_mayer | { |
187 | 1a6c0886 | j_mayer | char buf[1024]; |
188 | 1a6c0886 | j_mayer | ppc4xx_bd_info_t bd; |
189 | 1a6c0886 | j_mayer | CPUPPCState *env; |
190 | 1a6c0886 | j_mayer | qemu_irq *pic; |
191 | 1a6c0886 | j_mayer | ram_addr_t sram_offset, bios_offset, bdloc; |
192 | 71db710f | blueswir1 | target_phys_addr_t ram_bases[2], ram_sizes[2]; |
193 | 1a6c0886 | j_mayer | target_ulong sram_size, bios_size; |
194 | 1a6c0886 | j_mayer | //int phy_addr = 0;
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195 | 1a6c0886 | j_mayer | //static int phy_addr = 1;
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196 | 1a6c0886 | j_mayer | target_ulong kernel_base, kernel_size, initrd_base, initrd_size; |
197 | 1a6c0886 | j_mayer | int linux_boot;
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198 | 1a6c0886 | j_mayer | int fl_idx, fl_sectors, len;
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199 | 6ac0e82d | balrog | int ppc_boot_device = boot_device[0]; |
200 | e4bcb14c | ths | int index;
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201 | 1a6c0886 | j_mayer | |
202 | 1a6c0886 | j_mayer | /* XXX: fix this */
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203 | 1a6c0886 | j_mayer | ram_bases[0] = 0x00000000; |
204 | 1a6c0886 | j_mayer | ram_sizes[0] = 0x08000000; |
205 | 1a6c0886 | j_mayer | ram_bases[1] = 0x00000000; |
206 | 1a6c0886 | j_mayer | ram_sizes[1] = 0x00000000; |
207 | 1a6c0886 | j_mayer | ram_size = 128 * 1024 * 1024; |
208 | 1a6c0886 | j_mayer | #ifdef DEBUG_BOARD_INIT
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209 | 1a6c0886 | j_mayer | printf("%s: register cpu\n", __func__);
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210 | 1a6c0886 | j_mayer | #endif
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211 | 1a6c0886 | j_mayer | env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic, &sram_offset,
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212 | 1a6c0886 | j_mayer | kernel_filename == NULL ? 0 : 1); |
213 | 1a6c0886 | j_mayer | /* allocate SRAM */
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214 | 1a6c0886 | j_mayer | #ifdef DEBUG_BOARD_INIT
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215 | 1a6c0886 | j_mayer | printf("%s: register SRAM at offset %08lx\n", __func__, sram_offset);
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216 | 1a6c0886 | j_mayer | #endif
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217 | 1a6c0886 | j_mayer | sram_size = 512 * 1024; |
218 | 1a6c0886 | j_mayer | cpu_register_physical_memory(0xFFF00000, sram_size,
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219 | 1a6c0886 | j_mayer | sram_offset | IO_MEM_RAM); |
220 | 1a6c0886 | j_mayer | /* allocate and load BIOS */
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221 | 1a6c0886 | j_mayer | #ifdef DEBUG_BOARD_INIT
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222 | 1a6c0886 | j_mayer | printf("%s: register BIOS\n", __func__);
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223 | 1a6c0886 | j_mayer | #endif
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224 | 1a6c0886 | j_mayer | bios_offset = sram_offset + sram_size; |
225 | 1a6c0886 | j_mayer | fl_idx = 0;
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226 | 1a6c0886 | j_mayer | #ifdef USE_FLASH_BIOS
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227 | e4bcb14c | ths | index = drive_get_index(IF_PFLASH, 0, fl_idx);
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228 | e4bcb14c | ths | if (index != -1) { |
229 | e4bcb14c | ths | bios_size = bdrv_getlength(drives_table[index].bdrv); |
230 | 1a6c0886 | j_mayer | fl_sectors = (bios_size + 65535) >> 16; |
231 | 1a6c0886 | j_mayer | #ifdef DEBUG_BOARD_INIT
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232 | 1a6c0886 | j_mayer | printf("Register parallel flash %d size " ADDRX " at offset %08lx " |
233 | 1a6c0886 | j_mayer | " addr " ADDRX " '%s' %d\n", |
234 | 1a6c0886 | j_mayer | fl_idx, bios_size, bios_offset, -bios_size, |
235 | e4bcb14c | ths | bdrv_get_device_name(drives_table[index].bdrv), fl_sectors); |
236 | 1a6c0886 | j_mayer | #endif
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237 | 88eeee0a | balrog | pflash_cfi02_register((uint32_t)(-bios_size), bios_offset, |
238 | 4fbd24ba | balrog | drives_table[index].bdrv, 65536, fl_sectors, 1, |
239 | 4fbd24ba | balrog | 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA); |
240 | 1a6c0886 | j_mayer | fl_idx++; |
241 | 1a6c0886 | j_mayer | } else
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242 | 1a6c0886 | j_mayer | #endif
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243 | 1a6c0886 | j_mayer | { |
244 | 1a6c0886 | j_mayer | #ifdef DEBUG_BOARD_INIT
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245 | 1a6c0886 | j_mayer | printf("Load BIOS from file\n");
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246 | 1a6c0886 | j_mayer | #endif
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247 | 1192dad8 | j_mayer | if (bios_name == NULL) |
248 | 1192dad8 | j_mayer | bios_name = BIOS_FILENAME; |
249 | 1192dad8 | j_mayer | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
250 | 1a6c0886 | j_mayer | bios_size = load_image(buf, phys_ram_base + bios_offset); |
251 | 1a6c0886 | j_mayer | if (bios_size < 0 || bios_size > BIOS_SIZE) { |
252 | 1a6c0886 | j_mayer | fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", buf);
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253 | 1a6c0886 | j_mayer | exit(1);
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254 | 1a6c0886 | j_mayer | } |
255 | 1a6c0886 | j_mayer | bios_size = (bios_size + 0xfff) & ~0xfff; |
256 | 5fafdf24 | ths | cpu_register_physical_memory((uint32_t)(-bios_size), |
257 | 1a6c0886 | j_mayer | bios_size, bios_offset | IO_MEM_ROM); |
258 | 1a6c0886 | j_mayer | } |
259 | 1a6c0886 | j_mayer | bios_offset += bios_size; |
260 | 1a6c0886 | j_mayer | /* Register FPGA */
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261 | 1a6c0886 | j_mayer | #ifdef DEBUG_BOARD_INIT
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262 | 1a6c0886 | j_mayer | printf("%s: register FPGA\n", __func__);
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263 | 1a6c0886 | j_mayer | #endif
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264 | 1a6c0886 | j_mayer | ref405ep_fpga_init(0xF0300000);
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265 | 1a6c0886 | j_mayer | /* Register NVRAM */
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266 | 1a6c0886 | j_mayer | #ifdef DEBUG_BOARD_INIT
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267 | 1a6c0886 | j_mayer | printf("%s: register NVRAM\n", __func__);
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268 | 1a6c0886 | j_mayer | #endif
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269 | 1a6c0886 | j_mayer | m48t59_init(NULL, 0xF0000000, 0, 8192, 8); |
270 | 1a6c0886 | j_mayer | /* Load kernel */
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271 | 1a6c0886 | j_mayer | linux_boot = (kernel_filename != NULL);
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272 | 1a6c0886 | j_mayer | if (linux_boot) {
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273 | 1a6c0886 | j_mayer | #ifdef DEBUG_BOARD_INIT
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274 | 1a6c0886 | j_mayer | printf("%s: load kernel\n", __func__);
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275 | 1a6c0886 | j_mayer | #endif
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276 | 1a6c0886 | j_mayer | memset(&bd, 0, sizeof(bd)); |
277 | 1a6c0886 | j_mayer | bd.bi_memstart = 0x00000000;
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278 | 1a6c0886 | j_mayer | bd.bi_memsize = ram_size; |
279 | 217fae2d | j_mayer | bd.bi_flashstart = -bios_size; |
280 | 1a6c0886 | j_mayer | bd.bi_flashsize = -bios_size; |
281 | 1a6c0886 | j_mayer | bd.bi_flashoffset = 0;
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282 | 1a6c0886 | j_mayer | bd.bi_sramstart = 0xFFF00000;
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283 | 1a6c0886 | j_mayer | bd.bi_sramsize = sram_size; |
284 | 1a6c0886 | j_mayer | bd.bi_bootflags = 0;
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285 | 1a6c0886 | j_mayer | bd.bi_intfreq = 133333333;
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286 | 1a6c0886 | j_mayer | bd.bi_busfreq = 33333333;
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287 | 1a6c0886 | j_mayer | bd.bi_baudrate = 115200;
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288 | 1a6c0886 | j_mayer | bd.bi_s_version[0] = 'Q'; |
289 | 1a6c0886 | j_mayer | bd.bi_s_version[1] = 'M'; |
290 | 1a6c0886 | j_mayer | bd.bi_s_version[2] = 'U'; |
291 | 1a6c0886 | j_mayer | bd.bi_s_version[3] = '\0'; |
292 | 1a6c0886 | j_mayer | bd.bi_r_version[0] = 'Q'; |
293 | 1a6c0886 | j_mayer | bd.bi_r_version[1] = 'E'; |
294 | 1a6c0886 | j_mayer | bd.bi_r_version[2] = 'M'; |
295 | 1a6c0886 | j_mayer | bd.bi_r_version[3] = 'U'; |
296 | 1a6c0886 | j_mayer | bd.bi_r_version[4] = '\0'; |
297 | 1a6c0886 | j_mayer | bd.bi_procfreq = 133333333;
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298 | 1a6c0886 | j_mayer | bd.bi_plb_busfreq = 33333333;
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299 | 1a6c0886 | j_mayer | bd.bi_pci_busfreq = 33333333;
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300 | 1a6c0886 | j_mayer | bd.bi_opbfreq = 33333333;
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301 | b8d3f5d1 | j_mayer | bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
|
302 | 1a6c0886 | j_mayer | env->gpr[3] = bdloc;
|
303 | 1a6c0886 | j_mayer | kernel_base = KERNEL_LOAD_ADDR; |
304 | 1a6c0886 | j_mayer | /* now we can load the kernel */
|
305 | 1a6c0886 | j_mayer | kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base); |
306 | 1a6c0886 | j_mayer | if (kernel_size < 0) { |
307 | 5fafdf24 | ths | fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
308 | 1a6c0886 | j_mayer | kernel_filename); |
309 | 1a6c0886 | j_mayer | exit(1);
|
310 | 1a6c0886 | j_mayer | } |
311 | 1a6c0886 | j_mayer | printf("Load kernel size " TARGET_FMT_ld " at " TARGET_FMT_lx |
312 | 1a6c0886 | j_mayer | " %02x %02x %02x %02x\n", kernel_size, kernel_base,
|
313 | 1a6c0886 | j_mayer | *(char *)(phys_ram_base + kernel_base),
|
314 | 1a6c0886 | j_mayer | *(char *)(phys_ram_base + kernel_base + 1), |
315 | 1a6c0886 | j_mayer | *(char *)(phys_ram_base + kernel_base + 2), |
316 | 1a6c0886 | j_mayer | *(char *)(phys_ram_base + kernel_base + 3)); |
317 | 1a6c0886 | j_mayer | /* load initrd */
|
318 | 1a6c0886 | j_mayer | if (initrd_filename) {
|
319 | 1a6c0886 | j_mayer | initrd_base = INITRD_LOAD_ADDR; |
320 | 1a6c0886 | j_mayer | initrd_size = load_image(initrd_filename, |
321 | 1a6c0886 | j_mayer | phys_ram_base + initrd_base); |
322 | 1a6c0886 | j_mayer | if (initrd_size < 0) { |
323 | 5fafdf24 | ths | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
324 | 1a6c0886 | j_mayer | initrd_filename); |
325 | 1a6c0886 | j_mayer | exit(1);
|
326 | 1a6c0886 | j_mayer | } |
327 | 1a6c0886 | j_mayer | } else {
|
328 | 1a6c0886 | j_mayer | initrd_base = 0;
|
329 | 1a6c0886 | j_mayer | initrd_size = 0;
|
330 | 1a6c0886 | j_mayer | } |
331 | 1a6c0886 | j_mayer | env->gpr[4] = initrd_base;
|
332 | 1a6c0886 | j_mayer | env->gpr[5] = initrd_size;
|
333 | 6ac0e82d | balrog | ppc_boot_device = 'm';
|
334 | 1a6c0886 | j_mayer | if (kernel_cmdline != NULL) { |
335 | 1a6c0886 | j_mayer | len = strlen(kernel_cmdline); |
336 | 1a6c0886 | j_mayer | bdloc -= ((len + 255) & ~255); |
337 | 1a6c0886 | j_mayer | memcpy(phys_ram_base + bdloc, kernel_cmdline, len + 1);
|
338 | 1a6c0886 | j_mayer | env->gpr[6] = bdloc;
|
339 | 1a6c0886 | j_mayer | env->gpr[7] = bdloc + len;
|
340 | 1a6c0886 | j_mayer | } else {
|
341 | 1a6c0886 | j_mayer | env->gpr[6] = 0; |
342 | 1a6c0886 | j_mayer | env->gpr[7] = 0; |
343 | 1a6c0886 | j_mayer | } |
344 | 1a6c0886 | j_mayer | env->nip = KERNEL_LOAD_ADDR; |
345 | 1a6c0886 | j_mayer | } else {
|
346 | 1a6c0886 | j_mayer | kernel_base = 0;
|
347 | 1a6c0886 | j_mayer | kernel_size = 0;
|
348 | 1a6c0886 | j_mayer | initrd_base = 0;
|
349 | 1a6c0886 | j_mayer | initrd_size = 0;
|
350 | 1a6c0886 | j_mayer | bdloc = 0;
|
351 | 1a6c0886 | j_mayer | } |
352 | 1a6c0886 | j_mayer | #ifdef DEBUG_BOARD_INIT
|
353 | 1a6c0886 | j_mayer | printf("%s: Done\n", __func__);
|
354 | 1a6c0886 | j_mayer | #endif
|
355 | 1a6c0886 | j_mayer | printf("bdloc %016lx %s\n",
|
356 | 1a6c0886 | j_mayer | (unsigned long)bdloc, (char *)(phys_ram_base + bdloc)); |
357 | 1a6c0886 | j_mayer | } |
358 | 1a6c0886 | j_mayer | |
359 | 1a6c0886 | j_mayer | QEMUMachine ref405ep_machine = { |
360 | 1a6c0886 | j_mayer | "ref405ep",
|
361 | 1a6c0886 | j_mayer | "ref405ep",
|
362 | 1a6c0886 | j_mayer | ref405ep_init, |
363 | 7fb4fdcf | balrog | (128 * 1024 * 1024 + 4096 + 512 * 1024 + BIOS_SIZE) | RAMSIZE_FIXED, |
364 | 1a6c0886 | j_mayer | }; |
365 | 1a6c0886 | j_mayer | |
366 | 1a6c0886 | j_mayer | /*****************************************************************************/
|
367 | 1a6c0886 | j_mayer | /* AMCC Taihu evaluation board */
|
368 | 1a6c0886 | j_mayer | /* - PowerPC 405EP processor
|
369 | 1a6c0886 | j_mayer | * - SDRAM 128 MB at 0x00000000
|
370 | 1a6c0886 | j_mayer | * - Boot flash 2 MB at 0xFFE00000
|
371 | 1a6c0886 | j_mayer | * - Application flash 32 MB at 0xFC000000
|
372 | 1a6c0886 | j_mayer | * - 2 serial ports
|
373 | 1a6c0886 | j_mayer | * - 2 ethernet PHY
|
374 | 1a6c0886 | j_mayer | * - 1 USB 1.1 device 0x50000000
|
375 | 1a6c0886 | j_mayer | * - 1 LCD display 0x50100000
|
376 | 1a6c0886 | j_mayer | * - 1 CPLD 0x50100000
|
377 | 1a6c0886 | j_mayer | * - 1 I2C EEPROM
|
378 | 1a6c0886 | j_mayer | * - 1 I2C thermal sensor
|
379 | 1a6c0886 | j_mayer | * - a set of LEDs
|
380 | 1a6c0886 | j_mayer | * - bit-bang SPI port using GPIOs
|
381 | 1a6c0886 | j_mayer | * - 1 EBC interface connector 0 0x50200000
|
382 | 1a6c0886 | j_mayer | * - 1 cardbus controller + expansion slot.
|
383 | 1a6c0886 | j_mayer | * - 1 PCI expansion slot.
|
384 | 1a6c0886 | j_mayer | */
|
385 | 1a6c0886 | j_mayer | typedef struct taihu_cpld_t taihu_cpld_t; |
386 | 1a6c0886 | j_mayer | struct taihu_cpld_t {
|
387 | 1a6c0886 | j_mayer | uint32_t base; |
388 | 1a6c0886 | j_mayer | uint8_t reg0; |
389 | 1a6c0886 | j_mayer | uint8_t reg1; |
390 | 1a6c0886 | j_mayer | }; |
391 | 1a6c0886 | j_mayer | |
392 | 1a6c0886 | j_mayer | static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr) |
393 | 1a6c0886 | j_mayer | { |
394 | 1a6c0886 | j_mayer | taihu_cpld_t *cpld; |
395 | 1a6c0886 | j_mayer | uint32_t ret; |
396 | 1a6c0886 | j_mayer | |
397 | 1a6c0886 | j_mayer | cpld = opaque; |
398 | 1a6c0886 | j_mayer | addr -= cpld->base; |
399 | 1a6c0886 | j_mayer | switch (addr) {
|
400 | 1a6c0886 | j_mayer | case 0x0: |
401 | 1a6c0886 | j_mayer | ret = cpld->reg0; |
402 | 1a6c0886 | j_mayer | break;
|
403 | 1a6c0886 | j_mayer | case 0x1: |
404 | 1a6c0886 | j_mayer | ret = cpld->reg1; |
405 | 1a6c0886 | j_mayer | break;
|
406 | 1a6c0886 | j_mayer | default:
|
407 | 1a6c0886 | j_mayer | ret = 0;
|
408 | 1a6c0886 | j_mayer | break;
|
409 | 1a6c0886 | j_mayer | } |
410 | 1a6c0886 | j_mayer | |
411 | 1a6c0886 | j_mayer | return ret;
|
412 | 1a6c0886 | j_mayer | } |
413 | 1a6c0886 | j_mayer | |
414 | 1a6c0886 | j_mayer | static void taihu_cpld_writeb (void *opaque, |
415 | 1a6c0886 | j_mayer | target_phys_addr_t addr, uint32_t value) |
416 | 1a6c0886 | j_mayer | { |
417 | 1a6c0886 | j_mayer | taihu_cpld_t *cpld; |
418 | 1a6c0886 | j_mayer | |
419 | 1a6c0886 | j_mayer | cpld = opaque; |
420 | 1a6c0886 | j_mayer | addr -= cpld->base; |
421 | 1a6c0886 | j_mayer | switch (addr) {
|
422 | 1a6c0886 | j_mayer | case 0x0: |
423 | 1a6c0886 | j_mayer | /* Read only */
|
424 | 1a6c0886 | j_mayer | break;
|
425 | 1a6c0886 | j_mayer | case 0x1: |
426 | 1a6c0886 | j_mayer | cpld->reg1 = value; |
427 | 1a6c0886 | j_mayer | break;
|
428 | 1a6c0886 | j_mayer | default:
|
429 | 1a6c0886 | j_mayer | break;
|
430 | 1a6c0886 | j_mayer | } |
431 | 1a6c0886 | j_mayer | } |
432 | 1a6c0886 | j_mayer | |
433 | 1a6c0886 | j_mayer | static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr) |
434 | 1a6c0886 | j_mayer | { |
435 | 1a6c0886 | j_mayer | uint32_t ret; |
436 | 1a6c0886 | j_mayer | |
437 | 1a6c0886 | j_mayer | ret = taihu_cpld_readb(opaque, addr) << 8;
|
438 | 1a6c0886 | j_mayer | ret |= taihu_cpld_readb(opaque, addr + 1);
|
439 | 1a6c0886 | j_mayer | |
440 | 1a6c0886 | j_mayer | return ret;
|
441 | 1a6c0886 | j_mayer | } |
442 | 1a6c0886 | j_mayer | |
443 | 1a6c0886 | j_mayer | static void taihu_cpld_writew (void *opaque, |
444 | 1a6c0886 | j_mayer | target_phys_addr_t addr, uint32_t value) |
445 | 1a6c0886 | j_mayer | { |
446 | 1a6c0886 | j_mayer | taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF); |
447 | 1a6c0886 | j_mayer | taihu_cpld_writeb(opaque, addr + 1, value & 0xFF); |
448 | 1a6c0886 | j_mayer | } |
449 | 1a6c0886 | j_mayer | |
450 | 1a6c0886 | j_mayer | static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr) |
451 | 1a6c0886 | j_mayer | { |
452 | 1a6c0886 | j_mayer | uint32_t ret; |
453 | 1a6c0886 | j_mayer | |
454 | 1a6c0886 | j_mayer | ret = taihu_cpld_readb(opaque, addr) << 24;
|
455 | 1a6c0886 | j_mayer | ret |= taihu_cpld_readb(opaque, addr + 1) << 16; |
456 | 1a6c0886 | j_mayer | ret |= taihu_cpld_readb(opaque, addr + 2) << 8; |
457 | 1a6c0886 | j_mayer | ret |= taihu_cpld_readb(opaque, addr + 3);
|
458 | 1a6c0886 | j_mayer | |
459 | 1a6c0886 | j_mayer | return ret;
|
460 | 1a6c0886 | j_mayer | } |
461 | 1a6c0886 | j_mayer | |
462 | 1a6c0886 | j_mayer | static void taihu_cpld_writel (void *opaque, |
463 | 1a6c0886 | j_mayer | target_phys_addr_t addr, uint32_t value) |
464 | 1a6c0886 | j_mayer | { |
465 | 1a6c0886 | j_mayer | taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF); |
466 | 1a6c0886 | j_mayer | taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF); |
467 | 1a6c0886 | j_mayer | taihu_cpld_writel(opaque, addr + 2, (value >> 8) & 0xFF); |
468 | 1a6c0886 | j_mayer | taihu_cpld_writeb(opaque, addr + 3, value & 0xFF); |
469 | 1a6c0886 | j_mayer | } |
470 | 1a6c0886 | j_mayer | |
471 | 1a6c0886 | j_mayer | static CPUReadMemoryFunc *taihu_cpld_read[] = {
|
472 | 1a6c0886 | j_mayer | &taihu_cpld_readb, |
473 | 1a6c0886 | j_mayer | &taihu_cpld_readw, |
474 | 1a6c0886 | j_mayer | &taihu_cpld_readl, |
475 | 1a6c0886 | j_mayer | }; |
476 | 1a6c0886 | j_mayer | |
477 | 1a6c0886 | j_mayer | static CPUWriteMemoryFunc *taihu_cpld_write[] = {
|
478 | 1a6c0886 | j_mayer | &taihu_cpld_writeb, |
479 | 1a6c0886 | j_mayer | &taihu_cpld_writew, |
480 | 1a6c0886 | j_mayer | &taihu_cpld_writel, |
481 | 1a6c0886 | j_mayer | }; |
482 | 1a6c0886 | j_mayer | |
483 | 1a6c0886 | j_mayer | static void taihu_cpld_reset (void *opaque) |
484 | 1a6c0886 | j_mayer | { |
485 | 1a6c0886 | j_mayer | taihu_cpld_t *cpld; |
486 | 1a6c0886 | j_mayer | |
487 | 1a6c0886 | j_mayer | cpld = opaque; |
488 | 1a6c0886 | j_mayer | cpld->reg0 = 0x01;
|
489 | 1a6c0886 | j_mayer | cpld->reg1 = 0x80;
|
490 | 1a6c0886 | j_mayer | } |
491 | 1a6c0886 | j_mayer | |
492 | 1a6c0886 | j_mayer | static void taihu_cpld_init (uint32_t base) |
493 | 1a6c0886 | j_mayer | { |
494 | 1a6c0886 | j_mayer | taihu_cpld_t *cpld; |
495 | 1a6c0886 | j_mayer | int cpld_memory;
|
496 | 1a6c0886 | j_mayer | |
497 | 1a6c0886 | j_mayer | cpld = qemu_mallocz(sizeof(taihu_cpld_t));
|
498 | 1a6c0886 | j_mayer | if (cpld != NULL) { |
499 | 1a6c0886 | j_mayer | cpld->base = base; |
500 | 1a6c0886 | j_mayer | cpld_memory = cpu_register_io_memory(0, taihu_cpld_read,
|
501 | 1a6c0886 | j_mayer | taihu_cpld_write, cpld); |
502 | 1a6c0886 | j_mayer | cpu_register_physical_memory(base, 0x00000100, cpld_memory);
|
503 | 1a6c0886 | j_mayer | taihu_cpld_reset(cpld); |
504 | 1a6c0886 | j_mayer | qemu_register_reset(&taihu_cpld_reset, cpld); |
505 | 1a6c0886 | j_mayer | } |
506 | 1a6c0886 | j_mayer | } |
507 | 1a6c0886 | j_mayer | |
508 | 00f82b8a | aurel32 | static void taihu_405ep_init(ram_addr_t ram_size, int vga_ram_size, |
509 | 6ac0e82d | balrog | const char *boot_device, DisplayState *ds, |
510 | 5fafdf24 | ths | const char *kernel_filename, |
511 | 1a6c0886 | j_mayer | const char *kernel_cmdline, |
512 | 1a6c0886 | j_mayer | const char *initrd_filename, |
513 | 1a6c0886 | j_mayer | const char *cpu_model) |
514 | 1a6c0886 | j_mayer | { |
515 | 1a6c0886 | j_mayer | char buf[1024]; |
516 | 1a6c0886 | j_mayer | CPUPPCState *env; |
517 | 1a6c0886 | j_mayer | qemu_irq *pic; |
518 | 1a6c0886 | j_mayer | ram_addr_t bios_offset; |
519 | 71db710f | blueswir1 | target_phys_addr_t ram_bases[2], ram_sizes[2]; |
520 | 1a6c0886 | j_mayer | target_ulong bios_size; |
521 | 1a6c0886 | j_mayer | target_ulong kernel_base, kernel_size, initrd_base, initrd_size; |
522 | 1a6c0886 | j_mayer | int linux_boot;
|
523 | 1a6c0886 | j_mayer | int fl_idx, fl_sectors;
|
524 | 6ac0e82d | balrog | int ppc_boot_device = boot_device[0]; |
525 | e4bcb14c | ths | int index;
|
526 | 3b46e624 | ths | |
527 | 1a6c0886 | j_mayer | /* RAM is soldered to the board so the size cannot be changed */
|
528 | 1a6c0886 | j_mayer | ram_bases[0] = 0x00000000; |
529 | 1a6c0886 | j_mayer | ram_sizes[0] = 0x04000000; |
530 | 1a6c0886 | j_mayer | ram_bases[1] = 0x04000000; |
531 | 1a6c0886 | j_mayer | ram_sizes[1] = 0x04000000; |
532 | 1a6c0886 | j_mayer | #ifdef DEBUG_BOARD_INIT
|
533 | 1a6c0886 | j_mayer | printf("%s: register cpu\n", __func__);
|
534 | 1a6c0886 | j_mayer | #endif
|
535 | 1a6c0886 | j_mayer | env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic, &bios_offset,
|
536 | 1a6c0886 | j_mayer | kernel_filename == NULL ? 0 : 1); |
537 | 1a6c0886 | j_mayer | /* allocate and load BIOS */
|
538 | 1a6c0886 | j_mayer | #ifdef DEBUG_BOARD_INIT
|
539 | 1a6c0886 | j_mayer | printf("%s: register BIOS\n", __func__);
|
540 | 1a6c0886 | j_mayer | #endif
|
541 | 1a6c0886 | j_mayer | fl_idx = 0;
|
542 | 1a6c0886 | j_mayer | #if defined(USE_FLASH_BIOS)
|
543 | e4bcb14c | ths | index = drive_get_index(IF_PFLASH, 0, fl_idx);
|
544 | e4bcb14c | ths | if (index != -1) { |
545 | e4bcb14c | ths | bios_size = bdrv_getlength(drives_table[index].bdrv); |
546 | 1a6c0886 | j_mayer | /* XXX: should check that size is 2MB */
|
547 | 1a6c0886 | j_mayer | // bios_size = 2 * 1024 * 1024;
|
548 | 1a6c0886 | j_mayer | fl_sectors = (bios_size + 65535) >> 16; |
549 | 1a6c0886 | j_mayer | #ifdef DEBUG_BOARD_INIT
|
550 | 1a6c0886 | j_mayer | printf("Register parallel flash %d size " ADDRX " at offset %08lx " |
551 | 1a6c0886 | j_mayer | " addr " ADDRX " '%s' %d\n", |
552 | 1a6c0886 | j_mayer | fl_idx, bios_size, bios_offset, -bios_size, |
553 | e4bcb14c | ths | bdrv_get_device_name(drives_table[index].bdrv), fl_sectors); |
554 | 1a6c0886 | j_mayer | #endif
|
555 | 88eeee0a | balrog | pflash_cfi02_register((uint32_t)(-bios_size), bios_offset, |
556 | 4fbd24ba | balrog | drives_table[index].bdrv, 65536, fl_sectors, 1, |
557 | 4fbd24ba | balrog | 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA); |
558 | 1a6c0886 | j_mayer | fl_idx++; |
559 | 1a6c0886 | j_mayer | } else
|
560 | 1a6c0886 | j_mayer | #endif
|
561 | 1a6c0886 | j_mayer | { |
562 | 1a6c0886 | j_mayer | #ifdef DEBUG_BOARD_INIT
|
563 | 1a6c0886 | j_mayer | printf("Load BIOS from file\n");
|
564 | 1a6c0886 | j_mayer | #endif
|
565 | 1192dad8 | j_mayer | if (bios_name == NULL) |
566 | 1192dad8 | j_mayer | bios_name = BIOS_FILENAME; |
567 | 1192dad8 | j_mayer | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
568 | 1a6c0886 | j_mayer | bios_size = load_image(buf, phys_ram_base + bios_offset); |
569 | 1a6c0886 | j_mayer | if (bios_size < 0 || bios_size > BIOS_SIZE) { |
570 | 1a6c0886 | j_mayer | fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", buf);
|
571 | 1a6c0886 | j_mayer | exit(1);
|
572 | 1a6c0886 | j_mayer | } |
573 | 1a6c0886 | j_mayer | bios_size = (bios_size + 0xfff) & ~0xfff; |
574 | 5fafdf24 | ths | cpu_register_physical_memory((uint32_t)(-bios_size), |
575 | 1a6c0886 | j_mayer | bios_size, bios_offset | IO_MEM_ROM); |
576 | 1a6c0886 | j_mayer | } |
577 | 1a6c0886 | j_mayer | bios_offset += bios_size; |
578 | 1a6c0886 | j_mayer | /* Register Linux flash */
|
579 | e4bcb14c | ths | index = drive_get_index(IF_PFLASH, 0, fl_idx);
|
580 | e4bcb14c | ths | if (index != -1) { |
581 | e4bcb14c | ths | bios_size = bdrv_getlength(drives_table[index].bdrv); |
582 | 1a6c0886 | j_mayer | /* XXX: should check that size is 32MB */
|
583 | 1a6c0886 | j_mayer | bios_size = 32 * 1024 * 1024; |
584 | 1a6c0886 | j_mayer | fl_sectors = (bios_size + 65535) >> 16; |
585 | 1a6c0886 | j_mayer | #ifdef DEBUG_BOARD_INIT
|
586 | 1a6c0886 | j_mayer | printf("Register parallel flash %d size " ADDRX " at offset %08lx " |
587 | 1a6c0886 | j_mayer | " addr " ADDRX " '%s'\n", |
588 | 1a6c0886 | j_mayer | fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000,
|
589 | e4bcb14c | ths | bdrv_get_device_name(drives_table[index].bdrv)); |
590 | 1a6c0886 | j_mayer | #endif
|
591 | 88eeee0a | balrog | pflash_cfi02_register(0xfc000000, bios_offset,
|
592 | 4fbd24ba | balrog | drives_table[index].bdrv, 65536, fl_sectors, 1, |
593 | 4fbd24ba | balrog | 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA); |
594 | 1a6c0886 | j_mayer | fl_idx++; |
595 | 1a6c0886 | j_mayer | } |
596 | 1a6c0886 | j_mayer | /* Register CLPD & LCD display */
|
597 | 1a6c0886 | j_mayer | #ifdef DEBUG_BOARD_INIT
|
598 | 1a6c0886 | j_mayer | printf("%s: register CPLD\n", __func__);
|
599 | 1a6c0886 | j_mayer | #endif
|
600 | 1a6c0886 | j_mayer | taihu_cpld_init(0x50100000);
|
601 | 1a6c0886 | j_mayer | /* Load kernel */
|
602 | 1a6c0886 | j_mayer | linux_boot = (kernel_filename != NULL);
|
603 | 1a6c0886 | j_mayer | if (linux_boot) {
|
604 | 1a6c0886 | j_mayer | #ifdef DEBUG_BOARD_INIT
|
605 | 1a6c0886 | j_mayer | printf("%s: load kernel\n", __func__);
|
606 | 1a6c0886 | j_mayer | #endif
|
607 | 1a6c0886 | j_mayer | kernel_base = KERNEL_LOAD_ADDR; |
608 | 1a6c0886 | j_mayer | /* now we can load the kernel */
|
609 | 1a6c0886 | j_mayer | kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base); |
610 | 1a6c0886 | j_mayer | if (kernel_size < 0) { |
611 | 5fafdf24 | ths | fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
612 | 1a6c0886 | j_mayer | kernel_filename); |
613 | 1a6c0886 | j_mayer | exit(1);
|
614 | 1a6c0886 | j_mayer | } |
615 | 1a6c0886 | j_mayer | /* load initrd */
|
616 | 1a6c0886 | j_mayer | if (initrd_filename) {
|
617 | 1a6c0886 | j_mayer | initrd_base = INITRD_LOAD_ADDR; |
618 | 1a6c0886 | j_mayer | initrd_size = load_image(initrd_filename, |
619 | 1a6c0886 | j_mayer | phys_ram_base + initrd_base); |
620 | 1a6c0886 | j_mayer | if (initrd_size < 0) { |
621 | 1a6c0886 | j_mayer | fprintf(stderr, |
622 | 5fafdf24 | ths | "qemu: could not load initial ram disk '%s'\n",
|
623 | 1a6c0886 | j_mayer | initrd_filename); |
624 | 1a6c0886 | j_mayer | exit(1);
|
625 | 1a6c0886 | j_mayer | } |
626 | 1a6c0886 | j_mayer | } else {
|
627 | 1a6c0886 | j_mayer | initrd_base = 0;
|
628 | 1a6c0886 | j_mayer | initrd_size = 0;
|
629 | 1a6c0886 | j_mayer | } |
630 | 6ac0e82d | balrog | ppc_boot_device = 'm';
|
631 | 1a6c0886 | j_mayer | } else {
|
632 | 1a6c0886 | j_mayer | kernel_base = 0;
|
633 | 1a6c0886 | j_mayer | kernel_size = 0;
|
634 | 1a6c0886 | j_mayer | initrd_base = 0;
|
635 | 1a6c0886 | j_mayer | initrd_size = 0;
|
636 | 1a6c0886 | j_mayer | } |
637 | 1a6c0886 | j_mayer | #ifdef DEBUG_BOARD_INIT
|
638 | 1a6c0886 | j_mayer | printf("%s: Done\n", __func__);
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639 | 1a6c0886 | j_mayer | #endif
|
640 | 1a6c0886 | j_mayer | } |
641 | 1a6c0886 | j_mayer | |
642 | 1a6c0886 | j_mayer | QEMUMachine taihu_machine = { |
643 | 1a6c0886 | j_mayer | "taihu",
|
644 | 1a6c0886 | j_mayer | "taihu",
|
645 | 1a6c0886 | j_mayer | taihu_405ep_init, |
646 | 7fb4fdcf | balrog | (128 * 1024 * 1024 + 4096 + BIOS_SIZE + 32 * 1024 * 1024) | RAMSIZE_FIXED, |
647 | 1a6c0886 | j_mayer | }; |