root / hw / ppc405_boards.c @ c75a823c
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/*
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* QEMU PowerPC 405 evaluation boards emulation
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*
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "ppc.h" |
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#include "ppc405.h" |
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#include "nvram.h" |
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#include "flash.h" |
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#include "sysemu.h" |
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#include "block.h" |
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#include "boards.h" |
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extern int loglevel; |
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extern FILE *logfile;
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#define BIOS_FILENAME "ppc405_rom.bin" |
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#undef BIOS_SIZE
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#define BIOS_SIZE (2048 * 1024) |
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#define KERNEL_LOAD_ADDR 0x00000000 |
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#define INITRD_LOAD_ADDR 0x01800000 |
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#define USE_FLASH_BIOS
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#define DEBUG_BOARD_INIT
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/*****************************************************************************/
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/* PPC405EP reference board (IBM) */
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/* Standalone board with:
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* - PowerPC 405EP CPU
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* - SDRAM (0x00000000)
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* - Flash (0xFFF80000)
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* - SRAM (0xFFF00000)
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* - NVRAM (0xF0000000)
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* - FPGA (0xF0300000)
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*/
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typedef struct ref405ep_fpga_t ref405ep_fpga_t; |
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struct ref405ep_fpga_t {
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uint32_t base; |
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uint8_t reg0; |
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uint8_t reg1; |
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}; |
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static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr) |
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{ |
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ref405ep_fpga_t *fpga; |
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uint32_t ret; |
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fpga = opaque; |
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addr -= fpga->base; |
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switch (addr) {
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case 0x0: |
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ret = fpga->reg0; |
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break;
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case 0x1: |
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ret = fpga->reg1; |
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break;
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default:
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ret = 0;
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break;
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} |
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return ret;
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} |
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static void ref405ep_fpga_writeb (void *opaque, |
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target_phys_addr_t addr, uint32_t value) |
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{ |
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ref405ep_fpga_t *fpga; |
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fpga = opaque; |
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addr -= fpga->base; |
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switch (addr) {
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case 0x0: |
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/* Read only */
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break;
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case 0x1: |
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fpga->reg1 = value; |
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break;
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default:
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break;
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} |
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} |
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static uint32_t ref405ep_fpga_readw (void *opaque, target_phys_addr_t addr) |
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{ |
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uint32_t ret; |
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ret = ref405ep_fpga_readb(opaque, addr) << 8;
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ret |= ref405ep_fpga_readb(opaque, addr + 1);
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return ret;
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} |
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static void ref405ep_fpga_writew (void *opaque, |
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target_phys_addr_t addr, uint32_t value) |
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{ |
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ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF); |
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ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF); |
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} |
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static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr) |
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{ |
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uint32_t ret; |
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ret = ref405ep_fpga_readb(opaque, addr) << 24;
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ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16; |
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ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8; |
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ret |= ref405ep_fpga_readb(opaque, addr + 3);
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return ret;
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} |
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static void ref405ep_fpga_writel (void *opaque, |
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target_phys_addr_t addr, uint32_t value) |
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{ |
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ref405ep_fpga_writel(opaque, addr, (value >> 24) & 0xFF); |
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ref405ep_fpga_writel(opaque, addr + 1, (value >> 16) & 0xFF); |
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ref405ep_fpga_writel(opaque, addr + 2, (value >> 8) & 0xFF); |
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ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF); |
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} |
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static CPUReadMemoryFunc *ref405ep_fpga_read[] = {
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&ref405ep_fpga_readb, |
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&ref405ep_fpga_readw, |
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&ref405ep_fpga_readl, |
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}; |
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static CPUWriteMemoryFunc *ref405ep_fpga_write[] = {
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&ref405ep_fpga_writeb, |
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&ref405ep_fpga_writew, |
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&ref405ep_fpga_writel, |
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}; |
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static void ref405ep_fpga_reset (void *opaque) |
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{ |
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ref405ep_fpga_t *fpga; |
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fpga = opaque; |
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fpga->reg0 = 0x00;
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fpga->reg1 = 0x0F;
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} |
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static void ref405ep_fpga_init (uint32_t base) |
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{ |
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ref405ep_fpga_t *fpga; |
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int fpga_memory;
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fpga = qemu_mallocz(sizeof(ref405ep_fpga_t));
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if (fpga != NULL) { |
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fpga->base = base; |
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fpga_memory = cpu_register_io_memory(0, ref405ep_fpga_read,
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ref405ep_fpga_write, fpga); |
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cpu_register_physical_memory(base, 0x00000100, fpga_memory);
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ref405ep_fpga_reset(fpga); |
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qemu_register_reset(&ref405ep_fpga_reset, fpga); |
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} |
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} |
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static void ref405ep_init (ram_addr_t ram_size, int vga_ram_size, |
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const char *boot_device, DisplayState *ds, |
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const char *kernel_filename, |
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const char *kernel_cmdline, |
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const char *initrd_filename, |
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const char *cpu_model) |
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{ |
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char buf[1024]; |
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ppc4xx_bd_info_t bd; |
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CPUPPCState *env; |
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qemu_irq *pic; |
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ram_addr_t sram_offset, bios_offset, bdloc; |
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target_phys_addr_t ram_bases[2], ram_sizes[2]; |
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target_ulong sram_size, bios_size; |
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//int phy_addr = 0;
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//static int phy_addr = 1;
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target_ulong kernel_base, kernel_size, initrd_base, initrd_size; |
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int linux_boot;
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int fl_idx, fl_sectors, len;
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int ppc_boot_device = boot_device[0]; |
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int index;
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/* XXX: fix this */
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ram_bases[0] = 0x00000000; |
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ram_sizes[0] = 0x08000000; |
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ram_bases[1] = 0x00000000; |
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ram_sizes[1] = 0x00000000; |
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ram_size = 128 * 1024 * 1024; |
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#ifdef DEBUG_BOARD_INIT
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printf("%s: register cpu\n", __func__);
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#endif
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env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic, &sram_offset,
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kernel_filename == NULL ? 0 : 1); |
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/* allocate SRAM */
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#ifdef DEBUG_BOARD_INIT
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printf("%s: register SRAM at offset %08lx\n", __func__, sram_offset);
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#endif
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sram_size = 512 * 1024; |
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cpu_register_physical_memory(0xFFF00000, sram_size,
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sram_offset | IO_MEM_RAM); |
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/* allocate and load BIOS */
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#ifdef DEBUG_BOARD_INIT
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printf("%s: register BIOS\n", __func__);
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#endif
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bios_offset = sram_offset + sram_size; |
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fl_idx = 0;
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#ifdef USE_FLASH_BIOS
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index = drive_get_index(IF_PFLASH, 0, fl_idx);
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if (index != -1) { |
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bios_size = bdrv_getlength(drives_table[index].bdrv); |
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fl_sectors = (bios_size + 65535) >> 16; |
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#ifdef DEBUG_BOARD_INIT
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printf("Register parallel flash %d size " ADDRX " at offset %08lx " |
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" addr " ADDRX " '%s' %d\n", |
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fl_idx, bios_size, bios_offset, -bios_size, |
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bdrv_get_device_name(drives_table[index].bdrv), fl_sectors); |
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#endif
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pflash_cfi02_register((uint32_t)(-bios_size), bios_offset, |
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drives_table[index].bdrv, 65536, fl_sectors, 1, |
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2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA); |
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fl_idx++; |
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} else
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#endif
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{ |
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#ifdef DEBUG_BOARD_INIT
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printf("Load BIOS from file\n");
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#endif
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if (bios_name == NULL) |
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bios_name = BIOS_FILENAME; |
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
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bios_size = load_image(buf, phys_ram_base + bios_offset); |
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if (bios_size < 0 || bios_size > BIOS_SIZE) { |
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fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", buf);
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exit(1);
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} |
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bios_size = (bios_size + 0xfff) & ~0xfff; |
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cpu_register_physical_memory((uint32_t)(-bios_size), |
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bios_size, bios_offset | IO_MEM_ROM); |
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} |
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bios_offset += bios_size; |
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/* Register FPGA */
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#ifdef DEBUG_BOARD_INIT
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printf("%s: register FPGA\n", __func__);
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#endif
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ref405ep_fpga_init(0xF0300000);
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/* Register NVRAM */
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#ifdef DEBUG_BOARD_INIT
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printf("%s: register NVRAM\n", __func__);
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#endif
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m48t59_init(NULL, 0xF0000000, 0, 8192, 8); |
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/* Load kernel */
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linux_boot = (kernel_filename != NULL);
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if (linux_boot) {
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#ifdef DEBUG_BOARD_INIT
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printf("%s: load kernel\n", __func__);
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#endif
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memset(&bd, 0, sizeof(bd)); |
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bd.bi_memstart = 0x00000000;
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bd.bi_memsize = ram_size; |
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bd.bi_flashstart = -bios_size; |
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bd.bi_flashsize = -bios_size; |
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bd.bi_flashoffset = 0;
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bd.bi_sramstart = 0xFFF00000;
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bd.bi_sramsize = sram_size; |
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bd.bi_bootflags = 0;
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bd.bi_intfreq = 133333333;
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bd.bi_busfreq = 33333333;
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bd.bi_baudrate = 115200;
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bd.bi_s_version[0] = 'Q'; |
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bd.bi_s_version[1] = 'M'; |
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bd.bi_s_version[2] = 'U'; |
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bd.bi_s_version[3] = '\0'; |
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bd.bi_r_version[0] = 'Q'; |
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bd.bi_r_version[1] = 'E'; |
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bd.bi_r_version[2] = 'M'; |
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bd.bi_r_version[3] = 'U'; |
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bd.bi_r_version[4] = '\0'; |
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bd.bi_procfreq = 133333333;
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bd.bi_plb_busfreq = 33333333;
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bd.bi_pci_busfreq = 33333333;
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bd.bi_opbfreq = 33333333;
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bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
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env->gpr[3] = bdloc;
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kernel_base = KERNEL_LOAD_ADDR; |
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/* now we can load the kernel */
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kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base); |
306 |
if (kernel_size < 0) { |
307 |
fprintf(stderr, "qemu: could not load kernel '%s'\n",
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kernel_filename); |
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exit(1);
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} |
311 |
printf("Load kernel size " TARGET_FMT_ld " at " TARGET_FMT_lx |
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" %02x %02x %02x %02x\n", kernel_size, kernel_base,
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*(char *)(phys_ram_base + kernel_base),
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*(char *)(phys_ram_base + kernel_base + 1), |
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*(char *)(phys_ram_base + kernel_base + 2), |
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*(char *)(phys_ram_base + kernel_base + 3)); |
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/* load initrd */
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if (initrd_filename) {
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initrd_base = INITRD_LOAD_ADDR; |
320 |
initrd_size = load_image(initrd_filename, |
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phys_ram_base + initrd_base); |
322 |
if (initrd_size < 0) { |
323 |
fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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initrd_filename); |
325 |
exit(1);
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} |
327 |
} else {
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initrd_base = 0;
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initrd_size = 0;
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} |
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env->gpr[4] = initrd_base;
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env->gpr[5] = initrd_size;
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ppc_boot_device = 'm';
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if (kernel_cmdline != NULL) { |
335 |
len = strlen(kernel_cmdline); |
336 |
bdloc -= ((len + 255) & ~255); |
337 |
memcpy(phys_ram_base + bdloc, kernel_cmdline, len + 1);
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338 |
env->gpr[6] = bdloc;
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env->gpr[7] = bdloc + len;
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340 |
} else {
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341 |
env->gpr[6] = 0; |
342 |
env->gpr[7] = 0; |
343 |
} |
344 |
env->nip = KERNEL_LOAD_ADDR; |
345 |
} else {
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kernel_base = 0;
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kernel_size = 0;
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initrd_base = 0;
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349 |
initrd_size = 0;
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350 |
bdloc = 0;
|
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} |
352 |
#ifdef DEBUG_BOARD_INIT
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353 |
printf("%s: Done\n", __func__);
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#endif
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printf("bdloc %016lx %s\n",
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(unsigned long)bdloc, (char *)(phys_ram_base + bdloc)); |
357 |
} |
358 |
|
359 |
QEMUMachine ref405ep_machine = { |
360 |
"ref405ep",
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"ref405ep",
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ref405ep_init, |
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(128 * 1024 * 1024 + 4096 + 512 * 1024 + BIOS_SIZE) | RAMSIZE_FIXED, |
364 |
}; |
365 |
|
366 |
/*****************************************************************************/
|
367 |
/* AMCC Taihu evaluation board */
|
368 |
/* - PowerPC 405EP processor
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369 |
* - SDRAM 128 MB at 0x00000000
|
370 |
* - Boot flash 2 MB at 0xFFE00000
|
371 |
* - Application flash 32 MB at 0xFC000000
|
372 |
* - 2 serial ports
|
373 |
* - 2 ethernet PHY
|
374 |
* - 1 USB 1.1 device 0x50000000
|
375 |
* - 1 LCD display 0x50100000
|
376 |
* - 1 CPLD 0x50100000
|
377 |
* - 1 I2C EEPROM
|
378 |
* - 1 I2C thermal sensor
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379 |
* - a set of LEDs
|
380 |
* - bit-bang SPI port using GPIOs
|
381 |
* - 1 EBC interface connector 0 0x50200000
|
382 |
* - 1 cardbus controller + expansion slot.
|
383 |
* - 1 PCI expansion slot.
|
384 |
*/
|
385 |
typedef struct taihu_cpld_t taihu_cpld_t; |
386 |
struct taihu_cpld_t {
|
387 |
uint32_t base; |
388 |
uint8_t reg0; |
389 |
uint8_t reg1; |
390 |
}; |
391 |
|
392 |
static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr) |
393 |
{ |
394 |
taihu_cpld_t *cpld; |
395 |
uint32_t ret; |
396 |
|
397 |
cpld = opaque; |
398 |
addr -= cpld->base; |
399 |
switch (addr) {
|
400 |
case 0x0: |
401 |
ret = cpld->reg0; |
402 |
break;
|
403 |
case 0x1: |
404 |
ret = cpld->reg1; |
405 |
break;
|
406 |
default:
|
407 |
ret = 0;
|
408 |
break;
|
409 |
} |
410 |
|
411 |
return ret;
|
412 |
} |
413 |
|
414 |
static void taihu_cpld_writeb (void *opaque, |
415 |
target_phys_addr_t addr, uint32_t value) |
416 |
{ |
417 |
taihu_cpld_t *cpld; |
418 |
|
419 |
cpld = opaque; |
420 |
addr -= cpld->base; |
421 |
switch (addr) {
|
422 |
case 0x0: |
423 |
/* Read only */
|
424 |
break;
|
425 |
case 0x1: |
426 |
cpld->reg1 = value; |
427 |
break;
|
428 |
default:
|
429 |
break;
|
430 |
} |
431 |
} |
432 |
|
433 |
static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr) |
434 |
{ |
435 |
uint32_t ret; |
436 |
|
437 |
ret = taihu_cpld_readb(opaque, addr) << 8;
|
438 |
ret |= taihu_cpld_readb(opaque, addr + 1);
|
439 |
|
440 |
return ret;
|
441 |
} |
442 |
|
443 |
static void taihu_cpld_writew (void *opaque, |
444 |
target_phys_addr_t addr, uint32_t value) |
445 |
{ |
446 |
taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF); |
447 |
taihu_cpld_writeb(opaque, addr + 1, value & 0xFF); |
448 |
} |
449 |
|
450 |
static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr) |
451 |
{ |
452 |
uint32_t ret; |
453 |
|
454 |
ret = taihu_cpld_readb(opaque, addr) << 24;
|
455 |
ret |= taihu_cpld_readb(opaque, addr + 1) << 16; |
456 |
ret |= taihu_cpld_readb(opaque, addr + 2) << 8; |
457 |
ret |= taihu_cpld_readb(opaque, addr + 3);
|
458 |
|
459 |
return ret;
|
460 |
} |
461 |
|
462 |
static void taihu_cpld_writel (void *opaque, |
463 |
target_phys_addr_t addr, uint32_t value) |
464 |
{ |
465 |
taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF); |
466 |
taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF); |
467 |
taihu_cpld_writel(opaque, addr + 2, (value >> 8) & 0xFF); |
468 |
taihu_cpld_writeb(opaque, addr + 3, value & 0xFF); |
469 |
} |
470 |
|
471 |
static CPUReadMemoryFunc *taihu_cpld_read[] = {
|
472 |
&taihu_cpld_readb, |
473 |
&taihu_cpld_readw, |
474 |
&taihu_cpld_readl, |
475 |
}; |
476 |
|
477 |
static CPUWriteMemoryFunc *taihu_cpld_write[] = {
|
478 |
&taihu_cpld_writeb, |
479 |
&taihu_cpld_writew, |
480 |
&taihu_cpld_writel, |
481 |
}; |
482 |
|
483 |
static void taihu_cpld_reset (void *opaque) |
484 |
{ |
485 |
taihu_cpld_t *cpld; |
486 |
|
487 |
cpld = opaque; |
488 |
cpld->reg0 = 0x01;
|
489 |
cpld->reg1 = 0x80;
|
490 |
} |
491 |
|
492 |
static void taihu_cpld_init (uint32_t base) |
493 |
{ |
494 |
taihu_cpld_t *cpld; |
495 |
int cpld_memory;
|
496 |
|
497 |
cpld = qemu_mallocz(sizeof(taihu_cpld_t));
|
498 |
if (cpld != NULL) { |
499 |
cpld->base = base; |
500 |
cpld_memory = cpu_register_io_memory(0, taihu_cpld_read,
|
501 |
taihu_cpld_write, cpld); |
502 |
cpu_register_physical_memory(base, 0x00000100, cpld_memory);
|
503 |
taihu_cpld_reset(cpld); |
504 |
qemu_register_reset(&taihu_cpld_reset, cpld); |
505 |
} |
506 |
} |
507 |
|
508 |
static void taihu_405ep_init(ram_addr_t ram_size, int vga_ram_size, |
509 |
const char *boot_device, DisplayState *ds, |
510 |
const char *kernel_filename, |
511 |
const char *kernel_cmdline, |
512 |
const char *initrd_filename, |
513 |
const char *cpu_model) |
514 |
{ |
515 |
char buf[1024]; |
516 |
CPUPPCState *env; |
517 |
qemu_irq *pic; |
518 |
ram_addr_t bios_offset; |
519 |
target_phys_addr_t ram_bases[2], ram_sizes[2]; |
520 |
target_ulong bios_size; |
521 |
target_ulong kernel_base, kernel_size, initrd_base, initrd_size; |
522 |
int linux_boot;
|
523 |
int fl_idx, fl_sectors;
|
524 |
int ppc_boot_device = boot_device[0]; |
525 |
int index;
|
526 |
|
527 |
/* RAM is soldered to the board so the size cannot be changed */
|
528 |
ram_bases[0] = 0x00000000; |
529 |
ram_sizes[0] = 0x04000000; |
530 |
ram_bases[1] = 0x04000000; |
531 |
ram_sizes[1] = 0x04000000; |
532 |
#ifdef DEBUG_BOARD_INIT
|
533 |
printf("%s: register cpu\n", __func__);
|
534 |
#endif
|
535 |
env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic, &bios_offset,
|
536 |
kernel_filename == NULL ? 0 : 1); |
537 |
/* allocate and load BIOS */
|
538 |
#ifdef DEBUG_BOARD_INIT
|
539 |
printf("%s: register BIOS\n", __func__);
|
540 |
#endif
|
541 |
fl_idx = 0;
|
542 |
#if defined(USE_FLASH_BIOS)
|
543 |
index = drive_get_index(IF_PFLASH, 0, fl_idx);
|
544 |
if (index != -1) { |
545 |
bios_size = bdrv_getlength(drives_table[index].bdrv); |
546 |
/* XXX: should check that size is 2MB */
|
547 |
// bios_size = 2 * 1024 * 1024;
|
548 |
fl_sectors = (bios_size + 65535) >> 16; |
549 |
#ifdef DEBUG_BOARD_INIT
|
550 |
printf("Register parallel flash %d size " ADDRX " at offset %08lx " |
551 |
" addr " ADDRX " '%s' %d\n", |
552 |
fl_idx, bios_size, bios_offset, -bios_size, |
553 |
bdrv_get_device_name(drives_table[index].bdrv), fl_sectors); |
554 |
#endif
|
555 |
pflash_cfi02_register((uint32_t)(-bios_size), bios_offset, |
556 |
drives_table[index].bdrv, 65536, fl_sectors, 1, |
557 |
4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA); |
558 |
fl_idx++; |
559 |
} else
|
560 |
#endif
|
561 |
{ |
562 |
#ifdef DEBUG_BOARD_INIT
|
563 |
printf("Load BIOS from file\n");
|
564 |
#endif
|
565 |
if (bios_name == NULL) |
566 |
bios_name = BIOS_FILENAME; |
567 |
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
568 |
bios_size = load_image(buf, phys_ram_base + bios_offset); |
569 |
if (bios_size < 0 || bios_size > BIOS_SIZE) { |
570 |
fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", buf);
|
571 |
exit(1);
|
572 |
} |
573 |
bios_size = (bios_size + 0xfff) & ~0xfff; |
574 |
cpu_register_physical_memory((uint32_t)(-bios_size), |
575 |
bios_size, bios_offset | IO_MEM_ROM); |
576 |
} |
577 |
bios_offset += bios_size; |
578 |
/* Register Linux flash */
|
579 |
index = drive_get_index(IF_PFLASH, 0, fl_idx);
|
580 |
if (index != -1) { |
581 |
bios_size = bdrv_getlength(drives_table[index].bdrv); |
582 |
/* XXX: should check that size is 32MB */
|
583 |
bios_size = 32 * 1024 * 1024; |
584 |
fl_sectors = (bios_size + 65535) >> 16; |
585 |
#ifdef DEBUG_BOARD_INIT
|
586 |
printf("Register parallel flash %d size " ADDRX " at offset %08lx " |
587 |
" addr " ADDRX " '%s'\n", |
588 |
fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000,
|
589 |
bdrv_get_device_name(drives_table[index].bdrv)); |
590 |
#endif
|
591 |
pflash_cfi02_register(0xfc000000, bios_offset,
|
592 |
drives_table[index].bdrv, 65536, fl_sectors, 1, |
593 |
4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA); |
594 |
fl_idx++; |
595 |
} |
596 |
/* Register CLPD & LCD display */
|
597 |
#ifdef DEBUG_BOARD_INIT
|
598 |
printf("%s: register CPLD\n", __func__);
|
599 |
#endif
|
600 |
taihu_cpld_init(0x50100000);
|
601 |
/* Load kernel */
|
602 |
linux_boot = (kernel_filename != NULL);
|
603 |
if (linux_boot) {
|
604 |
#ifdef DEBUG_BOARD_INIT
|
605 |
printf("%s: load kernel\n", __func__);
|
606 |
#endif
|
607 |
kernel_base = KERNEL_LOAD_ADDR; |
608 |
/* now we can load the kernel */
|
609 |
kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base); |
610 |
if (kernel_size < 0) { |
611 |
fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
612 |
kernel_filename); |
613 |
exit(1);
|
614 |
} |
615 |
/* load initrd */
|
616 |
if (initrd_filename) {
|
617 |
initrd_base = INITRD_LOAD_ADDR; |
618 |
initrd_size = load_image(initrd_filename, |
619 |
phys_ram_base + initrd_base); |
620 |
if (initrd_size < 0) { |
621 |
fprintf(stderr, |
622 |
"qemu: could not load initial ram disk '%s'\n",
|
623 |
initrd_filename); |
624 |
exit(1);
|
625 |
} |
626 |
} else {
|
627 |
initrd_base = 0;
|
628 |
initrd_size = 0;
|
629 |
} |
630 |
ppc_boot_device = 'm';
|
631 |
} else {
|
632 |
kernel_base = 0;
|
633 |
kernel_size = 0;
|
634 |
initrd_base = 0;
|
635 |
initrd_size = 0;
|
636 |
} |
637 |
#ifdef DEBUG_BOARD_INIT
|
638 |
printf("%s: Done\n", __func__);
|
639 |
#endif
|
640 |
} |
641 |
|
642 |
QEMUMachine taihu_machine = { |
643 |
"taihu",
|
644 |
"taihu",
|
645 |
taihu_405ep_init, |
646 |
(128 * 1024 * 1024 + 4096 + BIOS_SIZE + 32 * 1024 * 1024) | RAMSIZE_FIXED, |
647 |
}; |