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1 | 69b91039 | bellard | /*
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2 | 69b91039 | bellard | * QEMU PCI bus manager
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3 | 69b91039 | bellard | *
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4 | 69b91039 | bellard | * Copyright (c) 2004 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 69b91039 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 69b91039 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 69b91039 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 69b91039 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 69b91039 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 69b91039 | bellard | * furnished to do so, subject to the following conditions:
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12 | 69b91039 | bellard | *
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13 | 69b91039 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 69b91039 | bellard | * all copies or substantial portions of the Software.
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15 | 69b91039 | bellard | *
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16 | 69b91039 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 69b91039 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 69b91039 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 69b91039 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 69b91039 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 69b91039 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 69b91039 | bellard | * THE SOFTWARE.
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23 | 69b91039 | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "pci.h" |
26 | 87ecb68b | pbrook | #include "console.h" |
27 | 87ecb68b | pbrook | #include "net.h" |
28 | fbe78f4f | aliguori | #include "virtio-net.h" |
29 | 69b91039 | bellard | |
30 | 69b91039 | bellard | //#define DEBUG_PCI
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31 | 69b91039 | bellard | |
32 | 30468f78 | bellard | struct PCIBus {
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33 | 30468f78 | bellard | int bus_num;
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34 | 30468f78 | bellard | int devfn_min;
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35 | 502a5395 | pbrook | pci_set_irq_fn set_irq; |
36 | d2b59317 | pbrook | pci_map_irq_fn map_irq; |
37 | 30468f78 | bellard | uint32_t config_reg; /* XXX: suppress */
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38 | 384d8876 | bellard | /* low level pic */
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39 | 384d8876 | bellard | SetIRQFunc *low_set_irq; |
40 | d537cf6c | pbrook | qemu_irq *irq_opaque; |
41 | 30468f78 | bellard | PCIDevice *devices[256];
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42 | 80b3ada7 | pbrook | PCIDevice *parent_dev; |
43 | 80b3ada7 | pbrook | PCIBus *next; |
44 | d2b59317 | pbrook | /* The bus IRQ state is the logical OR of the connected devices.
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45 | d2b59317 | pbrook | Keep a count of the number of devices with raised IRQs. */
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46 | 52fc1d83 | balrog | int nirq;
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47 | 80b3ada7 | pbrook | int irq_count[];
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48 | 30468f78 | bellard | }; |
49 | 69b91039 | bellard | |
50 | 1941d19c | bellard | static void pci_update_mappings(PCIDevice *d); |
51 | d537cf6c | pbrook | static void pci_set_irq(void *opaque, int irq_num, int level); |
52 | 1941d19c | bellard | |
53 | 69b91039 | bellard | target_phys_addr_t pci_mem_base; |
54 | d350d97d | aliguori | static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
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55 | d350d97d | aliguori | static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
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56 | 0ac32c83 | bellard | static int pci_irq_index; |
57 | 30468f78 | bellard | static PCIBus *first_bus;
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58 | 30468f78 | bellard | |
59 | 52fc1d83 | balrog | static void pcibus_save(QEMUFile *f, void *opaque) |
60 | 52fc1d83 | balrog | { |
61 | 52fc1d83 | balrog | PCIBus *bus = (PCIBus *)opaque; |
62 | 52fc1d83 | balrog | int i;
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63 | 52fc1d83 | balrog | |
64 | 52fc1d83 | balrog | qemu_put_be32(f, bus->nirq); |
65 | 52fc1d83 | balrog | for (i = 0; i < bus->nirq; i++) |
66 | 52fc1d83 | balrog | qemu_put_be32(f, bus->irq_count[i]); |
67 | 52fc1d83 | balrog | } |
68 | 52fc1d83 | balrog | |
69 | 52fc1d83 | balrog | static int pcibus_load(QEMUFile *f, void *opaque, int version_id) |
70 | 52fc1d83 | balrog | { |
71 | 52fc1d83 | balrog | PCIBus *bus = (PCIBus *)opaque; |
72 | 52fc1d83 | balrog | int i, nirq;
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73 | 52fc1d83 | balrog | |
74 | 52fc1d83 | balrog | if (version_id != 1) |
75 | 52fc1d83 | balrog | return -EINVAL;
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76 | 52fc1d83 | balrog | |
77 | 52fc1d83 | balrog | nirq = qemu_get_be32(f); |
78 | 52fc1d83 | balrog | if (bus->nirq != nirq) {
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79 | 52fc1d83 | balrog | fprintf(stderr, "pcibus_load: nirq mismatch: src=%d dst=%d\n",
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80 | 52fc1d83 | balrog | nirq, bus->nirq); |
81 | 52fc1d83 | balrog | return -EINVAL;
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82 | 52fc1d83 | balrog | } |
83 | 52fc1d83 | balrog | |
84 | 52fc1d83 | balrog | for (i = 0; i < nirq; i++) |
85 | 52fc1d83 | balrog | bus->irq_count[i] = qemu_get_be32(f); |
86 | 52fc1d83 | balrog | |
87 | 52fc1d83 | balrog | return 0; |
88 | 52fc1d83 | balrog | } |
89 | 52fc1d83 | balrog | |
90 | d2b59317 | pbrook | PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
91 | d537cf6c | pbrook | qemu_irq *pic, int devfn_min, int nirq) |
92 | 30468f78 | bellard | { |
93 | 30468f78 | bellard | PCIBus *bus; |
94 | 52fc1d83 | balrog | static int nbus = 0; |
95 | 52fc1d83 | balrog | |
96 | 80b3ada7 | pbrook | bus = qemu_mallocz(sizeof(PCIBus) + (nirq * sizeof(int))); |
97 | 502a5395 | pbrook | bus->set_irq = set_irq; |
98 | d2b59317 | pbrook | bus->map_irq = map_irq; |
99 | 502a5395 | pbrook | bus->irq_opaque = pic; |
100 | 502a5395 | pbrook | bus->devfn_min = devfn_min; |
101 | 52fc1d83 | balrog | bus->nirq = nirq; |
102 | 30468f78 | bellard | first_bus = bus; |
103 | 52fc1d83 | balrog | register_savevm("PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus); |
104 | 30468f78 | bellard | return bus;
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105 | 30468f78 | bellard | } |
106 | 69b91039 | bellard | |
107 | 9596ebb7 | pbrook | static PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
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108 | 80b3ada7 | pbrook | { |
109 | 80b3ada7 | pbrook | PCIBus *bus; |
110 | 80b3ada7 | pbrook | bus = qemu_mallocz(sizeof(PCIBus));
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111 | 80b3ada7 | pbrook | bus->map_irq = map_irq; |
112 | 80b3ada7 | pbrook | bus->parent_dev = dev; |
113 | 80b3ada7 | pbrook | bus->next = dev->bus->next; |
114 | 80b3ada7 | pbrook | dev->bus->next = bus; |
115 | 80b3ada7 | pbrook | return bus;
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116 | 80b3ada7 | pbrook | } |
117 | 80b3ada7 | pbrook | |
118 | 502a5395 | pbrook | int pci_bus_num(PCIBus *s)
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119 | 502a5395 | pbrook | { |
120 | 502a5395 | pbrook | return s->bus_num;
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121 | 502a5395 | pbrook | } |
122 | 502a5395 | pbrook | |
123 | 1941d19c | bellard | void pci_device_save(PCIDevice *s, QEMUFile *f)
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124 | 30ca2aab | bellard | { |
125 | 52fc1d83 | balrog | int i;
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126 | 52fc1d83 | balrog | |
127 | 52fc1d83 | balrog | qemu_put_be32(f, 2); /* PCI device version */ |
128 | 30ca2aab | bellard | qemu_put_buffer(f, s->config, 256);
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129 | 52fc1d83 | balrog | for (i = 0; i < 4; i++) |
130 | 52fc1d83 | balrog | qemu_put_be32(f, s->irq_state[i]); |
131 | 30ca2aab | bellard | } |
132 | 30ca2aab | bellard | |
133 | 1941d19c | bellard | int pci_device_load(PCIDevice *s, QEMUFile *f)
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134 | 30ca2aab | bellard | { |
135 | 1941d19c | bellard | uint32_t version_id; |
136 | 52fc1d83 | balrog | int i;
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137 | 52fc1d83 | balrog | |
138 | 1941d19c | bellard | version_id = qemu_get_be32(f); |
139 | 52fc1d83 | balrog | if (version_id > 2) |
140 | 30ca2aab | bellard | return -EINVAL;
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141 | 30ca2aab | bellard | qemu_get_buffer(f, s->config, 256);
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142 | 1941d19c | bellard | pci_update_mappings(s); |
143 | 52fc1d83 | balrog | |
144 | 52fc1d83 | balrog | if (version_id >= 2) |
145 | 52fc1d83 | balrog | for (i = 0; i < 4; i ++) |
146 | 52fc1d83 | balrog | s->irq_state[i] = qemu_get_be32(f); |
147 | 52fc1d83 | balrog | |
148 | 30ca2aab | bellard | return 0; |
149 | 30ca2aab | bellard | } |
150 | 30ca2aab | bellard | |
151 | d350d97d | aliguori | static int pci_set_default_subsystem_id(PCIDevice *pci_dev) |
152 | d350d97d | aliguori | { |
153 | d350d97d | aliguori | uint16_t *id; |
154 | d350d97d | aliguori | |
155 | d350d97d | aliguori | id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
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156 | d350d97d | aliguori | id[0] = cpu_to_le16(pci_default_sub_vendor_id);
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157 | d350d97d | aliguori | id[1] = cpu_to_le16(pci_default_sub_device_id);
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158 | d350d97d | aliguori | return 0; |
159 | d350d97d | aliguori | } |
160 | d350d97d | aliguori | |
161 | 69b91039 | bellard | /* -1 for devfn means auto assign */
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162 | 5fafdf24 | ths | PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
163 | 30468f78 | bellard | int instance_size, int devfn, |
164 | 5fafdf24 | ths | PCIConfigReadFunc *config_read, |
165 | 69b91039 | bellard | PCIConfigWriteFunc *config_write) |
166 | 69b91039 | bellard | { |
167 | 30468f78 | bellard | PCIDevice *pci_dev; |
168 | 69b91039 | bellard | |
169 | 0ac32c83 | bellard | if (pci_irq_index >= PCI_DEVICES_MAX)
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170 | 0ac32c83 | bellard | return NULL; |
171 | 3b46e624 | ths | |
172 | 69b91039 | bellard | if (devfn < 0) { |
173 | 30468f78 | bellard | for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) { |
174 | 30468f78 | bellard | if (!bus->devices[devfn])
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175 | 69b91039 | bellard | goto found;
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176 | 69b91039 | bellard | } |
177 | 69b91039 | bellard | return NULL; |
178 | 69b91039 | bellard | found: ;
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179 | 69b91039 | bellard | } |
180 | 69b91039 | bellard | pci_dev = qemu_mallocz(instance_size); |
181 | 69b91039 | bellard | if (!pci_dev)
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182 | 69b91039 | bellard | return NULL; |
183 | 30468f78 | bellard | pci_dev->bus = bus; |
184 | 69b91039 | bellard | pci_dev->devfn = devfn; |
185 | 69b91039 | bellard | pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
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186 | d2b59317 | pbrook | memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state)); |
187 | d350d97d | aliguori | pci_set_default_subsystem_id(pci_dev); |
188 | 0ac32c83 | bellard | |
189 | 0ac32c83 | bellard | if (!config_read)
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190 | 0ac32c83 | bellard | config_read = pci_default_read_config; |
191 | 0ac32c83 | bellard | if (!config_write)
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192 | 0ac32c83 | bellard | config_write = pci_default_write_config; |
193 | 69b91039 | bellard | pci_dev->config_read = config_read; |
194 | 69b91039 | bellard | pci_dev->config_write = config_write; |
195 | 0ac32c83 | bellard | pci_dev->irq_index = pci_irq_index++; |
196 | 30468f78 | bellard | bus->devices[devfn] = pci_dev; |
197 | d537cf6c | pbrook | pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
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198 | 69b91039 | bellard | return pci_dev;
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199 | 69b91039 | bellard | } |
200 | 69b91039 | bellard | |
201 | 5fafdf24 | ths | void pci_register_io_region(PCIDevice *pci_dev, int region_num, |
202 | 5fafdf24 | ths | uint32_t size, int type,
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203 | 69b91039 | bellard | PCIMapIORegionFunc *map_func) |
204 | 69b91039 | bellard | { |
205 | 69b91039 | bellard | PCIIORegion *r; |
206 | d7ce493a | pbrook | uint32_t addr; |
207 | 69b91039 | bellard | |
208 | 8a8696a3 | bellard | if ((unsigned int)region_num >= PCI_NUM_REGIONS) |
209 | 69b91039 | bellard | return;
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210 | 69b91039 | bellard | r = &pci_dev->io_regions[region_num]; |
211 | 69b91039 | bellard | r->addr = -1;
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212 | 69b91039 | bellard | r->size = size; |
213 | 69b91039 | bellard | r->type = type; |
214 | 69b91039 | bellard | r->map_func = map_func; |
215 | d7ce493a | pbrook | if (region_num == PCI_ROM_SLOT) {
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216 | d7ce493a | pbrook | addr = 0x30;
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217 | d7ce493a | pbrook | } else {
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218 | d7ce493a | pbrook | addr = 0x10 + region_num * 4; |
219 | d7ce493a | pbrook | } |
220 | d7ce493a | pbrook | *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type); |
221 | 69b91039 | bellard | } |
222 | 69b91039 | bellard | |
223 | 9596ebb7 | pbrook | static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
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224 | 69b91039 | bellard | { |
225 | 502a5395 | pbrook | return addr + pci_mem_base;
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226 | 69b91039 | bellard | } |
227 | 69b91039 | bellard | |
228 | 0ac32c83 | bellard | static void pci_update_mappings(PCIDevice *d) |
229 | 0ac32c83 | bellard | { |
230 | 0ac32c83 | bellard | PCIIORegion *r; |
231 | 0ac32c83 | bellard | int cmd, i;
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232 | 8a8696a3 | bellard | uint32_t last_addr, new_addr, config_ofs; |
233 | 3b46e624 | ths | |
234 | 0ac32c83 | bellard | cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND)); |
235 | 8a8696a3 | bellard | for(i = 0; i < PCI_NUM_REGIONS; i++) { |
236 | 0ac32c83 | bellard | r = &d->io_regions[i]; |
237 | 8a8696a3 | bellard | if (i == PCI_ROM_SLOT) {
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238 | 8a8696a3 | bellard | config_ofs = 0x30;
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239 | 8a8696a3 | bellard | } else {
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240 | 8a8696a3 | bellard | config_ofs = 0x10 + i * 4; |
241 | 8a8696a3 | bellard | } |
242 | 0ac32c83 | bellard | if (r->size != 0) { |
243 | 0ac32c83 | bellard | if (r->type & PCI_ADDRESS_SPACE_IO) {
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244 | 0ac32c83 | bellard | if (cmd & PCI_COMMAND_IO) {
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245 | 5fafdf24 | ths | new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
246 | 8a8696a3 | bellard | config_ofs)); |
247 | 0ac32c83 | bellard | new_addr = new_addr & ~(r->size - 1);
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248 | 0ac32c83 | bellard | last_addr = new_addr + r->size - 1;
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249 | 0ac32c83 | bellard | /* NOTE: we have only 64K ioports on PC */
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250 | 0ac32c83 | bellard | if (last_addr <= new_addr || new_addr == 0 || |
251 | 0ac32c83 | bellard | last_addr >= 0x10000) {
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252 | 0ac32c83 | bellard | new_addr = -1;
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253 | 0ac32c83 | bellard | } |
254 | 0ac32c83 | bellard | } else {
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255 | 0ac32c83 | bellard | new_addr = -1;
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256 | 0ac32c83 | bellard | } |
257 | 0ac32c83 | bellard | } else {
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258 | 0ac32c83 | bellard | if (cmd & PCI_COMMAND_MEMORY) {
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259 | 5fafdf24 | ths | new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
260 | 8a8696a3 | bellard | config_ofs)); |
261 | 8a8696a3 | bellard | /* the ROM slot has a specific enable bit */
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262 | 8a8696a3 | bellard | if (i == PCI_ROM_SLOT && !(new_addr & 1)) |
263 | 8a8696a3 | bellard | goto no_mem_map;
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264 | 0ac32c83 | bellard | new_addr = new_addr & ~(r->size - 1);
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265 | 0ac32c83 | bellard | last_addr = new_addr + r->size - 1;
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266 | 0ac32c83 | bellard | /* NOTE: we do not support wrapping */
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267 | 0ac32c83 | bellard | /* XXX: as we cannot support really dynamic
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268 | 0ac32c83 | bellard | mappings, we handle specific values as invalid
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269 | 0ac32c83 | bellard | mappings. */
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270 | 0ac32c83 | bellard | if (last_addr <= new_addr || new_addr == 0 || |
271 | 0ac32c83 | bellard | last_addr == -1) {
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272 | 0ac32c83 | bellard | new_addr = -1;
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273 | 0ac32c83 | bellard | } |
274 | 0ac32c83 | bellard | } else {
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275 | 8a8696a3 | bellard | no_mem_map:
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276 | 0ac32c83 | bellard | new_addr = -1;
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277 | 0ac32c83 | bellard | } |
278 | 0ac32c83 | bellard | } |
279 | 0ac32c83 | bellard | /* now do the real mapping */
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280 | 0ac32c83 | bellard | if (new_addr != r->addr) {
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281 | 0ac32c83 | bellard | if (r->addr != -1) { |
282 | 0ac32c83 | bellard | if (r->type & PCI_ADDRESS_SPACE_IO) {
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283 | 0ac32c83 | bellard | int class;
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284 | 0ac32c83 | bellard | /* NOTE: specific hack for IDE in PC case:
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285 | 0ac32c83 | bellard | only one byte must be mapped. */
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286 | 0ac32c83 | bellard | class = d->config[0x0a] | (d->config[0x0b] << 8); |
287 | 0ac32c83 | bellard | if (class == 0x0101 && r->size == 4) { |
288 | 0ac32c83 | bellard | isa_unassign_ioport(r->addr + 2, 1); |
289 | 0ac32c83 | bellard | } else {
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290 | 0ac32c83 | bellard | isa_unassign_ioport(r->addr, r->size); |
291 | 0ac32c83 | bellard | } |
292 | 0ac32c83 | bellard | } else {
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293 | 502a5395 | pbrook | cpu_register_physical_memory(pci_to_cpu_addr(r->addr), |
294 | 5fafdf24 | ths | r->size, |
295 | 0ac32c83 | bellard | IO_MEM_UNASSIGNED); |
296 | f65ed4c1 | aliguori | qemu_unregister_coalesced_mmio(r->addr, r->size); |
297 | 0ac32c83 | bellard | } |
298 | 0ac32c83 | bellard | } |
299 | 0ac32c83 | bellard | r->addr = new_addr; |
300 | 0ac32c83 | bellard | if (r->addr != -1) { |
301 | 0ac32c83 | bellard | r->map_func(d, i, r->addr, r->size, r->type); |
302 | 0ac32c83 | bellard | } |
303 | 0ac32c83 | bellard | } |
304 | 0ac32c83 | bellard | } |
305 | 0ac32c83 | bellard | } |
306 | 0ac32c83 | bellard | } |
307 | 0ac32c83 | bellard | |
308 | 5fafdf24 | ths | uint32_t pci_default_read_config(PCIDevice *d, |
309 | 0ac32c83 | bellard | uint32_t address, int len)
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310 | 69b91039 | bellard | { |
311 | 0ac32c83 | bellard | uint32_t val; |
312 | a2d4e44b | ths | |
313 | 0ac32c83 | bellard | switch(len) {
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314 | 0ac32c83 | bellard | default:
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315 | 0ac32c83 | bellard | case 4: |
316 | a2d4e44b | ths | if (address <= 0xfc) { |
317 | a2d4e44b | ths | val = le32_to_cpu(*(uint32_t *)(d->config + address)); |
318 | a2d4e44b | ths | break;
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319 | a2d4e44b | ths | } |
320 | a2d4e44b | ths | /* fall through */
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321 | a2d4e44b | ths | case 2: |
322 | a2d4e44b | ths | if (address <= 0xfe) { |
323 | a2d4e44b | ths | val = le16_to_cpu(*(uint16_t *)(d->config + address)); |
324 | a2d4e44b | ths | break;
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325 | a2d4e44b | ths | } |
326 | a2d4e44b | ths | /* fall through */
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327 | a2d4e44b | ths | case 1: |
328 | a2d4e44b | ths | val = d->config[address]; |
329 | 0ac32c83 | bellard | break;
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330 | 0ac32c83 | bellard | } |
331 | 0ac32c83 | bellard | return val;
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332 | 0ac32c83 | bellard | } |
333 | 0ac32c83 | bellard | |
334 | 5fafdf24 | ths | void pci_default_write_config(PCIDevice *d,
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335 | 0ac32c83 | bellard | uint32_t address, uint32_t val, int len)
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336 | 0ac32c83 | bellard | { |
337 | 0ac32c83 | bellard | int can_write, i;
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338 | 7bf5be70 | bellard | uint32_t end, addr; |
339 | 0ac32c83 | bellard | |
340 | 5fafdf24 | ths | if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) || |
341 | 8a8696a3 | bellard | (address >= 0x30 && address < 0x34))) { |
342 | 0ac32c83 | bellard | PCIIORegion *r; |
343 | 0ac32c83 | bellard | int reg;
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344 | 0ac32c83 | bellard | |
345 | 8a8696a3 | bellard | if ( address >= 0x30 ) { |
346 | 8a8696a3 | bellard | reg = PCI_ROM_SLOT; |
347 | 8a8696a3 | bellard | }else{
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348 | 8a8696a3 | bellard | reg = (address - 0x10) >> 2; |
349 | 8a8696a3 | bellard | } |
350 | 0ac32c83 | bellard | r = &d->io_regions[reg]; |
351 | 0ac32c83 | bellard | if (r->size == 0) |
352 | 0ac32c83 | bellard | goto default_config;
|
353 | 0ac32c83 | bellard | /* compute the stored value */
|
354 | 8a8696a3 | bellard | if (reg == PCI_ROM_SLOT) {
|
355 | 8a8696a3 | bellard | /* keep ROM enable bit */
|
356 | 8a8696a3 | bellard | val &= (~(r->size - 1)) | 1; |
357 | 8a8696a3 | bellard | } else {
|
358 | 8a8696a3 | bellard | val &= ~(r->size - 1);
|
359 | 8a8696a3 | bellard | val |= r->type; |
360 | 8a8696a3 | bellard | } |
361 | 8a8696a3 | bellard | *(uint32_t *)(d->config + address) = cpu_to_le32(val); |
362 | 0ac32c83 | bellard | pci_update_mappings(d); |
363 | 69b91039 | bellard | return;
|
364 | 0ac32c83 | bellard | } |
365 | 0ac32c83 | bellard | default_config:
|
366 | 0ac32c83 | bellard | /* not efficient, but simple */
|
367 | 7bf5be70 | bellard | addr = address; |
368 | 0ac32c83 | bellard | for(i = 0; i < len; i++) { |
369 | 0ac32c83 | bellard | /* default read/write accesses */
|
370 | 1f62d938 | bellard | switch(d->config[0x0e]) { |
371 | 0ac32c83 | bellard | case 0x00: |
372 | 1f62d938 | bellard | case 0x80: |
373 | 1f62d938 | bellard | switch(addr) {
|
374 | 1f62d938 | bellard | case 0x00: |
375 | 1f62d938 | bellard | case 0x01: |
376 | 1f62d938 | bellard | case 0x02: |
377 | 1f62d938 | bellard | case 0x03: |
378 | 1f62d938 | bellard | case 0x08: |
379 | 1f62d938 | bellard | case 0x09: |
380 | 1f62d938 | bellard | case 0x0a: |
381 | 1f62d938 | bellard | case 0x0b: |
382 | 1f62d938 | bellard | case 0x0e: |
383 | 1f62d938 | bellard | case 0x10 ... 0x27: /* base */ |
384 | 8098ed41 | aurel32 | case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */ |
385 | 1f62d938 | bellard | case 0x30 ... 0x33: /* rom */ |
386 | 1f62d938 | bellard | case 0x3d: |
387 | 1f62d938 | bellard | can_write = 0;
|
388 | 1f62d938 | bellard | break;
|
389 | 1f62d938 | bellard | default:
|
390 | 1f62d938 | bellard | can_write = 1;
|
391 | 1f62d938 | bellard | break;
|
392 | 1f62d938 | bellard | } |
393 | 0ac32c83 | bellard | break;
|
394 | 0ac32c83 | bellard | default:
|
395 | 1f62d938 | bellard | case 0x01: |
396 | 1f62d938 | bellard | switch(addr) {
|
397 | 1f62d938 | bellard | case 0x00: |
398 | 1f62d938 | bellard | case 0x01: |
399 | 1f62d938 | bellard | case 0x02: |
400 | 1f62d938 | bellard | case 0x03: |
401 | 1f62d938 | bellard | case 0x08: |
402 | 1f62d938 | bellard | case 0x09: |
403 | 1f62d938 | bellard | case 0x0a: |
404 | 1f62d938 | bellard | case 0x0b: |
405 | 1f62d938 | bellard | case 0x0e: |
406 | 8098ed41 | aurel32 | case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */ |
407 | 1f62d938 | bellard | case 0x38 ... 0x3b: /* rom */ |
408 | 1f62d938 | bellard | case 0x3d: |
409 | 1f62d938 | bellard | can_write = 0;
|
410 | 1f62d938 | bellard | break;
|
411 | 1f62d938 | bellard | default:
|
412 | 1f62d938 | bellard | can_write = 1;
|
413 | 1f62d938 | bellard | break;
|
414 | 1f62d938 | bellard | } |
415 | 0ac32c83 | bellard | break;
|
416 | 0ac32c83 | bellard | } |
417 | 0ac32c83 | bellard | if (can_write) {
|
418 | 8098ed41 | aurel32 | /* Mask out writes to reserved bits in registers */
|
419 | 8098ed41 | aurel32 | switch (addr) {
|
420 | 475dc65f | aurel32 | case 0x05: |
421 | 475dc65f | aurel32 | val &= ~PCI_COMMAND_RESERVED_MASK_HI; |
422 | 475dc65f | aurel32 | break;
|
423 | 8098ed41 | aurel32 | case 0x06: |
424 | 8098ed41 | aurel32 | val &= ~PCI_STATUS_RESERVED_MASK_LO; |
425 | 8098ed41 | aurel32 | break;
|
426 | 8098ed41 | aurel32 | case 0x07: |
427 | 8098ed41 | aurel32 | val &= ~PCI_STATUS_RESERVED_MASK_HI; |
428 | 8098ed41 | aurel32 | break;
|
429 | 8098ed41 | aurel32 | } |
430 | 7bf5be70 | bellard | d->config[addr] = val; |
431 | 0ac32c83 | bellard | } |
432 | a2d4e44b | ths | if (++addr > 0xff) |
433 | a2d4e44b | ths | break;
|
434 | 0ac32c83 | bellard | val >>= 8;
|
435 | 0ac32c83 | bellard | } |
436 | 0ac32c83 | bellard | |
437 | 0ac32c83 | bellard | end = address + len; |
438 | 0ac32c83 | bellard | if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) { |
439 | 0ac32c83 | bellard | /* if the command register is modified, we must modify the mappings */
|
440 | 0ac32c83 | bellard | pci_update_mappings(d); |
441 | 69b91039 | bellard | } |
442 | 69b91039 | bellard | } |
443 | 69b91039 | bellard | |
444 | 502a5395 | pbrook | void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len) |
445 | 69b91039 | bellard | { |
446 | 30468f78 | bellard | PCIBus *s = opaque; |
447 | 30468f78 | bellard | PCIDevice *pci_dev; |
448 | 30468f78 | bellard | int config_addr, bus_num;
|
449 | 3b46e624 | ths | |
450 | 69b91039 | bellard | #if defined(DEBUG_PCI) && 0 |
451 | 69b91039 | bellard | printf("pci_data_write: addr=%08x val=%08x len=%d\n",
|
452 | 502a5395 | pbrook | addr, val, len); |
453 | 69b91039 | bellard | #endif
|
454 | 502a5395 | pbrook | bus_num = (addr >> 16) & 0xff; |
455 | 80b3ada7 | pbrook | while (s && s->bus_num != bus_num)
|
456 | 80b3ada7 | pbrook | s = s->next; |
457 | 80b3ada7 | pbrook | if (!s)
|
458 | 69b91039 | bellard | return;
|
459 | 502a5395 | pbrook | pci_dev = s->devices[(addr >> 8) & 0xff]; |
460 | 69b91039 | bellard | if (!pci_dev)
|
461 | 69b91039 | bellard | return;
|
462 | 502a5395 | pbrook | config_addr = addr & 0xff;
|
463 | 69b91039 | bellard | #if defined(DEBUG_PCI)
|
464 | 69b91039 | bellard | printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
|
465 | 69b91039 | bellard | pci_dev->name, config_addr, val, len); |
466 | 69b91039 | bellard | #endif
|
467 | 0ac32c83 | bellard | pci_dev->config_write(pci_dev, config_addr, val, len); |
468 | 69b91039 | bellard | } |
469 | 69b91039 | bellard | |
470 | 502a5395 | pbrook | uint32_t pci_data_read(void *opaque, uint32_t addr, int len) |
471 | 69b91039 | bellard | { |
472 | 30468f78 | bellard | PCIBus *s = opaque; |
473 | 30468f78 | bellard | PCIDevice *pci_dev; |
474 | 30468f78 | bellard | int config_addr, bus_num;
|
475 | 69b91039 | bellard | uint32_t val; |
476 | 69b91039 | bellard | |
477 | 502a5395 | pbrook | bus_num = (addr >> 16) & 0xff; |
478 | 80b3ada7 | pbrook | while (s && s->bus_num != bus_num)
|
479 | 80b3ada7 | pbrook | s= s->next; |
480 | 80b3ada7 | pbrook | if (!s)
|
481 | 69b91039 | bellard | goto fail;
|
482 | 502a5395 | pbrook | pci_dev = s->devices[(addr >> 8) & 0xff]; |
483 | 69b91039 | bellard | if (!pci_dev) {
|
484 | 69b91039 | bellard | fail:
|
485 | 63ce9e0a | bellard | switch(len) {
|
486 | 63ce9e0a | bellard | case 1: |
487 | 63ce9e0a | bellard | val = 0xff;
|
488 | 63ce9e0a | bellard | break;
|
489 | 63ce9e0a | bellard | case 2: |
490 | 63ce9e0a | bellard | val = 0xffff;
|
491 | 63ce9e0a | bellard | break;
|
492 | 63ce9e0a | bellard | default:
|
493 | 63ce9e0a | bellard | case 4: |
494 | 63ce9e0a | bellard | val = 0xffffffff;
|
495 | 63ce9e0a | bellard | break;
|
496 | 63ce9e0a | bellard | } |
497 | 69b91039 | bellard | goto the_end;
|
498 | 69b91039 | bellard | } |
499 | 502a5395 | pbrook | config_addr = addr & 0xff;
|
500 | 69b91039 | bellard | val = pci_dev->config_read(pci_dev, config_addr, len); |
501 | 69b91039 | bellard | #if defined(DEBUG_PCI)
|
502 | 69b91039 | bellard | printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
|
503 | 69b91039 | bellard | pci_dev->name, config_addr, val, len); |
504 | 69b91039 | bellard | #endif
|
505 | 69b91039 | bellard | the_end:
|
506 | 69b91039 | bellard | #if defined(DEBUG_PCI) && 0 |
507 | 69b91039 | bellard | printf("pci_data_read: addr=%08x val=%08x len=%d\n",
|
508 | 502a5395 | pbrook | addr, val, len); |
509 | 69b91039 | bellard | #endif
|
510 | 69b91039 | bellard | return val;
|
511 | 69b91039 | bellard | } |
512 | 69b91039 | bellard | |
513 | 502a5395 | pbrook | /***********************************************************/
|
514 | 502a5395 | pbrook | /* generic PCI irq support */
|
515 | 30468f78 | bellard | |
516 | 502a5395 | pbrook | /* 0 <= irq_num <= 3. level must be 0 or 1 */
|
517 | d537cf6c | pbrook | static void pci_set_irq(void *opaque, int irq_num, int level) |
518 | 69b91039 | bellard | { |
519 | d537cf6c | pbrook | PCIDevice *pci_dev = (PCIDevice *)opaque; |
520 | 80b3ada7 | pbrook | PCIBus *bus; |
521 | 80b3ada7 | pbrook | int change;
|
522 | 3b46e624 | ths | |
523 | 80b3ada7 | pbrook | change = level - pci_dev->irq_state[irq_num]; |
524 | 80b3ada7 | pbrook | if (!change)
|
525 | 80b3ada7 | pbrook | return;
|
526 | d2b59317 | pbrook | |
527 | d2b59317 | pbrook | pci_dev->irq_state[irq_num] = level; |
528 | 5e966ce6 | pbrook | for (;;) {
|
529 | 5e966ce6 | pbrook | bus = pci_dev->bus; |
530 | 80b3ada7 | pbrook | irq_num = bus->map_irq(pci_dev, irq_num); |
531 | 5e966ce6 | pbrook | if (bus->set_irq)
|
532 | 5e966ce6 | pbrook | break;
|
533 | 80b3ada7 | pbrook | pci_dev = bus->parent_dev; |
534 | 80b3ada7 | pbrook | } |
535 | 80b3ada7 | pbrook | bus->irq_count[irq_num] += change; |
536 | d2b59317 | pbrook | bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
|
537 | 69b91039 | bellard | } |
538 | 69b91039 | bellard | |
539 | 502a5395 | pbrook | /***********************************************************/
|
540 | 502a5395 | pbrook | /* monitor info on PCI */
|
541 | 0ac32c83 | bellard | |
542 | 6650ee6d | pbrook | typedef struct { |
543 | 6650ee6d | pbrook | uint16_t class; |
544 | 6650ee6d | pbrook | const char *desc; |
545 | 6650ee6d | pbrook | } pci_class_desc; |
546 | 6650ee6d | pbrook | |
547 | 09bc878a | blueswir1 | static const pci_class_desc pci_class_descriptions[] = |
548 | 6650ee6d | pbrook | { |
549 | 4ca9c76f | pbrook | { 0x0100, "SCSI controller"}, |
550 | 6650ee6d | pbrook | { 0x0101, "IDE controller"}, |
551 | dcb5b19a | ths | { 0x0102, "Floppy controller"}, |
552 | dcb5b19a | ths | { 0x0103, "IPI controller"}, |
553 | dcb5b19a | ths | { 0x0104, "RAID controller"}, |
554 | dcb5b19a | ths | { 0x0106, "SATA controller"}, |
555 | dcb5b19a | ths | { 0x0107, "SAS controller"}, |
556 | dcb5b19a | ths | { 0x0180, "Storage controller"}, |
557 | 6650ee6d | pbrook | { 0x0200, "Ethernet controller"}, |
558 | dcb5b19a | ths | { 0x0201, "Token Ring controller"}, |
559 | dcb5b19a | ths | { 0x0202, "FDDI controller"}, |
560 | dcb5b19a | ths | { 0x0203, "ATM controller"}, |
561 | dcb5b19a | ths | { 0x0280, "Network controller"}, |
562 | 6650ee6d | pbrook | { 0x0300, "VGA controller"}, |
563 | dcb5b19a | ths | { 0x0301, "XGA controller"}, |
564 | dcb5b19a | ths | { 0x0302, "3D controller"}, |
565 | dcb5b19a | ths | { 0x0380, "Display controller"}, |
566 | dcb5b19a | ths | { 0x0400, "Video controller"}, |
567 | dcb5b19a | ths | { 0x0401, "Audio controller"}, |
568 | dcb5b19a | ths | { 0x0402, "Phone"}, |
569 | dcb5b19a | ths | { 0x0480, "Multimedia controller"}, |
570 | dcb5b19a | ths | { 0x0500, "RAM controller"}, |
571 | dcb5b19a | ths | { 0x0501, "Flash controller"}, |
572 | dcb5b19a | ths | { 0x0580, "Memory controller"}, |
573 | 6650ee6d | pbrook | { 0x0600, "Host bridge"}, |
574 | 6650ee6d | pbrook | { 0x0601, "ISA bridge"}, |
575 | dcb5b19a | ths | { 0x0602, "EISA bridge"}, |
576 | dcb5b19a | ths | { 0x0603, "MC bridge"}, |
577 | 6650ee6d | pbrook | { 0x0604, "PCI bridge"}, |
578 | dcb5b19a | ths | { 0x0605, "PCMCIA bridge"}, |
579 | dcb5b19a | ths | { 0x0606, "NUBUS bridge"}, |
580 | dcb5b19a | ths | { 0x0607, "CARDBUS bridge"}, |
581 | dcb5b19a | ths | { 0x0608, "RACEWAY bridge"}, |
582 | dcb5b19a | ths | { 0x0680, "Bridge"}, |
583 | 6650ee6d | pbrook | { 0x0c03, "USB controller"}, |
584 | 6650ee6d | pbrook | { 0, NULL} |
585 | 6650ee6d | pbrook | }; |
586 | 6650ee6d | pbrook | |
587 | 502a5395 | pbrook | static void pci_info_device(PCIDevice *d) |
588 | 30468f78 | bellard | { |
589 | 502a5395 | pbrook | int i, class;
|
590 | 502a5395 | pbrook | PCIIORegion *r; |
591 | 09bc878a | blueswir1 | const pci_class_desc *desc;
|
592 | 30468f78 | bellard | |
593 | 502a5395 | pbrook | term_printf(" Bus %2d, device %3d, function %d:\n",
|
594 | 502a5395 | pbrook | d->bus->bus_num, d->devfn >> 3, d->devfn & 7); |
595 | 502a5395 | pbrook | class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE))); |
596 | 502a5395 | pbrook | term_printf(" ");
|
597 | 6650ee6d | pbrook | desc = pci_class_descriptions; |
598 | 6650ee6d | pbrook | while (desc->desc && class != desc->class)
|
599 | 6650ee6d | pbrook | desc++; |
600 | 6650ee6d | pbrook | if (desc->desc) {
|
601 | 6650ee6d | pbrook | term_printf("%s", desc->desc);
|
602 | 6650ee6d | pbrook | } else {
|
603 | 502a5395 | pbrook | term_printf("Class %04x", class);
|
604 | 72cc6cfe | bellard | } |
605 | 502a5395 | pbrook | term_printf(": PCI device %04x:%04x\n",
|
606 | 502a5395 | pbrook | le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))), |
607 | 502a5395 | pbrook | le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID)))); |
608 | 30468f78 | bellard | |
609 | 502a5395 | pbrook | if (d->config[PCI_INTERRUPT_PIN] != 0) { |
610 | 502a5395 | pbrook | term_printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
|
611 | 30468f78 | bellard | } |
612 | 80b3ada7 | pbrook | if (class == 0x0604) { |
613 | 80b3ada7 | pbrook | term_printf(" BUS %d.\n", d->config[0x19]); |
614 | 80b3ada7 | pbrook | } |
615 | 502a5395 | pbrook | for(i = 0;i < PCI_NUM_REGIONS; i++) { |
616 | 502a5395 | pbrook | r = &d->io_regions[i]; |
617 | 502a5395 | pbrook | if (r->size != 0) { |
618 | 502a5395 | pbrook | term_printf(" BAR%d: ", i);
|
619 | 502a5395 | pbrook | if (r->type & PCI_ADDRESS_SPACE_IO) {
|
620 | 5fafdf24 | ths | term_printf("I/O at 0x%04x [0x%04x].\n",
|
621 | 502a5395 | pbrook | r->addr, r->addr + r->size - 1);
|
622 | 502a5395 | pbrook | } else {
|
623 | 5fafdf24 | ths | term_printf("32 bit memory at 0x%08x [0x%08x].\n",
|
624 | 502a5395 | pbrook | r->addr, r->addr + r->size - 1);
|
625 | 502a5395 | pbrook | } |
626 | 502a5395 | pbrook | } |
627 | 77d4bc34 | bellard | } |
628 | 80b3ada7 | pbrook | if (class == 0x0604 && d->config[0x19] != 0) { |
629 | 80b3ada7 | pbrook | pci_for_each_device(d->config[0x19], pci_info_device);
|
630 | 80b3ada7 | pbrook | } |
631 | 384d8876 | bellard | } |
632 | 384d8876 | bellard | |
633 | 80b3ada7 | pbrook | void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d)) |
634 | 384d8876 | bellard | { |
635 | 502a5395 | pbrook | PCIBus *bus = first_bus; |
636 | 384d8876 | bellard | PCIDevice *d; |
637 | 502a5395 | pbrook | int devfn;
|
638 | 3b46e624 | ths | |
639 | 80b3ada7 | pbrook | while (bus && bus->bus_num != bus_num)
|
640 | 80b3ada7 | pbrook | bus = bus->next; |
641 | 502a5395 | pbrook | if (bus) {
|
642 | 502a5395 | pbrook | for(devfn = 0; devfn < 256; devfn++) { |
643 | 502a5395 | pbrook | d = bus->devices[devfn]; |
644 | 502a5395 | pbrook | if (d)
|
645 | 502a5395 | pbrook | fn(d); |
646 | 502a5395 | pbrook | } |
647 | f2aa58c6 | bellard | } |
648 | f2aa58c6 | bellard | } |
649 | f2aa58c6 | bellard | |
650 | 502a5395 | pbrook | void pci_info(void) |
651 | f2aa58c6 | bellard | { |
652 | 80b3ada7 | pbrook | pci_for_each_device(0, pci_info_device);
|
653 | 77d4bc34 | bellard | } |
654 | a41b2ff2 | pbrook | |
655 | cb457d76 | aliguori | static const char * const pci_nic_models[] = { |
656 | cb457d76 | aliguori | "ne2k_pci",
|
657 | cb457d76 | aliguori | "i82551",
|
658 | cb457d76 | aliguori | "i82557b",
|
659 | cb457d76 | aliguori | "i82559er",
|
660 | cb457d76 | aliguori | "rtl8139",
|
661 | cb457d76 | aliguori | "e1000",
|
662 | cb457d76 | aliguori | "pcnet",
|
663 | cb457d76 | aliguori | "virtio",
|
664 | cb457d76 | aliguori | NULL
|
665 | cb457d76 | aliguori | }; |
666 | cb457d76 | aliguori | |
667 | cb457d76 | aliguori | typedef void (*PCINICInitFn)(PCIBus *, NICInfo *, int); |
668 | cb457d76 | aliguori | |
669 | cb457d76 | aliguori | static PCINICInitFn pci_nic_init_fns[] = {
|
670 | cb457d76 | aliguori | pci_ne2000_init, |
671 | cb457d76 | aliguori | pci_i82551_init, |
672 | cb457d76 | aliguori | pci_i82557b_init, |
673 | cb457d76 | aliguori | pci_i82559er_init, |
674 | cb457d76 | aliguori | pci_rtl8139_init, |
675 | cb457d76 | aliguori | pci_e1000_init, |
676 | cb457d76 | aliguori | pci_pcnet_init, |
677 | cb457d76 | aliguori | virtio_net_init, |
678 | cb457d76 | aliguori | NULL
|
679 | cb457d76 | aliguori | }; |
680 | cb457d76 | aliguori | |
681 | a41b2ff2 | pbrook | /* Initialize a PCI NIC. */
|
682 | cb457d76 | aliguori | void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn, |
683 | cb457d76 | aliguori | const char *default_model) |
684 | a41b2ff2 | pbrook | { |
685 | cb457d76 | aliguori | int i;
|
686 | cb457d76 | aliguori | |
687 | cb457d76 | aliguori | qemu_check_nic_model_list(nd, pci_nic_models, default_model); |
688 | cb457d76 | aliguori | |
689 | cb457d76 | aliguori | for (i = 0; pci_nic_models[i]; i++) |
690 | cb457d76 | aliguori | if (strcmp(nd->model, pci_nic_models[i]) == 0) |
691 | cb457d76 | aliguori | pci_nic_init_fns[i](bus, nd, devfn); |
692 | a41b2ff2 | pbrook | } |
693 | a41b2ff2 | pbrook | |
694 | 80b3ada7 | pbrook | typedef struct { |
695 | 80b3ada7 | pbrook | PCIDevice dev; |
696 | 80b3ada7 | pbrook | PCIBus *bus; |
697 | 80b3ada7 | pbrook | } PCIBridge; |
698 | 80b3ada7 | pbrook | |
699 | 9596ebb7 | pbrook | static void pci_bridge_write_config(PCIDevice *d, |
700 | 80b3ada7 | pbrook | uint32_t address, uint32_t val, int len)
|
701 | 80b3ada7 | pbrook | { |
702 | 80b3ada7 | pbrook | PCIBridge *s = (PCIBridge *)d; |
703 | 80b3ada7 | pbrook | |
704 | 80b3ada7 | pbrook | if (address == 0x19 || (address == 0x18 && len > 1)) { |
705 | 80b3ada7 | pbrook | if (address == 0x19) |
706 | 80b3ada7 | pbrook | s->bus->bus_num = val & 0xff;
|
707 | 80b3ada7 | pbrook | else
|
708 | 80b3ada7 | pbrook | s->bus->bus_num = (val >> 8) & 0xff; |
709 | 80b3ada7 | pbrook | #if defined(DEBUG_PCI)
|
710 | 80b3ada7 | pbrook | printf ("pci-bridge: %s: Assigned bus %d\n", d->name, s->bus->bus_num);
|
711 | 80b3ada7 | pbrook | #endif
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712 | 80b3ada7 | pbrook | } |
713 | 80b3ada7 | pbrook | pci_default_write_config(d, address, val, len); |
714 | 80b3ada7 | pbrook | } |
715 | 80b3ada7 | pbrook | |
716 | 80b3ada7 | pbrook | PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
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717 | 80b3ada7 | pbrook | pci_map_irq_fn map_irq, const char *name) |
718 | 80b3ada7 | pbrook | { |
719 | 80b3ada7 | pbrook | PCIBridge *s; |
720 | 5fafdf24 | ths | s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
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721 | 80b3ada7 | pbrook | devfn, NULL, pci_bridge_write_config);
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722 | 80b3ada7 | pbrook | s->dev.config[0x00] = id >> 16; |
723 | 451a4212 | ths | s->dev.config[0x01] = id >> 24; |
724 | 80b3ada7 | pbrook | s->dev.config[0x02] = id; // device_id |
725 | 80b3ada7 | pbrook | s->dev.config[0x03] = id >> 8; |
726 | 80b3ada7 | pbrook | s->dev.config[0x04] = 0x06; // command = bus master, pci mem |
727 | 80b3ada7 | pbrook | s->dev.config[0x05] = 0x00; |
728 | 80b3ada7 | pbrook | s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error |
729 | 80b3ada7 | pbrook | s->dev.config[0x07] = 0x00; // status = fast devsel |
730 | 80b3ada7 | pbrook | s->dev.config[0x08] = 0x00; // revision |
731 | 80b3ada7 | pbrook | s->dev.config[0x09] = 0x00; // programming i/f |
732 | 80b3ada7 | pbrook | s->dev.config[0x0A] = 0x04; // class_sub = PCI to PCI bridge |
733 | 80b3ada7 | pbrook | s->dev.config[0x0B] = 0x06; // class_base = PCI_bridge |
734 | 80b3ada7 | pbrook | s->dev.config[0x0D] = 0x10; // latency_timer |
735 | 80b3ada7 | pbrook | s->dev.config[0x0E] = 0x81; // header_type |
736 | 80b3ada7 | pbrook | s->dev.config[0x1E] = 0xa0; // secondary status |
737 | 80b3ada7 | pbrook | |
738 | 80b3ada7 | pbrook | s->bus = pci_register_secondary_bus(&s->dev, map_irq); |
739 | 80b3ada7 | pbrook | return s->bus;
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740 | 80b3ada7 | pbrook | } |