root / hw / pci_bridge.c @ cde844fa
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1 | 783753fd | Isaku Yamahata | /*
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2 | 783753fd | Isaku Yamahata | * QEMU PCI bus manager
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3 | 783753fd | Isaku Yamahata | *
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4 | 783753fd | Isaku Yamahata | * Copyright (c) 2004 Fabrice Bellard
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5 | 783753fd | Isaku Yamahata | *
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6 | 783753fd | Isaku Yamahata | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 783753fd | Isaku Yamahata | * of this software and associated documentation files (the "Software"), to dea
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8 | 783753fd | Isaku Yamahata | |
9 | 783753fd | Isaku Yamahata | * in the Software without restriction, including without limitation the rights
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10 | 783753fd | Isaku Yamahata | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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11 | 783753fd | Isaku Yamahata | * copies of the Software, and to permit persons to whom the Software is
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12 | 783753fd | Isaku Yamahata | * furnished to do so, subject to the following conditions:
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13 | 783753fd | Isaku Yamahata | *
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14 | 783753fd | Isaku Yamahata | * The above copyright notice and this permission notice shall be included in
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15 | 783753fd | Isaku Yamahata | * all copies or substantial portions of the Software.
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16 | 783753fd | Isaku Yamahata | *
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17 | 783753fd | Isaku Yamahata | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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18 | 783753fd | Isaku Yamahata | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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19 | 783753fd | Isaku Yamahata | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 | 783753fd | Isaku Yamahata | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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21 | 783753fd | Isaku Yamahata | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM
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22 | 783753fd | Isaku Yamahata | |
23 | 783753fd | Isaku Yamahata | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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24 | 783753fd | Isaku Yamahata | * THE SOFTWARE.
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25 | 783753fd | Isaku Yamahata | */
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26 | 783753fd | Isaku Yamahata | /*
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27 | 783753fd | Isaku Yamahata | * split out from pci.c
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28 | 783753fd | Isaku Yamahata | * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
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29 | 783753fd | Isaku Yamahata | * VA Linux Systems Japan K.K.
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30 | 783753fd | Isaku Yamahata | */
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31 | 783753fd | Isaku Yamahata | |
32 | 783753fd | Isaku Yamahata | #include "pci_bridge.h" |
33 | 783753fd | Isaku Yamahata | #include "pci_internals.h" |
34 | 5afb9869 | Blue Swirl | #include "range.h" |
35 | 783753fd | Isaku Yamahata | |
36 | f4c817e0 | Isaku Yamahata | /* PCI bridge subsystem vendor ID helper functions */
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37 | f4c817e0 | Isaku Yamahata | #define PCI_SSVID_SIZEOF 8 |
38 | f4c817e0 | Isaku Yamahata | #define PCI_SSVID_SVID 4 |
39 | f4c817e0 | Isaku Yamahata | #define PCI_SSVID_SSID 6 |
40 | f4c817e0 | Isaku Yamahata | |
41 | f4c817e0 | Isaku Yamahata | int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset,
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42 | f4c817e0 | Isaku Yamahata | uint16_t svid, uint16_t ssid) |
43 | f4c817e0 | Isaku Yamahata | { |
44 | f4c817e0 | Isaku Yamahata | int pos;
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45 | f4c817e0 | Isaku Yamahata | pos = pci_add_capability(dev, PCI_CAP_ID_SSVID, offset, PCI_SSVID_SIZEOF); |
46 | f4c817e0 | Isaku Yamahata | if (pos < 0) { |
47 | f4c817e0 | Isaku Yamahata | return pos;
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48 | f4c817e0 | Isaku Yamahata | } |
49 | f4c817e0 | Isaku Yamahata | |
50 | f4c817e0 | Isaku Yamahata | pci_set_word(dev->config + pos + PCI_SSVID_SVID, svid); |
51 | f4c817e0 | Isaku Yamahata | pci_set_word(dev->config + pos + PCI_SSVID_SSID, ssid); |
52 | f4c817e0 | Isaku Yamahata | return pos;
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53 | f4c817e0 | Isaku Yamahata | } |
54 | f4c817e0 | Isaku Yamahata | |
55 | 68f79994 | Isaku Yamahata | /* Accessor function to get parent bridge device from pci bus. */
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56 | 783753fd | Isaku Yamahata | PCIDevice *pci_bridge_get_device(PCIBus *bus) |
57 | 783753fd | Isaku Yamahata | { |
58 | 783753fd | Isaku Yamahata | return bus->parent_dev;
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59 | 783753fd | Isaku Yamahata | } |
60 | 783753fd | Isaku Yamahata | |
61 | 68f79994 | Isaku Yamahata | /* Accessor function to get secondary bus from pci-to-pci bridge device */
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62 | 68f79994 | Isaku Yamahata | PCIBus *pci_bridge_get_sec_bus(PCIBridge *br) |
63 | 68f79994 | Isaku Yamahata | { |
64 | 68f79994 | Isaku Yamahata | return &br->sec_bus;
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65 | 68f79994 | Isaku Yamahata | } |
66 | 68f79994 | Isaku Yamahata | |
67 | 68f79994 | Isaku Yamahata | static uint32_t pci_config_get_io_base(const PCIDevice *d, |
68 | 783753fd | Isaku Yamahata | uint32_t base, uint32_t base_upper16) |
69 | 783753fd | Isaku Yamahata | { |
70 | 783753fd | Isaku Yamahata | uint32_t val; |
71 | 783753fd | Isaku Yamahata | |
72 | 783753fd | Isaku Yamahata | val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8;
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73 | 783753fd | Isaku Yamahata | if (d->config[base] & PCI_IO_RANGE_TYPE_32) {
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74 | 783753fd | Isaku Yamahata | val |= (uint32_t)pci_get_word(d->config + base_upper16) << 16;
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75 | 783753fd | Isaku Yamahata | } |
76 | 783753fd | Isaku Yamahata | return val;
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77 | 783753fd | Isaku Yamahata | } |
78 | 783753fd | Isaku Yamahata | |
79 | 68f79994 | Isaku Yamahata | static pcibus_t pci_config_get_memory_base(const PCIDevice *d, uint32_t base) |
80 | 783753fd | Isaku Yamahata | { |
81 | 783753fd | Isaku Yamahata | return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
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82 | 783753fd | Isaku Yamahata | << 16;
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83 | 783753fd | Isaku Yamahata | } |
84 | 783753fd | Isaku Yamahata | |
85 | 68f79994 | Isaku Yamahata | static pcibus_t pci_config_get_pref_base(const PCIDevice *d, |
86 | 783753fd | Isaku Yamahata | uint32_t base, uint32_t upper) |
87 | 783753fd | Isaku Yamahata | { |
88 | 783753fd | Isaku Yamahata | pcibus_t tmp; |
89 | 783753fd | Isaku Yamahata | pcibus_t val; |
90 | 783753fd | Isaku Yamahata | |
91 | 783753fd | Isaku Yamahata | tmp = (pcibus_t)pci_get_word(d->config + base); |
92 | 783753fd | Isaku Yamahata | val = (tmp & PCI_PREF_RANGE_MASK) << 16;
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93 | 783753fd | Isaku Yamahata | if (tmp & PCI_PREF_RANGE_TYPE_64) {
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94 | 783753fd | Isaku Yamahata | val |= (pcibus_t)pci_get_long(d->config + upper) << 32;
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95 | 783753fd | Isaku Yamahata | } |
96 | 783753fd | Isaku Yamahata | return val;
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97 | 783753fd | Isaku Yamahata | } |
98 | 783753fd | Isaku Yamahata | |
99 | 68f79994 | Isaku Yamahata | /* accessor function to get bridge filtering base address */
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100 | 68f79994 | Isaku Yamahata | pcibus_t pci_bridge_get_base(const PCIDevice *bridge, uint8_t type)
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101 | 783753fd | Isaku Yamahata | { |
102 | 783753fd | Isaku Yamahata | pcibus_t base; |
103 | 783753fd | Isaku Yamahata | if (type & PCI_BASE_ADDRESS_SPACE_IO) {
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104 | 783753fd | Isaku Yamahata | base = pci_config_get_io_base(bridge, |
105 | 783753fd | Isaku Yamahata | PCI_IO_BASE, PCI_IO_BASE_UPPER16); |
106 | 783753fd | Isaku Yamahata | } else {
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107 | 783753fd | Isaku Yamahata | if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
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108 | 783753fd | Isaku Yamahata | base = pci_config_get_pref_base( |
109 | 783753fd | Isaku Yamahata | bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32); |
110 | 783753fd | Isaku Yamahata | } else {
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111 | 783753fd | Isaku Yamahata | base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE); |
112 | 783753fd | Isaku Yamahata | } |
113 | 783753fd | Isaku Yamahata | } |
114 | 783753fd | Isaku Yamahata | |
115 | 783753fd | Isaku Yamahata | return base;
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116 | 783753fd | Isaku Yamahata | } |
117 | 783753fd | Isaku Yamahata | |
118 | 68f79994 | Isaku Yamahata | /* accessor funciton to get bridge filtering limit */
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119 | 68f79994 | Isaku Yamahata | pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type)
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120 | 783753fd | Isaku Yamahata | { |
121 | 783753fd | Isaku Yamahata | pcibus_t limit; |
122 | 783753fd | Isaku Yamahata | if (type & PCI_BASE_ADDRESS_SPACE_IO) {
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123 | 783753fd | Isaku Yamahata | limit = pci_config_get_io_base(bridge, |
124 | 783753fd | Isaku Yamahata | PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16); |
125 | 783753fd | Isaku Yamahata | limit |= 0xfff; /* PCI bridge spec 3.2.5.6. */ |
126 | 783753fd | Isaku Yamahata | } else {
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127 | 783753fd | Isaku Yamahata | if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
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128 | 783753fd | Isaku Yamahata | limit = pci_config_get_pref_base( |
129 | 783753fd | Isaku Yamahata | bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32); |
130 | 783753fd | Isaku Yamahata | } else {
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131 | 783753fd | Isaku Yamahata | limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT); |
132 | 783753fd | Isaku Yamahata | } |
133 | 783753fd | Isaku Yamahata | limit |= 0xfffff; /* PCI bridge spec 3.2.5.{1, 8}. */ |
134 | 783753fd | Isaku Yamahata | } |
135 | 783753fd | Isaku Yamahata | return limit;
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136 | 783753fd | Isaku Yamahata | } |
137 | 783753fd | Isaku Yamahata | |
138 | 7df32ca0 | Michael S. Tsirkin | static void pci_bridge_init_alias(PCIBridge *bridge, MemoryRegion *alias, |
139 | 7df32ca0 | Michael S. Tsirkin | uint8_t type, const char *name, |
140 | 7df32ca0 | Michael S. Tsirkin | MemoryRegion *space, |
141 | 7df32ca0 | Michael S. Tsirkin | MemoryRegion *parent_space, |
142 | 7df32ca0 | Michael S. Tsirkin | bool enabled)
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143 | 7df32ca0 | Michael S. Tsirkin | { |
144 | 7df32ca0 | Michael S. Tsirkin | pcibus_t base = pci_bridge_get_base(&bridge->dev, type); |
145 | 7df32ca0 | Michael S. Tsirkin | pcibus_t limit = pci_bridge_get_limit(&bridge->dev, type); |
146 | 7df32ca0 | Michael S. Tsirkin | /* TODO: this doesn't handle base = 0 limit = 2^64 - 1 correctly.
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147 | 7df32ca0 | Michael S. Tsirkin | * Apparently no way to do this with existing memory APIs. */
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148 | 7df32ca0 | Michael S. Tsirkin | pcibus_t size = enabled && limit >= base ? limit + 1 - base : 0; |
149 | 7df32ca0 | Michael S. Tsirkin | |
150 | 7df32ca0 | Michael S. Tsirkin | memory_region_init_alias(alias, name, space, base, size); |
151 | 7df32ca0 | Michael S. Tsirkin | memory_region_add_subregion_overlap(parent_space, base, alias, 1);
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152 | 7df32ca0 | Michael S. Tsirkin | } |
153 | 7df32ca0 | Michael S. Tsirkin | |
154 | 7df32ca0 | Michael S. Tsirkin | static void pci_bridge_cleanup_alias(MemoryRegion *alias, |
155 | 7df32ca0 | Michael S. Tsirkin | MemoryRegion *parent_space) |
156 | 7df32ca0 | Michael S. Tsirkin | { |
157 | 7df32ca0 | Michael S. Tsirkin | memory_region_del_subregion(parent_space, alias); |
158 | 7df32ca0 | Michael S. Tsirkin | memory_region_destroy(alias); |
159 | 7df32ca0 | Michael S. Tsirkin | } |
160 | 7df32ca0 | Michael S. Tsirkin | |
161 | 7df32ca0 | Michael S. Tsirkin | static void pci_bridge_region_init(PCIBridge *br) |
162 | 7df32ca0 | Michael S. Tsirkin | { |
163 | 7df32ca0 | Michael S. Tsirkin | PCIBus *parent = br->dev.bus; |
164 | 7df32ca0 | Michael S. Tsirkin | uint16_t cmd = pci_get_word(br->dev.config + PCI_COMMAND); |
165 | 7df32ca0 | Michael S. Tsirkin | |
166 | 7df32ca0 | Michael S. Tsirkin | pci_bridge_init_alias(br, &br->alias_pref_mem, |
167 | 7df32ca0 | Michael S. Tsirkin | PCI_BASE_ADDRESS_MEM_PREFETCH, |
168 | 7df32ca0 | Michael S. Tsirkin | "pci_bridge_pref_mem",
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169 | 336411ca | Michael S. Tsirkin | &br->address_space_mem, |
170 | 7df32ca0 | Michael S. Tsirkin | parent->address_space_mem, |
171 | 7df32ca0 | Michael S. Tsirkin | cmd & PCI_COMMAND_MEMORY); |
172 | 7df32ca0 | Michael S. Tsirkin | pci_bridge_init_alias(br, &br->alias_mem, |
173 | 7df32ca0 | Michael S. Tsirkin | PCI_BASE_ADDRESS_SPACE_MEMORY, |
174 | 7df32ca0 | Michael S. Tsirkin | "pci_bridge_mem",
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175 | 336411ca | Michael S. Tsirkin | &br->address_space_mem, |
176 | 7df32ca0 | Michael S. Tsirkin | parent->address_space_mem, |
177 | 7df32ca0 | Michael S. Tsirkin | cmd & PCI_COMMAND_MEMORY); |
178 | 7df32ca0 | Michael S. Tsirkin | pci_bridge_init_alias(br, &br->alias_io, |
179 | 7df32ca0 | Michael S. Tsirkin | PCI_BASE_ADDRESS_SPACE_IO, |
180 | 7df32ca0 | Michael S. Tsirkin | "pci_bridge_io",
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181 | 336411ca | Michael S. Tsirkin | &br->address_space_io, |
182 | 7df32ca0 | Michael S. Tsirkin | parent->address_space_io, |
183 | 7df32ca0 | Michael S. Tsirkin | cmd & PCI_COMMAND_IO); |
184 | 7df32ca0 | Michael S. Tsirkin | /* TODO: optinal VGA and VGA palette snooping support. */
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185 | 7df32ca0 | Michael S. Tsirkin | } |
186 | 7df32ca0 | Michael S. Tsirkin | |
187 | 7df32ca0 | Michael S. Tsirkin | static void pci_bridge_region_cleanup(PCIBridge *br) |
188 | 7df32ca0 | Michael S. Tsirkin | { |
189 | 7df32ca0 | Michael S. Tsirkin | PCIBus *parent = br->dev.bus; |
190 | 7df32ca0 | Michael S. Tsirkin | pci_bridge_cleanup_alias(&br->alias_io, |
191 | 7df32ca0 | Michael S. Tsirkin | parent->address_space_io); |
192 | 7df32ca0 | Michael S. Tsirkin | pci_bridge_cleanup_alias(&br->alias_mem, |
193 | 7df32ca0 | Michael S. Tsirkin | parent->address_space_mem); |
194 | 7df32ca0 | Michael S. Tsirkin | pci_bridge_cleanup_alias(&br->alias_pref_mem, |
195 | 7df32ca0 | Michael S. Tsirkin | parent->address_space_mem); |
196 | 7df32ca0 | Michael S. Tsirkin | } |
197 | 7df32ca0 | Michael S. Tsirkin | |
198 | 7df32ca0 | Michael S. Tsirkin | static void pci_bridge_update_mappings(PCIBridge *br) |
199 | 7df32ca0 | Michael S. Tsirkin | { |
200 | 7df32ca0 | Michael S. Tsirkin | /* Make updates atomic to: handle the case of one VCPU updating the bridge
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201 | 7df32ca0 | Michael S. Tsirkin | * while another accesses an unaffected region. */
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202 | 7df32ca0 | Michael S. Tsirkin | memory_region_transaction_begin(); |
203 | 7df32ca0 | Michael S. Tsirkin | pci_bridge_region_cleanup(br); |
204 | 7df32ca0 | Michael S. Tsirkin | pci_bridge_region_init(br); |
205 | 7df32ca0 | Michael S. Tsirkin | memory_region_transaction_commit(); |
206 | 7df32ca0 | Michael S. Tsirkin | } |
207 | 7df32ca0 | Michael S. Tsirkin | |
208 | 68f79994 | Isaku Yamahata | /* default write_config function for PCI-to-PCI bridge */
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209 | 68f79994 | Isaku Yamahata | void pci_bridge_write_config(PCIDevice *d,
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210 | 783753fd | Isaku Yamahata | uint32_t address, uint32_t val, int len)
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211 | 783753fd | Isaku Yamahata | { |
212 | a5fce077 | Isaku Yamahata | PCIBridge *s = container_of(d, PCIBridge, dev); |
213 | a5fce077 | Isaku Yamahata | uint16_t oldctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL); |
214 | a5fce077 | Isaku Yamahata | uint16_t newctl; |
215 | a5fce077 | Isaku Yamahata | |
216 | 783753fd | Isaku Yamahata | pci_default_write_config(d, address, val, len); |
217 | 783753fd | Isaku Yamahata | |
218 | 7df32ca0 | Michael S. Tsirkin | if (ranges_overlap(address, len, PCI_COMMAND, 2) || |
219 | 7df32ca0 | Michael S. Tsirkin | |
220 | 7df32ca0 | Michael S. Tsirkin | /* io base/limit */
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221 | 783753fd | Isaku Yamahata | ranges_overlap(address, len, PCI_IO_BASE, 2) ||
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222 | 783753fd | Isaku Yamahata | |
223 | 783753fd | Isaku Yamahata | /* memory base/limit, prefetchable base/limit and
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224 | 783753fd | Isaku Yamahata | io base/limit upper 16 */
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225 | 783753fd | Isaku Yamahata | ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) {
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226 | 7df32ca0 | Michael S. Tsirkin | pci_bridge_update_mappings(s); |
227 | 783753fd | Isaku Yamahata | } |
228 | a5fce077 | Isaku Yamahata | |
229 | a5fce077 | Isaku Yamahata | newctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL); |
230 | a5fce077 | Isaku Yamahata | if (~oldctl & newctl & PCI_BRIDGE_CTL_BUS_RESET) {
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231 | a5fce077 | Isaku Yamahata | /* Trigger hot reset on 0->1 transition. */
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232 | a5fce077 | Isaku Yamahata | pci_bus_reset(&s->sec_bus); |
233 | a5fce077 | Isaku Yamahata | } |
234 | 783753fd | Isaku Yamahata | } |
235 | 783753fd | Isaku Yamahata | |
236 | 0208def1 | Isaku Yamahata | void pci_bridge_disable_base_limit(PCIDevice *dev)
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237 | 0208def1 | Isaku Yamahata | { |
238 | 0208def1 | Isaku Yamahata | uint8_t *conf = dev->config; |
239 | 0208def1 | Isaku Yamahata | |
240 | 0208def1 | Isaku Yamahata | pci_byte_test_and_set_mask(conf + PCI_IO_BASE, |
241 | 0208def1 | Isaku Yamahata | PCI_IO_RANGE_MASK & 0xff);
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242 | 0208def1 | Isaku Yamahata | pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT, |
243 | 0208def1 | Isaku Yamahata | PCI_IO_RANGE_MASK & 0xff);
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244 | 0208def1 | Isaku Yamahata | pci_word_test_and_set_mask(conf + PCI_MEMORY_BASE, |
245 | 0208def1 | Isaku Yamahata | PCI_MEMORY_RANGE_MASK & 0xffff);
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246 | 0208def1 | Isaku Yamahata | pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT, |
247 | 0208def1 | Isaku Yamahata | PCI_MEMORY_RANGE_MASK & 0xffff);
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248 | 0208def1 | Isaku Yamahata | pci_word_test_and_set_mask(conf + PCI_PREF_MEMORY_BASE, |
249 | 0208def1 | Isaku Yamahata | PCI_PREF_RANGE_MASK & 0xffff);
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250 | 0208def1 | Isaku Yamahata | pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT, |
251 | 0208def1 | Isaku Yamahata | PCI_PREF_RANGE_MASK & 0xffff);
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252 | 0208def1 | Isaku Yamahata | pci_set_word(conf + PCI_PREF_BASE_UPPER32, 0);
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253 | 0208def1 | Isaku Yamahata | pci_set_word(conf + PCI_PREF_LIMIT_UPPER32, 0);
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254 | 0208def1 | Isaku Yamahata | } |
255 | 0208def1 | Isaku Yamahata | |
256 | 68f79994 | Isaku Yamahata | /* reset bridge specific configuration registers */
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257 | 68f79994 | Isaku Yamahata | void pci_bridge_reset_reg(PCIDevice *dev)
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258 | 68f79994 | Isaku Yamahata | { |
259 | 68f79994 | Isaku Yamahata | uint8_t *conf = dev->config; |
260 | 68f79994 | Isaku Yamahata | |
261 | 68f79994 | Isaku Yamahata | conf[PCI_PRIMARY_BUS] = 0;
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262 | 68f79994 | Isaku Yamahata | conf[PCI_SECONDARY_BUS] = 0;
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263 | 68f79994 | Isaku Yamahata | conf[PCI_SUBORDINATE_BUS] = 0;
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264 | 68f79994 | Isaku Yamahata | conf[PCI_SEC_LATENCY_TIMER] = 0;
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265 | 68f79994 | Isaku Yamahata | |
266 | 0208def1 | Isaku Yamahata | /*
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267 | 0208def1 | Isaku Yamahata | * the default values for base/limit registers aren't specified
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268 | 0208def1 | Isaku Yamahata | * in the PCI-to-PCI-bridge spec. So we don't thouch them here.
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269 | 0208def1 | Isaku Yamahata | * Each implementation can override it.
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270 | 0208def1 | Isaku Yamahata | * typical implementation does
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271 | 0208def1 | Isaku Yamahata | * zero base/limit registers or
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272 | 0208def1 | Isaku Yamahata | * disable forwarding: pci_bridge_disable_base_limit()
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273 | 0208def1 | Isaku Yamahata | * If disable forwarding is wanted, call pci_bridge_disable_base_limit()
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274 | 0208def1 | Isaku Yamahata | * after this function.
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275 | 0208def1 | Isaku Yamahata | */
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276 | 0208def1 | Isaku Yamahata | pci_byte_test_and_clear_mask(conf + PCI_IO_BASE, |
277 | 0208def1 | Isaku Yamahata | PCI_IO_RANGE_MASK & 0xff);
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278 | 0208def1 | Isaku Yamahata | pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT, |
279 | 0208def1 | Isaku Yamahata | PCI_IO_RANGE_MASK & 0xff);
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280 | 0208def1 | Isaku Yamahata | pci_word_test_and_clear_mask(conf + PCI_MEMORY_BASE, |
281 | 0208def1 | Isaku Yamahata | PCI_MEMORY_RANGE_MASK & 0xffff);
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282 | 0208def1 | Isaku Yamahata | pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT, |
283 | 0208def1 | Isaku Yamahata | PCI_MEMORY_RANGE_MASK & 0xffff);
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284 | 0208def1 | Isaku Yamahata | pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_BASE, |
285 | 0208def1 | Isaku Yamahata | PCI_PREF_RANGE_MASK & 0xffff);
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286 | 0208def1 | Isaku Yamahata | pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT, |
287 | 0208def1 | Isaku Yamahata | PCI_PREF_RANGE_MASK & 0xffff);
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288 | 68f79994 | Isaku Yamahata | pci_set_word(conf + PCI_PREF_BASE_UPPER32, 0);
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289 | 68f79994 | Isaku Yamahata | pci_set_word(conf + PCI_PREF_LIMIT_UPPER32, 0);
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290 | 68f79994 | Isaku Yamahata | |
291 | 68f79994 | Isaku Yamahata | pci_set_word(conf + PCI_BRIDGE_CONTROL, 0);
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292 | 68f79994 | Isaku Yamahata | } |
293 | 68f79994 | Isaku Yamahata | |
294 | 68f79994 | Isaku Yamahata | /* default reset function for PCI-to-PCI bridge */
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295 | 68f79994 | Isaku Yamahata | void pci_bridge_reset(DeviceState *qdev)
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296 | 783753fd | Isaku Yamahata | { |
297 | 68f79994 | Isaku Yamahata | PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev); |
298 | 68f79994 | Isaku Yamahata | pci_bridge_reset_reg(dev); |
299 | 68f79994 | Isaku Yamahata | } |
300 | 783753fd | Isaku Yamahata | |
301 | 68f79994 | Isaku Yamahata | /* default qdev initialization function for PCI-to-PCI bridge */
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302 | 68f79994 | Isaku Yamahata | int pci_bridge_initfn(PCIDevice *dev)
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303 | 68f79994 | Isaku Yamahata | { |
304 | 68f79994 | Isaku Yamahata | PCIBus *parent = dev->bus; |
305 | 68f79994 | Isaku Yamahata | PCIBridge *br = DO_UPCAST(PCIBridge, dev, dev); |
306 | 68f79994 | Isaku Yamahata | PCIBus *sec_bus = &br->sec_bus; |
307 | 783753fd | Isaku Yamahata | |
308 | 783753fd | Isaku Yamahata | pci_set_word(dev->config + PCI_STATUS, |
309 | 783753fd | Isaku Yamahata | PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK); |
310 | 783753fd | Isaku Yamahata | pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI); |
311 | 783753fd | Isaku Yamahata | dev->config[PCI_HEADER_TYPE] = |
312 | 783753fd | Isaku Yamahata | (dev->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) | |
313 | 783753fd | Isaku Yamahata | PCI_HEADER_TYPE_BRIDGE; |
314 | 783753fd | Isaku Yamahata | pci_set_word(dev->config + PCI_SEC_STATUS, |
315 | 783753fd | Isaku Yamahata | PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK); |
316 | 68f79994 | Isaku Yamahata | |
317 | 68f79994 | Isaku Yamahata | qbus_create_inplace(&sec_bus->qbus, &pci_bus_info, &dev->qdev, |
318 | 68f79994 | Isaku Yamahata | br->bus_name); |
319 | 68f79994 | Isaku Yamahata | sec_bus->parent_dev = dev; |
320 | 68f79994 | Isaku Yamahata | sec_bus->map_irq = br->map_irq; |
321 | 336411ca | Michael S. Tsirkin | sec_bus->address_space_mem = &br->address_space_mem; |
322 | 52ce6f05 | Blue Swirl | memory_region_init(&br->address_space_mem, "pci_bridge_pci", INT64_MAX);
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323 | 336411ca | Michael S. Tsirkin | sec_bus->address_space_io = &br->address_space_io; |
324 | 336411ca | Michael S. Tsirkin | memory_region_init(&br->address_space_io, "pci_bridge_io", 65536); |
325 | 7df32ca0 | Michael S. Tsirkin | pci_bridge_region_init(br); |
326 | 68f79994 | Isaku Yamahata | QLIST_INIT(&sec_bus->child); |
327 | 68f79994 | Isaku Yamahata | QLIST_INSERT_HEAD(&parent->child, sec_bus, sibling); |
328 | 783753fd | Isaku Yamahata | return 0; |
329 | 783753fd | Isaku Yamahata | } |
330 | 783753fd | Isaku Yamahata | |
331 | 68f79994 | Isaku Yamahata | /* default qdev clean up function for PCI-to-PCI bridge */
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332 | 68f79994 | Isaku Yamahata | int pci_bridge_exitfn(PCIDevice *pci_dev)
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333 | 783753fd | Isaku Yamahata | { |
334 | 783753fd | Isaku Yamahata | PCIBridge *s = DO_UPCAST(PCIBridge, dev, pci_dev); |
335 | 51a92333 | Isaku Yamahata | assert(QLIST_EMPTY(&s->sec_bus.child)); |
336 | 51a92333 | Isaku Yamahata | QLIST_REMOVE(&s->sec_bus, sibling); |
337 | 7df32ca0 | Michael S. Tsirkin | pci_bridge_region_cleanup(s); |
338 | 336411ca | Michael S. Tsirkin | memory_region_destroy(&s->address_space_mem); |
339 | 336411ca | Michael S. Tsirkin | memory_region_destroy(&s->address_space_io); |
340 | 68f79994 | Isaku Yamahata | /* qbus_free() is called automatically by qdev_free() */
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341 | 783753fd | Isaku Yamahata | return 0; |
342 | 783753fd | Isaku Yamahata | } |
343 | 783753fd | Isaku Yamahata | |
344 | 68f79994 | Isaku Yamahata | /*
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345 | 68f79994 | Isaku Yamahata | * before qdev initialization(qdev_init()), this function sets bus_name and
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346 | 68f79994 | Isaku Yamahata | * map_irq callback which are necessry for pci_bridge_initfn() to
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347 | 68f79994 | Isaku Yamahata | * initialize bus.
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348 | 68f79994 | Isaku Yamahata | */
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349 | 68f79994 | Isaku Yamahata | void pci_bridge_map_irq(PCIBridge *br, const char* bus_name, |
350 | 68f79994 | Isaku Yamahata | pci_map_irq_fn map_irq) |
351 | 783753fd | Isaku Yamahata | { |
352 | 68f79994 | Isaku Yamahata | br->map_irq = map_irq; |
353 | 68f79994 | Isaku Yamahata | br->bus_name = bus_name; |
354 | 783753fd | Isaku Yamahata | } |