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hw/omap_gpmc.c: Add missing 'break's to fix 8 bit NAND writes
Add missing 'break' statements which would have meant that writingto an 8 bit NAND device was broken. Spotted by Coverity (see bug887883).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
hw/omap_gpmc: Modify correct field when writing IRQSTATUS register
Writing to IRQSTATUS should affect irqst, not irqen -- errorspotted by Andrzej Zaborowski.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
hw/omap_gpmc: Add comment about FIFOTHRESHOLDSTATUS bit
Promote the remark about why we handle FIFOTHRESHOLDSTATUS theway we do from the commit message of de8af7fe0 to a comment inthe code.
omap_gpmc: Accept a zero mask field on omap3630
OMAP3630 adds an extra bit of address masking, so a mask of0xb1111 is valid. Unfortunately the GPMC_REVISION is the same ason the OMAP3430 which only has three bits of address masking, sowe have to derive this feature directly from the OMAP revision...
omap_gpmc: Pull prefetch engine data into sub-struct
Refactor the gpmc state structure so items relating tothe prefetch engine are in their own sub-struct and havemore useful names.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
omap: Wire up the DMA request line to the GPMC
omap_gpmc: Implement prefetch engine
This commit implements the prefetch engine feature of the GPMCwhich can be used for NAND devices. This includes both interruptdriven and DMA-filling modes.
omap_gpmc: Clean up omap_gpmc_attach MemoryRegion conversion
Now that all callers of omap_gpmc_attach pass in a MemoryRegion*,we can remove the base_update and unmap function pointer arguments,and the opaque pointer that was passed into these callbacks....
omap_gpmc: Refactor omap_gpmc_cs_map and omap_gpmc_cs_unmap
Refactor the omap_gpmc_cs_map/unmap functions: * take the omap_gpmc_s* and a chipselect id rather than the omap_gpmc_cs_file_s*, so they have access to the general gpmc member fields * extract the base and mask from the config registers in the functions...
omap_gpmc: GPMC_IRQSTATUS is write-one-to-clear
Fix a bug in the handling of writes to GPMC_IRQSTATUS:it behaves as "write one to clear, writing zero is ignored".
omap_gpmc: Wire up the GPMC IRQ correctly
The omap_gpmc wasn't actually wiring up its IRQ, soanything that provoked an interrupt would be usinguninitialised data for its IRQ number.
omap_gpmc: Fix handling of FIFOTHRESHOLDSTATUS bit
The OMAP3 TRM is inconsistent about whether the GPMC FIFOTHRESHOLDSTATUSbit should be set when FIFOPOINTER > FIFOTHRESHOLD or when it is >=FIFOTHRESHOLD. Apparently the underlying functional spec from which...
omap_gpmc: Take omap_mpu_state* in omap_gpmc_init
Take a pointer to the omap mpu state struct in omap_gpmc_init.Some details of GPMC behaviour depend on the OMAP version weare a part of.
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>[Riku Voipio: Fixes and restructuring patchset]...
omap_gpmc: Calculate revision from OMAP model
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>[Riku Voipio: Fixes and restructuring patchset]Signed-off-by: Riku Voipio <riku.voipio@iki.fi>[Peter Maydell: More fixes and cleanups for upstream submission]...
omap_gpmc: Reindent misindented switch statements
Whitespace-only change fixing indentation.
omap_gpmc: Support NAND devices
Support accesses to NAND devices, both by mapping them intothe GPMC address space, and via the NAND_COMMAND, NAND_ADDRESSand NAND_DATA GPMC registers.
hw/omap_gpmc: Don't try to map CS0 twice on reset
Remove a spurious second map of the OMAP GPMC CS0 region on reset.This fixes an assertion failure when we try to add the region toits container when it was already added. (The old code did notcomplain about mismatched map/unmap calls, but the new MemoryRegion...
omap_gpmc/nseries/tusb6010: convert to memory API
Somewhat clumsy since it needs a variable sized region.
Signed-off-by: Avi Kivity <avi@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Use glib memory allocation and free functions
qemu_malloc/qemu_free no longer exist after this commit.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Add endianness as io mem parameter
As stated before, devices can be little, big or native endian. Thetarget endianness is not of their concern, so we need to push thingsdown a level.
This patch adds a parameter to cpu_register_io_memory that allows adevice to choose its endianness. For now, all devices simply choose...
hw/omap2.c : separate gpmc(general purpose memory controller)
Signed-off-by: cmchao <cmchao@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>