root / target-ppc / helper.c @ d12d51d5
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1 | 79aceca5 | bellard | /*
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2 | 3fc6c082 | bellard | * PowerPC emulation helpers for qemu.
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3 | 5fafdf24 | ths | *
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4 | 76a66253 | j_mayer | * Copyright (c) 2003-2007 Jocelyn Mayer
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5 | 79aceca5 | bellard | *
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6 | 79aceca5 | bellard | * This library is free software; you can redistribute it and/or
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7 | 79aceca5 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 79aceca5 | bellard | * License as published by the Free Software Foundation; either
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9 | 79aceca5 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 79aceca5 | bellard | *
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11 | 79aceca5 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 79aceca5 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 79aceca5 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 79aceca5 | bellard | * Lesser General Public License for more details.
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15 | 79aceca5 | bellard | *
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16 | 79aceca5 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 79aceca5 | bellard | * License along with this library; if not, write to the Free Software
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18 | fad6cb1a | aurel32 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
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19 | 79aceca5 | bellard | */
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20 | fdabc366 | bellard | #include <stdarg.h> |
21 | fdabc366 | bellard | #include <stdlib.h> |
22 | fdabc366 | bellard | #include <stdio.h> |
23 | fdabc366 | bellard | #include <string.h> |
24 | fdabc366 | bellard | #include <inttypes.h> |
25 | fdabc366 | bellard | #include <signal.h> |
26 | fdabc366 | bellard | #include <assert.h> |
27 | fdabc366 | bellard | |
28 | fdabc366 | bellard | #include "cpu.h" |
29 | fdabc366 | bellard | #include "exec-all.h" |
30 | 0411a972 | j_mayer | #include "helper_regs.h" |
31 | ca10f867 | aurel32 | #include "qemu-common.h" |
32 | d76d1650 | aurel32 | #include "kvm.h" |
33 | 9a64fbe4 | bellard | |
34 | 9a64fbe4 | bellard | //#define DEBUG_MMU
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35 | 9a64fbe4 | bellard | //#define DEBUG_BATS
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36 | 6b542af7 | j_mayer | //#define DEBUG_SLB
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37 | 76a66253 | j_mayer | //#define DEBUG_SOFTWARE_TLB
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38 | 0411a972 | j_mayer | //#define DUMP_PAGE_TABLES
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39 | 9a64fbe4 | bellard | //#define DEBUG_EXCEPTIONS
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40 | fdabc366 | bellard | //#define FLUSH_ALL_TLBS
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41 | 9a64fbe4 | bellard | |
42 | d12d51d5 | aliguori | #ifdef DEBUG_MMU
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43 | d12d51d5 | aliguori | # define LOG_MMU(...) do { \ |
44 | d12d51d5 | aliguori | if (loglevel) \
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45 | d12d51d5 | aliguori | fprintf(logfile, ## __VA_ARGS__); \ |
46 | d12d51d5 | aliguori | } while (0) |
47 | d12d51d5 | aliguori | # define LOG_MMU_STATE(env) do { \ |
48 | d12d51d5 | aliguori | if (loglevel) \
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49 | d12d51d5 | aliguori | cpu_dump_state(env, logfile, fprintf, 0); \
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50 | d12d51d5 | aliguori | } while (0) |
51 | d12d51d5 | aliguori | #else
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52 | d12d51d5 | aliguori | # define LOG_MMU(...) do { } while (0) |
53 | d12d51d5 | aliguori | # define LOG_MMU_STATE(...) do { } while (0) |
54 | d12d51d5 | aliguori | #endif
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55 | d12d51d5 | aliguori | |
56 | d12d51d5 | aliguori | |
57 | d12d51d5 | aliguori | #ifdef DEBUG_SOFTWARE_TLB
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58 | d12d51d5 | aliguori | # define LOG_SWTLB(...) do { \ |
59 | d12d51d5 | aliguori | if (loglevel) \
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60 | d12d51d5 | aliguori | fprintf(logfile, ## __VA_ARGS__); \ |
61 | d12d51d5 | aliguori | } while (0) |
62 | d12d51d5 | aliguori | #else
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63 | d12d51d5 | aliguori | # define LOG_SWTLB(...) do { } while (0) |
64 | d12d51d5 | aliguori | #endif
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65 | d12d51d5 | aliguori | |
66 | d12d51d5 | aliguori | #ifdef DEBUG_BATS
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67 | d12d51d5 | aliguori | # define LOG_BATS(...) do { \ |
68 | d12d51d5 | aliguori | if (loglevel) \
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69 | d12d51d5 | aliguori | fprintf(logfile, ## __VA_ARGS__); \ |
70 | d12d51d5 | aliguori | } while (0) |
71 | d12d51d5 | aliguori | #else
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72 | d12d51d5 | aliguori | # define LOG_BATS(...) do { } while (0) |
73 | d12d51d5 | aliguori | #endif
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74 | d12d51d5 | aliguori | |
75 | d12d51d5 | aliguori | #ifdef DEBUG_SLB
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76 | d12d51d5 | aliguori | # define LOG_SLB(...) do { \ |
77 | d12d51d5 | aliguori | if (loglevel) \
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78 | d12d51d5 | aliguori | fprintf(logfile, ## __VA_ARGS__); \ |
79 | d12d51d5 | aliguori | } while (0) |
80 | d12d51d5 | aliguori | #else
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81 | d12d51d5 | aliguori | # define LOG_SLB(...) do { } while (0) |
82 | d12d51d5 | aliguori | #endif
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83 | d12d51d5 | aliguori | |
84 | d12d51d5 | aliguori | #ifdef DEBUG_EXCEPTIONS
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85 | d12d51d5 | aliguori | # define LOG_EXCP(...) do { \ |
86 | d12d51d5 | aliguori | if (loglevel) \
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87 | d12d51d5 | aliguori | fprintf(logfile, ## __VA_ARGS__); \ |
88 | d12d51d5 | aliguori | } while (0) |
89 | d12d51d5 | aliguori | #else
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90 | d12d51d5 | aliguori | # define LOG_EXCP(...) do { } while (0) |
91 | d12d51d5 | aliguori | #endif
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92 | d12d51d5 | aliguori | |
93 | d12d51d5 | aliguori | |
94 | 9a64fbe4 | bellard | /*****************************************************************************/
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95 | 3fc6c082 | bellard | /* PowerPC MMU emulation */
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96 | a541f297 | bellard | |
97 | d9bce9d9 | j_mayer | #if defined(CONFIG_USER_ONLY)
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98 | e96efcfc | j_mayer | int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
99 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
100 | 24741ef3 | bellard | { |
101 | 24741ef3 | bellard | int exception, error_code;
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102 | d9bce9d9 | j_mayer | |
103 | 24741ef3 | bellard | if (rw == 2) { |
104 | e1833e1f | j_mayer | exception = POWERPC_EXCP_ISI; |
105 | 8f793433 | j_mayer | error_code = 0x40000000;
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106 | 24741ef3 | bellard | } else {
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107 | e1833e1f | j_mayer | exception = POWERPC_EXCP_DSI; |
108 | 8f793433 | j_mayer | error_code = 0x40000000;
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109 | 24741ef3 | bellard | if (rw)
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110 | 24741ef3 | bellard | error_code |= 0x02000000;
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111 | 24741ef3 | bellard | env->spr[SPR_DAR] = address; |
112 | 24741ef3 | bellard | env->spr[SPR_DSISR] = error_code; |
113 | 24741ef3 | bellard | } |
114 | 24741ef3 | bellard | env->exception_index = exception; |
115 | 24741ef3 | bellard | env->error_code = error_code; |
116 | 76a66253 | j_mayer | |
117 | 24741ef3 | bellard | return 1; |
118 | 24741ef3 | bellard | } |
119 | 76a66253 | j_mayer | |
120 | 9b3c35e0 | j_mayer | target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr) |
121 | 24741ef3 | bellard | { |
122 | 24741ef3 | bellard | return addr;
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123 | 24741ef3 | bellard | } |
124 | 36081602 | j_mayer | |
125 | 24741ef3 | bellard | #else
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126 | 76a66253 | j_mayer | /* Common routines used by software and hardware TLBs emulation */
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127 | b068d6a7 | j_mayer | static always_inline int pte_is_valid (target_ulong pte0) |
128 | 76a66253 | j_mayer | { |
129 | 76a66253 | j_mayer | return pte0 & 0x80000000 ? 1 : 0; |
130 | 76a66253 | j_mayer | } |
131 | 76a66253 | j_mayer | |
132 | b068d6a7 | j_mayer | static always_inline void pte_invalidate (target_ulong *pte0) |
133 | 76a66253 | j_mayer | { |
134 | 76a66253 | j_mayer | *pte0 &= ~0x80000000;
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135 | 76a66253 | j_mayer | } |
136 | 76a66253 | j_mayer | |
137 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
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138 | b068d6a7 | j_mayer | static always_inline int pte64_is_valid (target_ulong pte0) |
139 | caa4039c | j_mayer | { |
140 | caa4039c | j_mayer | return pte0 & 0x0000000000000001ULL ? 1 : 0; |
141 | caa4039c | j_mayer | } |
142 | caa4039c | j_mayer | |
143 | b068d6a7 | j_mayer | static always_inline void pte64_invalidate (target_ulong *pte0) |
144 | caa4039c | j_mayer | { |
145 | caa4039c | j_mayer | *pte0 &= ~0x0000000000000001ULL;
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146 | caa4039c | j_mayer | } |
147 | caa4039c | j_mayer | #endif
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148 | caa4039c | j_mayer | |
149 | 76a66253 | j_mayer | #define PTE_PTEM_MASK 0x7FFFFFBF |
150 | 76a66253 | j_mayer | #define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B) |
151 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
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152 | caa4039c | j_mayer | #define PTE64_PTEM_MASK 0xFFFFFFFFFFFFFF80ULL |
153 | caa4039c | j_mayer | #define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F) |
154 | caa4039c | j_mayer | #endif
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155 | 76a66253 | j_mayer | |
156 | b227a8e9 | j_mayer | static always_inline int pp_check (int key, int pp, int nx) |
157 | b227a8e9 | j_mayer | { |
158 | b227a8e9 | j_mayer | int access;
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159 | b227a8e9 | j_mayer | |
160 | b227a8e9 | j_mayer | /* Compute access rights */
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161 | b227a8e9 | j_mayer | /* When pp is 3/7, the result is undefined. Set it to noaccess */
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162 | b227a8e9 | j_mayer | access = 0;
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163 | b227a8e9 | j_mayer | if (key == 0) { |
164 | b227a8e9 | j_mayer | switch (pp) {
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165 | b227a8e9 | j_mayer | case 0x0: |
166 | b227a8e9 | j_mayer | case 0x1: |
167 | b227a8e9 | j_mayer | case 0x2: |
168 | b227a8e9 | j_mayer | access |= PAGE_WRITE; |
169 | b227a8e9 | j_mayer | /* No break here */
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170 | b227a8e9 | j_mayer | case 0x3: |
171 | b227a8e9 | j_mayer | case 0x6: |
172 | b227a8e9 | j_mayer | access |= PAGE_READ; |
173 | b227a8e9 | j_mayer | break;
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174 | b227a8e9 | j_mayer | } |
175 | b227a8e9 | j_mayer | } else {
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176 | b227a8e9 | j_mayer | switch (pp) {
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177 | b227a8e9 | j_mayer | case 0x0: |
178 | b227a8e9 | j_mayer | case 0x6: |
179 | b227a8e9 | j_mayer | access = 0;
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180 | b227a8e9 | j_mayer | break;
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181 | b227a8e9 | j_mayer | case 0x1: |
182 | b227a8e9 | j_mayer | case 0x3: |
183 | b227a8e9 | j_mayer | access = PAGE_READ; |
184 | b227a8e9 | j_mayer | break;
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185 | b227a8e9 | j_mayer | case 0x2: |
186 | b227a8e9 | j_mayer | access = PAGE_READ | PAGE_WRITE; |
187 | b227a8e9 | j_mayer | break;
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188 | b227a8e9 | j_mayer | } |
189 | b227a8e9 | j_mayer | } |
190 | b227a8e9 | j_mayer | if (nx == 0) |
191 | b227a8e9 | j_mayer | access |= PAGE_EXEC; |
192 | b227a8e9 | j_mayer | |
193 | b227a8e9 | j_mayer | return access;
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194 | b227a8e9 | j_mayer | } |
195 | b227a8e9 | j_mayer | |
196 | b227a8e9 | j_mayer | static always_inline int check_prot (int prot, int rw, int access_type) |
197 | b227a8e9 | j_mayer | { |
198 | b227a8e9 | j_mayer | int ret;
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199 | b227a8e9 | j_mayer | |
200 | b227a8e9 | j_mayer | if (access_type == ACCESS_CODE) {
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201 | b227a8e9 | j_mayer | if (prot & PAGE_EXEC)
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202 | b227a8e9 | j_mayer | ret = 0;
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203 | b227a8e9 | j_mayer | else
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204 | b227a8e9 | j_mayer | ret = -2;
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205 | b227a8e9 | j_mayer | } else if (rw) { |
206 | b227a8e9 | j_mayer | if (prot & PAGE_WRITE)
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207 | b227a8e9 | j_mayer | ret = 0;
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208 | b227a8e9 | j_mayer | else
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209 | b227a8e9 | j_mayer | ret = -2;
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210 | b227a8e9 | j_mayer | } else {
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211 | b227a8e9 | j_mayer | if (prot & PAGE_READ)
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212 | b227a8e9 | j_mayer | ret = 0;
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213 | b227a8e9 | j_mayer | else
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214 | b227a8e9 | j_mayer | ret = -2;
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215 | b227a8e9 | j_mayer | } |
216 | b227a8e9 | j_mayer | |
217 | b227a8e9 | j_mayer | return ret;
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218 | b227a8e9 | j_mayer | } |
219 | b227a8e9 | j_mayer | |
220 | b068d6a7 | j_mayer | static always_inline int _pte_check (mmu_ctx_t *ctx, int is_64b, |
221 | b068d6a7 | j_mayer | target_ulong pte0, target_ulong pte1, |
222 | b227a8e9 | j_mayer | int h, int rw, int type) |
223 | 76a66253 | j_mayer | { |
224 | caa4039c | j_mayer | target_ulong ptem, mmask; |
225 | b227a8e9 | j_mayer | int access, ret, pteh, ptev, pp;
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226 | 76a66253 | j_mayer | |
227 | 76a66253 | j_mayer | access = 0;
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228 | 76a66253 | j_mayer | ret = -1;
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229 | 76a66253 | j_mayer | /* Check validity and table match */
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230 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
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231 | caa4039c | j_mayer | if (is_64b) {
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232 | caa4039c | j_mayer | ptev = pte64_is_valid(pte0); |
233 | caa4039c | j_mayer | pteh = (pte0 >> 1) & 1; |
234 | caa4039c | j_mayer | } else
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235 | caa4039c | j_mayer | #endif
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236 | caa4039c | j_mayer | { |
237 | caa4039c | j_mayer | ptev = pte_is_valid(pte0); |
238 | caa4039c | j_mayer | pteh = (pte0 >> 6) & 1; |
239 | caa4039c | j_mayer | } |
240 | caa4039c | j_mayer | if (ptev && h == pteh) {
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241 | 76a66253 | j_mayer | /* Check vsid & api */
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242 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
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243 | caa4039c | j_mayer | if (is_64b) {
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244 | caa4039c | j_mayer | ptem = pte0 & PTE64_PTEM_MASK; |
245 | caa4039c | j_mayer | mmask = PTE64_CHECK_MASK; |
246 | b227a8e9 | j_mayer | pp = (pte1 & 0x00000003) | ((pte1 >> 61) & 0x00000004); |
247 | b227a8e9 | j_mayer | ctx->nx |= (pte1 >> 2) & 1; /* No execute bit */ |
248 | b227a8e9 | j_mayer | ctx->nx |= (pte1 >> 3) & 1; /* Guarded bit */ |
249 | caa4039c | j_mayer | } else
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250 | caa4039c | j_mayer | #endif
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251 | caa4039c | j_mayer | { |
252 | caa4039c | j_mayer | ptem = pte0 & PTE_PTEM_MASK; |
253 | caa4039c | j_mayer | mmask = PTE_CHECK_MASK; |
254 | b227a8e9 | j_mayer | pp = pte1 & 0x00000003;
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255 | caa4039c | j_mayer | } |
256 | caa4039c | j_mayer | if (ptem == ctx->ptem) {
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257 | 6f2d8978 | j_mayer | if (ctx->raddr != (target_phys_addr_t)-1ULL) { |
258 | 76a66253 | j_mayer | /* all matches should have equal RPN, WIMG & PP */
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259 | caa4039c | j_mayer | if ((ctx->raddr & mmask) != (pte1 & mmask)) {
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260 | caa4039c | j_mayer | if (loglevel != 0) |
261 | 76a66253 | j_mayer | fprintf(logfile, "Bad RPN/WIMG/PP\n");
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262 | 76a66253 | j_mayer | return -3; |
263 | 76a66253 | j_mayer | } |
264 | 76a66253 | j_mayer | } |
265 | 76a66253 | j_mayer | /* Compute access rights */
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266 | b227a8e9 | j_mayer | access = pp_check(ctx->key, pp, ctx->nx); |
267 | 76a66253 | j_mayer | /* Keep the matching PTE informations */
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268 | 76a66253 | j_mayer | ctx->raddr = pte1; |
269 | 76a66253 | j_mayer | ctx->prot = access; |
270 | b227a8e9 | j_mayer | ret = check_prot(ctx->prot, rw, type); |
271 | b227a8e9 | j_mayer | if (ret == 0) { |
272 | 76a66253 | j_mayer | /* Access granted */
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273 | d12d51d5 | aliguori | LOG_MMU("PTE access granted !\n");
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274 | 76a66253 | j_mayer | } else {
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275 | 76a66253 | j_mayer | /* Access right violation */
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276 | d12d51d5 | aliguori | LOG_MMU("PTE access rejected\n");
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277 | 76a66253 | j_mayer | } |
278 | 76a66253 | j_mayer | } |
279 | 76a66253 | j_mayer | } |
280 | 76a66253 | j_mayer | |
281 | 76a66253 | j_mayer | return ret;
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282 | 76a66253 | j_mayer | } |
283 | 76a66253 | j_mayer | |
284 | a11b8151 | j_mayer | static always_inline int pte32_check (mmu_ctx_t *ctx, |
285 | a11b8151 | j_mayer | target_ulong pte0, target_ulong pte1, |
286 | a11b8151 | j_mayer | int h, int rw, int type) |
287 | caa4039c | j_mayer | { |
288 | b227a8e9 | j_mayer | return _pte_check(ctx, 0, pte0, pte1, h, rw, type); |
289 | caa4039c | j_mayer | } |
290 | caa4039c | j_mayer | |
291 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
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292 | a11b8151 | j_mayer | static always_inline int pte64_check (mmu_ctx_t *ctx, |
293 | a11b8151 | j_mayer | target_ulong pte0, target_ulong pte1, |
294 | a11b8151 | j_mayer | int h, int rw, int type) |
295 | caa4039c | j_mayer | { |
296 | b227a8e9 | j_mayer | return _pte_check(ctx, 1, pte0, pte1, h, rw, type); |
297 | caa4039c | j_mayer | } |
298 | caa4039c | j_mayer | #endif
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299 | caa4039c | j_mayer | |
300 | a11b8151 | j_mayer | static always_inline int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p, |
301 | a11b8151 | j_mayer | int ret, int rw) |
302 | 76a66253 | j_mayer | { |
303 | 76a66253 | j_mayer | int store = 0; |
304 | 76a66253 | j_mayer | |
305 | 76a66253 | j_mayer | /* Update page flags */
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306 | 76a66253 | j_mayer | if (!(*pte1p & 0x00000100)) { |
307 | 76a66253 | j_mayer | /* Update accessed flag */
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308 | 76a66253 | j_mayer | *pte1p |= 0x00000100;
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309 | 76a66253 | j_mayer | store = 1;
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310 | 76a66253 | j_mayer | } |
311 | 76a66253 | j_mayer | if (!(*pte1p & 0x00000080)) { |
312 | 76a66253 | j_mayer | if (rw == 1 && ret == 0) { |
313 | 76a66253 | j_mayer | /* Update changed flag */
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314 | 76a66253 | j_mayer | *pte1p |= 0x00000080;
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315 | 76a66253 | j_mayer | store = 1;
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316 | 76a66253 | j_mayer | } else {
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317 | 76a66253 | j_mayer | /* Force page fault for first write access */
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318 | 76a66253 | j_mayer | ctx->prot &= ~PAGE_WRITE; |
319 | 76a66253 | j_mayer | } |
320 | 76a66253 | j_mayer | } |
321 | 76a66253 | j_mayer | |
322 | 76a66253 | j_mayer | return store;
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323 | 76a66253 | j_mayer | } |
324 | 76a66253 | j_mayer | |
325 | 76a66253 | j_mayer | /* Software driven TLB helpers */
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326 | a11b8151 | j_mayer | static always_inline int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr, |
327 | a11b8151 | j_mayer | int way, int is_code) |
328 | 76a66253 | j_mayer | { |
329 | 76a66253 | j_mayer | int nr;
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330 | 76a66253 | j_mayer | |
331 | 76a66253 | j_mayer | /* Select TLB num in a way from address */
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332 | 76a66253 | j_mayer | nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);
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333 | 76a66253 | j_mayer | /* Select TLB way */
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334 | 76a66253 | j_mayer | nr += env->tlb_per_way * way; |
335 | 76a66253 | j_mayer | /* 6xx have separate TLBs for instructions and data */
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336 | 76a66253 | j_mayer | if (is_code && env->id_tlbs == 1) |
337 | 76a66253 | j_mayer | nr += env->nb_tlb; |
338 | 76a66253 | j_mayer | |
339 | 76a66253 | j_mayer | return nr;
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340 | 76a66253 | j_mayer | } |
341 | 76a66253 | j_mayer | |
342 | a11b8151 | j_mayer | static always_inline void ppc6xx_tlb_invalidate_all (CPUState *env) |
343 | 76a66253 | j_mayer | { |
344 | 1d0a48fb | j_mayer | ppc6xx_tlb_t *tlb; |
345 | 76a66253 | j_mayer | int nr, max;
|
346 | 76a66253 | j_mayer | |
347 | d12d51d5 | aliguori | //LOG_SWTLB("Invalidate all TLBs\n");
|
348 | 76a66253 | j_mayer | /* Invalidate all defined software TLB */
|
349 | 76a66253 | j_mayer | max = env->nb_tlb; |
350 | 76a66253 | j_mayer | if (env->id_tlbs == 1) |
351 | 76a66253 | j_mayer | max *= 2;
|
352 | 76a66253 | j_mayer | for (nr = 0; nr < max; nr++) { |
353 | 1d0a48fb | j_mayer | tlb = &env->tlb[nr].tlb6; |
354 | 76a66253 | j_mayer | pte_invalidate(&tlb->pte0); |
355 | 76a66253 | j_mayer | } |
356 | 76a66253 | j_mayer | tlb_flush(env, 1);
|
357 | 76a66253 | j_mayer | } |
358 | 76a66253 | j_mayer | |
359 | b068d6a7 | j_mayer | static always_inline void __ppc6xx_tlb_invalidate_virt (CPUState *env, |
360 | b068d6a7 | j_mayer | target_ulong eaddr, |
361 | b068d6a7 | j_mayer | int is_code,
|
362 | b068d6a7 | j_mayer | int match_epn)
|
363 | 76a66253 | j_mayer | { |
364 | 4a057712 | j_mayer | #if !defined(FLUSH_ALL_TLBS)
|
365 | 1d0a48fb | j_mayer | ppc6xx_tlb_t *tlb; |
366 | 76a66253 | j_mayer | int way, nr;
|
367 | 76a66253 | j_mayer | |
368 | 76a66253 | j_mayer | /* Invalidate ITLB + DTLB, all ways */
|
369 | 76a66253 | j_mayer | for (way = 0; way < env->nb_ways; way++) { |
370 | 76a66253 | j_mayer | nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code); |
371 | 1d0a48fb | j_mayer | tlb = &env->tlb[nr].tlb6; |
372 | 76a66253 | j_mayer | if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) { |
373 | d12d51d5 | aliguori | LOG_SWTLB("TLB invalidate %d/%d " ADDRX "\n", |
374 | 76a66253 | j_mayer | nr, env->nb_tlb, eaddr); |
375 | 76a66253 | j_mayer | pte_invalidate(&tlb->pte0); |
376 | 76a66253 | j_mayer | tlb_flush_page(env, tlb->EPN); |
377 | 76a66253 | j_mayer | } |
378 | 76a66253 | j_mayer | } |
379 | 76a66253 | j_mayer | #else
|
380 | 76a66253 | j_mayer | /* XXX: PowerPC specification say this is valid as well */
|
381 | 76a66253 | j_mayer | ppc6xx_tlb_invalidate_all(env); |
382 | 76a66253 | j_mayer | #endif
|
383 | 76a66253 | j_mayer | } |
384 | 76a66253 | j_mayer | |
385 | a11b8151 | j_mayer | static always_inline void ppc6xx_tlb_invalidate_virt (CPUState *env, |
386 | a11b8151 | j_mayer | target_ulong eaddr, |
387 | a11b8151 | j_mayer | int is_code)
|
388 | 76a66253 | j_mayer | { |
389 | 76a66253 | j_mayer | __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
|
390 | 76a66253 | j_mayer | } |
391 | 76a66253 | j_mayer | |
392 | 76a66253 | j_mayer | void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code, |
393 | 76a66253 | j_mayer | target_ulong pte0, target_ulong pte1) |
394 | 76a66253 | j_mayer | { |
395 | 1d0a48fb | j_mayer | ppc6xx_tlb_t *tlb; |
396 | 76a66253 | j_mayer | int nr;
|
397 | 76a66253 | j_mayer | |
398 | 76a66253 | j_mayer | nr = ppc6xx_tlb_getnum(env, EPN, way, is_code); |
399 | 1d0a48fb | j_mayer | tlb = &env->tlb[nr].tlb6; |
400 | d12d51d5 | aliguori | LOG_SWTLB("Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX |
401 | 1b9eb036 | j_mayer | " PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1); |
402 | 76a66253 | j_mayer | /* Invalidate any pending reference in Qemu for this virtual address */
|
403 | 76a66253 | j_mayer | __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
|
404 | 76a66253 | j_mayer | tlb->pte0 = pte0; |
405 | 76a66253 | j_mayer | tlb->pte1 = pte1; |
406 | 76a66253 | j_mayer | tlb->EPN = EPN; |
407 | 76a66253 | j_mayer | /* Store last way for LRU mechanism */
|
408 | 76a66253 | j_mayer | env->last_way = way; |
409 | 76a66253 | j_mayer | } |
410 | 76a66253 | j_mayer | |
411 | a11b8151 | j_mayer | static always_inline int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx, |
412 | a11b8151 | j_mayer | target_ulong eaddr, int rw,
|
413 | a11b8151 | j_mayer | int access_type)
|
414 | 76a66253 | j_mayer | { |
415 | 1d0a48fb | j_mayer | ppc6xx_tlb_t *tlb; |
416 | 76a66253 | j_mayer | int nr, best, way;
|
417 | 76a66253 | j_mayer | int ret;
|
418 | d9bce9d9 | j_mayer | |
419 | 76a66253 | j_mayer | best = -1;
|
420 | 76a66253 | j_mayer | ret = -1; /* No TLB found */ |
421 | 76a66253 | j_mayer | for (way = 0; way < env->nb_ways; way++) { |
422 | 76a66253 | j_mayer | nr = ppc6xx_tlb_getnum(env, eaddr, way, |
423 | 76a66253 | j_mayer | access_type == ACCESS_CODE ? 1 : 0); |
424 | 1d0a48fb | j_mayer | tlb = &env->tlb[nr].tlb6; |
425 | 76a66253 | j_mayer | /* This test "emulates" the PTE index match for hardware TLBs */
|
426 | 76a66253 | j_mayer | if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
|
427 | d12d51d5 | aliguori | LOG_SWTLB("TLB %d/%d %s [" ADDRX " " ADDRX |
428 | 1b9eb036 | j_mayer | "] <> " ADDRX "\n", |
429 | 76a66253 | j_mayer | nr, env->nb_tlb, |
430 | 76a66253 | j_mayer | pte_is_valid(tlb->pte0) ? "valid" : "inval", |
431 | 76a66253 | j_mayer | tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr); |
432 | 76a66253 | j_mayer | continue;
|
433 | 76a66253 | j_mayer | } |
434 | d12d51d5 | aliguori | LOG_SWTLB("TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX |
435 | 1b9eb036 | j_mayer | " %c %c\n",
|
436 | 76a66253 | j_mayer | nr, env->nb_tlb, |
437 | 76a66253 | j_mayer | pte_is_valid(tlb->pte0) ? "valid" : "inval", |
438 | 76a66253 | j_mayer | tlb->EPN, eaddr, tlb->pte1, |
439 | 76a66253 | j_mayer | rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D'); |
440 | b227a8e9 | j_mayer | switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw, access_type)) { |
441 | 76a66253 | j_mayer | case -3: |
442 | 76a66253 | j_mayer | /* TLB inconsistency */
|
443 | 76a66253 | j_mayer | return -1; |
444 | 76a66253 | j_mayer | case -2: |
445 | 76a66253 | j_mayer | /* Access violation */
|
446 | 76a66253 | j_mayer | ret = -2;
|
447 | 76a66253 | j_mayer | best = nr; |
448 | 76a66253 | j_mayer | break;
|
449 | 76a66253 | j_mayer | case -1: |
450 | 76a66253 | j_mayer | default:
|
451 | 76a66253 | j_mayer | /* No match */
|
452 | 76a66253 | j_mayer | break;
|
453 | 76a66253 | j_mayer | case 0: |
454 | 76a66253 | j_mayer | /* access granted */
|
455 | 76a66253 | j_mayer | /* XXX: we should go on looping to check all TLBs consistency
|
456 | 76a66253 | j_mayer | * but we can speed-up the whole thing as the
|
457 | 76a66253 | j_mayer | * result would be undefined if TLBs are not consistent.
|
458 | 76a66253 | j_mayer | */
|
459 | 76a66253 | j_mayer | ret = 0;
|
460 | 76a66253 | j_mayer | best = nr; |
461 | 76a66253 | j_mayer | goto done;
|
462 | 76a66253 | j_mayer | } |
463 | 76a66253 | j_mayer | } |
464 | 76a66253 | j_mayer | if (best != -1) { |
465 | 76a66253 | j_mayer | done:
|
466 | d12d51d5 | aliguori | LOG_SWTLB("found TLB at addr " PADDRX " prot=%01x ret=%d\n", |
467 | 76a66253 | j_mayer | ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret); |
468 | 76a66253 | j_mayer | /* Update page flags */
|
469 | 1d0a48fb | j_mayer | pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw); |
470 | 76a66253 | j_mayer | } |
471 | 76a66253 | j_mayer | |
472 | 76a66253 | j_mayer | return ret;
|
473 | 76a66253 | j_mayer | } |
474 | 76a66253 | j_mayer | |
475 | 9a64fbe4 | bellard | /* Perform BAT hit & translation */
|
476 | faadf50e | j_mayer | static always_inline void bat_size_prot (CPUState *env, target_ulong *blp, |
477 | faadf50e | j_mayer | int *validp, int *protp, |
478 | faadf50e | j_mayer | target_ulong *BATu, target_ulong *BATl) |
479 | faadf50e | j_mayer | { |
480 | faadf50e | j_mayer | target_ulong bl; |
481 | faadf50e | j_mayer | int pp, valid, prot;
|
482 | faadf50e | j_mayer | |
483 | faadf50e | j_mayer | bl = (*BATu & 0x00001FFC) << 15; |
484 | faadf50e | j_mayer | valid = 0;
|
485 | faadf50e | j_mayer | prot = 0;
|
486 | faadf50e | j_mayer | if (((msr_pr == 0) && (*BATu & 0x00000002)) || |
487 | faadf50e | j_mayer | ((msr_pr != 0) && (*BATu & 0x00000001))) { |
488 | faadf50e | j_mayer | valid = 1;
|
489 | faadf50e | j_mayer | pp = *BATl & 0x00000003;
|
490 | faadf50e | j_mayer | if (pp != 0) { |
491 | faadf50e | j_mayer | prot = PAGE_READ | PAGE_EXEC; |
492 | faadf50e | j_mayer | if (pp == 0x2) |
493 | faadf50e | j_mayer | prot |= PAGE_WRITE; |
494 | faadf50e | j_mayer | } |
495 | faadf50e | j_mayer | } |
496 | faadf50e | j_mayer | *blp = bl; |
497 | faadf50e | j_mayer | *validp = valid; |
498 | faadf50e | j_mayer | *protp = prot; |
499 | faadf50e | j_mayer | } |
500 | faadf50e | j_mayer | |
501 | faadf50e | j_mayer | static always_inline void bat_601_size_prot (CPUState *env,target_ulong *blp, |
502 | faadf50e | j_mayer | int *validp, int *protp, |
503 | faadf50e | j_mayer | target_ulong *BATu, |
504 | faadf50e | j_mayer | target_ulong *BATl) |
505 | faadf50e | j_mayer | { |
506 | faadf50e | j_mayer | target_ulong bl; |
507 | faadf50e | j_mayer | int key, pp, valid, prot;
|
508 | faadf50e | j_mayer | |
509 | faadf50e | j_mayer | bl = (*BATl & 0x0000003F) << 17; |
510 | d12d51d5 | aliguori | LOG_BATS("b %02x ==> bl " ADDRX " msk " ADDRX "\n", |
511 | 6b542af7 | j_mayer | (uint8_t)(*BATl & 0x0000003F), bl, ~bl);
|
512 | faadf50e | j_mayer | prot = 0;
|
513 | faadf50e | j_mayer | valid = (*BATl >> 6) & 1; |
514 | faadf50e | j_mayer | if (valid) {
|
515 | faadf50e | j_mayer | pp = *BATu & 0x00000003;
|
516 | faadf50e | j_mayer | if (msr_pr == 0) |
517 | faadf50e | j_mayer | key = (*BATu >> 3) & 1; |
518 | faadf50e | j_mayer | else
|
519 | faadf50e | j_mayer | key = (*BATu >> 2) & 1; |
520 | faadf50e | j_mayer | prot = pp_check(key, pp, 0);
|
521 | faadf50e | j_mayer | } |
522 | faadf50e | j_mayer | *blp = bl; |
523 | faadf50e | j_mayer | *validp = valid; |
524 | faadf50e | j_mayer | *protp = prot; |
525 | faadf50e | j_mayer | } |
526 | faadf50e | j_mayer | |
527 | a11b8151 | j_mayer | static always_inline int get_bat (CPUState *env, mmu_ctx_t *ctx, |
528 | a11b8151 | j_mayer | target_ulong virtual, int rw, int type) |
529 | 9a64fbe4 | bellard | { |
530 | 76a66253 | j_mayer | target_ulong *BATlt, *BATut, *BATu, *BATl; |
531 | 76a66253 | j_mayer | target_ulong base, BEPIl, BEPIu, bl; |
532 | faadf50e | j_mayer | int i, valid, prot;
|
533 | 9a64fbe4 | bellard | int ret = -1; |
534 | 9a64fbe4 | bellard | |
535 | d12d51d5 | aliguori | LOG_BATS("%s: %cBAT v " ADDRX "\n", __func__, |
536 | 76a66253 | j_mayer | type == ACCESS_CODE ? 'I' : 'D', virtual); |
537 | 9a64fbe4 | bellard | switch (type) {
|
538 | 9a64fbe4 | bellard | case ACCESS_CODE:
|
539 | 9a64fbe4 | bellard | BATlt = env->IBAT[1];
|
540 | 9a64fbe4 | bellard | BATut = env->IBAT[0];
|
541 | 9a64fbe4 | bellard | break;
|
542 | 9a64fbe4 | bellard | default:
|
543 | 9a64fbe4 | bellard | BATlt = env->DBAT[1];
|
544 | 9a64fbe4 | bellard | BATut = env->DBAT[0];
|
545 | 9a64fbe4 | bellard | break;
|
546 | 9a64fbe4 | bellard | } |
547 | 9a64fbe4 | bellard | base = virtual & 0xFFFC0000;
|
548 | faadf50e | j_mayer | for (i = 0; i < env->nb_BATs; i++) { |
549 | 9a64fbe4 | bellard | BATu = &BATut[i]; |
550 | 9a64fbe4 | bellard | BATl = &BATlt[i]; |
551 | 9a64fbe4 | bellard | BEPIu = *BATu & 0xF0000000;
|
552 | 9a64fbe4 | bellard | BEPIl = *BATu & 0x0FFE0000;
|
553 | faadf50e | j_mayer | if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
|
554 | faadf50e | j_mayer | bat_601_size_prot(env, &bl, &valid, &prot, BATu, BATl); |
555 | faadf50e | j_mayer | } else {
|
556 | faadf50e | j_mayer | bat_size_prot(env, &bl, &valid, &prot, BATu, BATl); |
557 | faadf50e | j_mayer | } |
558 | d12d51d5 | aliguori | LOG_BATS("%s: %cBAT%d v " ADDRX " BATu " ADDRX |
559 | 6b542af7 | j_mayer | " BATl " ADDRX "\n", __func__, |
560 | 6b542af7 | j_mayer | type == ACCESS_CODE ? 'I' : 'D', i, virtual, *BATu, *BATl); |
561 | 9a64fbe4 | bellard | if ((virtual & 0xF0000000) == BEPIu && |
562 | 9a64fbe4 | bellard | ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
|
563 | 9a64fbe4 | bellard | /* BAT matches */
|
564 | faadf50e | j_mayer | if (valid != 0) { |
565 | 9a64fbe4 | bellard | /* Get physical address */
|
566 | 76a66253 | j_mayer | ctx->raddr = (*BATl & 0xF0000000) |
|
567 | 9a64fbe4 | bellard | ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) | |
568 | a541f297 | bellard | (virtual & 0x0001F000);
|
569 | b227a8e9 | j_mayer | /* Compute access rights */
|
570 | faadf50e | j_mayer | ctx->prot = prot; |
571 | b227a8e9 | j_mayer | ret = check_prot(ctx->prot, rw, type); |
572 | d12d51d5 | aliguori | if (ret == 0) |
573 | d12d51d5 | aliguori | LOG_BATS("BAT %d match: r " PADDRX " prot=%c%c\n", |
574 | d12d51d5 | aliguori | i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-', |
575 | d12d51d5 | aliguori | ctx->prot & PAGE_WRITE ? 'W' : '-'); |
576 | 9a64fbe4 | bellard | break;
|
577 | 9a64fbe4 | bellard | } |
578 | 9a64fbe4 | bellard | } |
579 | 9a64fbe4 | bellard | } |
580 | 9a64fbe4 | bellard | if (ret < 0) { |
581 | d12d51d5 | aliguori | #if defined(DEBUG_BATS)
|
582 | d12d51d5 | aliguori | if (IS_LOGGING) {
|
583 | d12d51d5 | aliguori | QEMU_LOG0("no BAT match for " ADDRX ":\n", virtual); |
584 | 4a057712 | j_mayer | for (i = 0; i < 4; i++) { |
585 | 4a057712 | j_mayer | BATu = &BATut[i]; |
586 | 4a057712 | j_mayer | BATl = &BATlt[i]; |
587 | 4a057712 | j_mayer | BEPIu = *BATu & 0xF0000000;
|
588 | 4a057712 | j_mayer | BEPIl = *BATu & 0x0FFE0000;
|
589 | 4a057712 | j_mayer | bl = (*BATu & 0x00001FFC) << 15; |
590 | d12d51d5 | aliguori | QEMU_LOG0("%s: %cBAT%d v " ADDRX " BATu " ADDRX |
591 | 6b542af7 | j_mayer | " BATl " ADDRX " \n\t" ADDRX " " ADDRX " " ADDRX "\n", |
592 | 4a057712 | j_mayer | __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, |
593 | 4a057712 | j_mayer | *BATu, *BATl, BEPIu, BEPIl, bl); |
594 | 4a057712 | j_mayer | } |
595 | 9a64fbe4 | bellard | } |
596 | 9a64fbe4 | bellard | #endif
|
597 | 9a64fbe4 | bellard | } |
598 | 9a64fbe4 | bellard | /* No hit */
|
599 | 9a64fbe4 | bellard | return ret;
|
600 | 9a64fbe4 | bellard | } |
601 | 9a64fbe4 | bellard | |
602 | 9a64fbe4 | bellard | /* PTE table lookup */
|
603 | b227a8e9 | j_mayer | static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h, |
604 | b227a8e9 | j_mayer | int rw, int type) |
605 | 9a64fbe4 | bellard | { |
606 | 76a66253 | j_mayer | target_ulong base, pte0, pte1; |
607 | 76a66253 | j_mayer | int i, good = -1; |
608 | caa4039c | j_mayer | int ret, r;
|
609 | 9a64fbe4 | bellard | |
610 | 76a66253 | j_mayer | ret = -1; /* No entry found */ |
611 | 76a66253 | j_mayer | base = ctx->pg_addr[h]; |
612 | 9a64fbe4 | bellard | for (i = 0; i < 8; i++) { |
613 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
614 | caa4039c | j_mayer | if (is_64b) {
|
615 | caa4039c | j_mayer | pte0 = ldq_phys(base + (i * 16));
|
616 | caa4039c | j_mayer | pte1 = ldq_phys(base + (i * 16) + 8); |
617 | b227a8e9 | j_mayer | r = pte64_check(ctx, pte0, pte1, h, rw, type); |
618 | d12d51d5 | aliguori | LOG_MMU("Load pte from " ADDRX " => " ADDRX " " ADDRX |
619 | 6b542af7 | j_mayer | " %d %d %d " ADDRX "\n", |
620 | 12de9a39 | j_mayer | base + (i * 16), pte0, pte1,
|
621 | 12de9a39 | j_mayer | (int)(pte0 & 1), h, (int)((pte0 >> 1) & 1), |
622 | 12de9a39 | j_mayer | ctx->ptem); |
623 | caa4039c | j_mayer | } else
|
624 | caa4039c | j_mayer | #endif
|
625 | caa4039c | j_mayer | { |
626 | caa4039c | j_mayer | pte0 = ldl_phys(base + (i * 8));
|
627 | caa4039c | j_mayer | pte1 = ldl_phys(base + (i * 8) + 4); |
628 | b227a8e9 | j_mayer | r = pte32_check(ctx, pte0, pte1, h, rw, type); |
629 | d12d51d5 | aliguori | LOG_MMU("Load pte from " ADDRX " => " ADDRX " " ADDRX |
630 | 6b542af7 | j_mayer | " %d %d %d " ADDRX "\n", |
631 | 12de9a39 | j_mayer | base + (i * 8), pte0, pte1,
|
632 | 12de9a39 | j_mayer | (int)(pte0 >> 31), h, (int)((pte0 >> 6) & 1), |
633 | 12de9a39 | j_mayer | ctx->ptem); |
634 | 12de9a39 | j_mayer | } |
635 | caa4039c | j_mayer | switch (r) {
|
636 | 76a66253 | j_mayer | case -3: |
637 | 76a66253 | j_mayer | /* PTE inconsistency */
|
638 | 76a66253 | j_mayer | return -1; |
639 | 76a66253 | j_mayer | case -2: |
640 | 76a66253 | j_mayer | /* Access violation */
|
641 | 76a66253 | j_mayer | ret = -2;
|
642 | 76a66253 | j_mayer | good = i; |
643 | 76a66253 | j_mayer | break;
|
644 | 76a66253 | j_mayer | case -1: |
645 | 76a66253 | j_mayer | default:
|
646 | 76a66253 | j_mayer | /* No PTE match */
|
647 | 76a66253 | j_mayer | break;
|
648 | 76a66253 | j_mayer | case 0: |
649 | 76a66253 | j_mayer | /* access granted */
|
650 | 76a66253 | j_mayer | /* XXX: we should go on looping to check all PTEs consistency
|
651 | 76a66253 | j_mayer | * but if we can speed-up the whole thing as the
|
652 | 76a66253 | j_mayer | * result would be undefined if PTEs are not consistent.
|
653 | 76a66253 | j_mayer | */
|
654 | 76a66253 | j_mayer | ret = 0;
|
655 | 76a66253 | j_mayer | good = i; |
656 | 76a66253 | j_mayer | goto done;
|
657 | 9a64fbe4 | bellard | } |
658 | 9a64fbe4 | bellard | } |
659 | 9a64fbe4 | bellard | if (good != -1) { |
660 | 76a66253 | j_mayer | done:
|
661 | d12d51d5 | aliguori | LOG_MMU("found PTE at addr " PADDRX " prot=%01x ret=%d\n", |
662 | 76a66253 | j_mayer | ctx->raddr, ctx->prot, ret); |
663 | 9a64fbe4 | bellard | /* Update page flags */
|
664 | 76a66253 | j_mayer | pte1 = ctx->raddr; |
665 | caa4039c | j_mayer | if (pte_update_flags(ctx, &pte1, ret, rw) == 1) { |
666 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
667 | caa4039c | j_mayer | if (is_64b) {
|
668 | caa4039c | j_mayer | stq_phys_notdirty(base + (good * 16) + 8, pte1); |
669 | caa4039c | j_mayer | } else
|
670 | caa4039c | j_mayer | #endif
|
671 | caa4039c | j_mayer | { |
672 | caa4039c | j_mayer | stl_phys_notdirty(base + (good * 8) + 4, pte1); |
673 | caa4039c | j_mayer | } |
674 | caa4039c | j_mayer | } |
675 | 9a64fbe4 | bellard | } |
676 | 9a64fbe4 | bellard | |
677 | 9a64fbe4 | bellard | return ret;
|
678 | 79aceca5 | bellard | } |
679 | 79aceca5 | bellard | |
680 | a11b8151 | j_mayer | static always_inline int find_pte32 (mmu_ctx_t *ctx, int h, int rw, int type) |
681 | caa4039c | j_mayer | { |
682 | b227a8e9 | j_mayer | return _find_pte(ctx, 0, h, rw, type); |
683 | caa4039c | j_mayer | } |
684 | caa4039c | j_mayer | |
685 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
686 | a11b8151 | j_mayer | static always_inline int find_pte64 (mmu_ctx_t *ctx, int h, int rw, int type) |
687 | caa4039c | j_mayer | { |
688 | b227a8e9 | j_mayer | return _find_pte(ctx, 1, h, rw, type); |
689 | caa4039c | j_mayer | } |
690 | caa4039c | j_mayer | #endif
|
691 | caa4039c | j_mayer | |
692 | b068d6a7 | j_mayer | static always_inline int find_pte (CPUState *env, mmu_ctx_t *ctx, |
693 | b227a8e9 | j_mayer | int h, int rw, int type) |
694 | caa4039c | j_mayer | { |
695 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
696 | add78955 | j_mayer | if (env->mmu_model & POWERPC_MMU_64)
|
697 | b227a8e9 | j_mayer | return find_pte64(ctx, h, rw, type);
|
698 | caa4039c | j_mayer | #endif
|
699 | caa4039c | j_mayer | |
700 | b227a8e9 | j_mayer | return find_pte32(ctx, h, rw, type);
|
701 | caa4039c | j_mayer | } |
702 | caa4039c | j_mayer | |
703 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
704 | a11b8151 | j_mayer | static always_inline int slb_is_valid (uint64_t slb64) |
705 | eacc3249 | j_mayer | { |
706 | eacc3249 | j_mayer | return slb64 & 0x0000000008000000ULL ? 1 : 0; |
707 | eacc3249 | j_mayer | } |
708 | eacc3249 | j_mayer | |
709 | a11b8151 | j_mayer | static always_inline void slb_invalidate (uint64_t *slb64) |
710 | eacc3249 | j_mayer | { |
711 | eacc3249 | j_mayer | *slb64 &= ~0x0000000008000000ULL;
|
712 | eacc3249 | j_mayer | } |
713 | eacc3249 | j_mayer | |
714 | a11b8151 | j_mayer | static always_inline int slb_lookup (CPUPPCState *env, target_ulong eaddr, |
715 | a11b8151 | j_mayer | target_ulong *vsid, |
716 | a11b8151 | j_mayer | target_ulong *page_mask, int *attr)
|
717 | caa4039c | j_mayer | { |
718 | caa4039c | j_mayer | target_phys_addr_t sr_base; |
719 | caa4039c | j_mayer | target_ulong mask; |
720 | caa4039c | j_mayer | uint64_t tmp64; |
721 | caa4039c | j_mayer | uint32_t tmp; |
722 | caa4039c | j_mayer | int n, ret;
|
723 | caa4039c | j_mayer | |
724 | caa4039c | j_mayer | ret = -5;
|
725 | caa4039c | j_mayer | sr_base = env->spr[SPR_ASR]; |
726 | d12d51d5 | aliguori | LOG_SLB("%s: eaddr " ADDRX " base " PADDRX "\n", |
727 | 12de9a39 | j_mayer | __func__, eaddr, sr_base); |
728 | caa4039c | j_mayer | mask = 0x0000000000000000ULL; /* Avoid gcc warning */ |
729 | eacc3249 | j_mayer | for (n = 0; n < env->slb_nr; n++) { |
730 | caa4039c | j_mayer | tmp64 = ldq_phys(sr_base); |
731 | 12de9a39 | j_mayer | tmp = ldl_phys(sr_base + 8);
|
732 | d12d51d5 | aliguori | LOG_SLB("%s: seg %d " PADDRX " %016" PRIx64 " %08" |
733 | b33c17e1 | j_mayer | PRIx32 "\n", __func__, n, sr_base, tmp64, tmp);
|
734 | eacc3249 | j_mayer | if (slb_is_valid(tmp64)) {
|
735 | caa4039c | j_mayer | /* SLB entry is valid */
|
736 | caa4039c | j_mayer | switch (tmp64 & 0x0000000006000000ULL) { |
737 | caa4039c | j_mayer | case 0x0000000000000000ULL: |
738 | caa4039c | j_mayer | /* 256 MB segment */
|
739 | caa4039c | j_mayer | mask = 0xFFFFFFFFF0000000ULL;
|
740 | caa4039c | j_mayer | break;
|
741 | caa4039c | j_mayer | case 0x0000000002000000ULL: |
742 | caa4039c | j_mayer | /* 1 TB segment */
|
743 | caa4039c | j_mayer | mask = 0xFFFF000000000000ULL;
|
744 | caa4039c | j_mayer | break;
|
745 | caa4039c | j_mayer | case 0x0000000004000000ULL: |
746 | caa4039c | j_mayer | case 0x0000000006000000ULL: |
747 | caa4039c | j_mayer | /* Reserved => segment is invalid */
|
748 | caa4039c | j_mayer | continue;
|
749 | caa4039c | j_mayer | } |
750 | caa4039c | j_mayer | if ((eaddr & mask) == (tmp64 & mask)) {
|
751 | caa4039c | j_mayer | /* SLB match */
|
752 | caa4039c | j_mayer | *vsid = ((tmp64 << 24) | (tmp >> 8)) & 0x0003FFFFFFFFFFFFULL; |
753 | caa4039c | j_mayer | *page_mask = ~mask; |
754 | caa4039c | j_mayer | *attr = tmp & 0xFF;
|
755 | eacc3249 | j_mayer | ret = n; |
756 | caa4039c | j_mayer | break;
|
757 | caa4039c | j_mayer | } |
758 | caa4039c | j_mayer | } |
759 | caa4039c | j_mayer | sr_base += 12;
|
760 | caa4039c | j_mayer | } |
761 | caa4039c | j_mayer | |
762 | caa4039c | j_mayer | return ret;
|
763 | 79aceca5 | bellard | } |
764 | 12de9a39 | j_mayer | |
765 | eacc3249 | j_mayer | void ppc_slb_invalidate_all (CPUPPCState *env)
|
766 | eacc3249 | j_mayer | { |
767 | eacc3249 | j_mayer | target_phys_addr_t sr_base; |
768 | eacc3249 | j_mayer | uint64_t tmp64; |
769 | eacc3249 | j_mayer | int n, do_invalidate;
|
770 | eacc3249 | j_mayer | |
771 | eacc3249 | j_mayer | do_invalidate = 0;
|
772 | eacc3249 | j_mayer | sr_base = env->spr[SPR_ASR]; |
773 | 2c1ee068 | j_mayer | /* XXX: Warning: slbia never invalidates the first segment */
|
774 | 2c1ee068 | j_mayer | for (n = 1; n < env->slb_nr; n++) { |
775 | eacc3249 | j_mayer | tmp64 = ldq_phys(sr_base); |
776 | eacc3249 | j_mayer | if (slb_is_valid(tmp64)) {
|
777 | eacc3249 | j_mayer | slb_invalidate(&tmp64); |
778 | eacc3249 | j_mayer | stq_phys(sr_base, tmp64); |
779 | eacc3249 | j_mayer | /* XXX: given the fact that segment size is 256 MB or 1TB,
|
780 | eacc3249 | j_mayer | * and we still don't have a tlb_flush_mask(env, n, mask)
|
781 | eacc3249 | j_mayer | * in Qemu, we just invalidate all TLBs
|
782 | eacc3249 | j_mayer | */
|
783 | eacc3249 | j_mayer | do_invalidate = 1;
|
784 | eacc3249 | j_mayer | } |
785 | eacc3249 | j_mayer | sr_base += 12;
|
786 | eacc3249 | j_mayer | } |
787 | eacc3249 | j_mayer | if (do_invalidate)
|
788 | eacc3249 | j_mayer | tlb_flush(env, 1);
|
789 | eacc3249 | j_mayer | } |
790 | eacc3249 | j_mayer | |
791 | eacc3249 | j_mayer | void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0)
|
792 | eacc3249 | j_mayer | { |
793 | eacc3249 | j_mayer | target_phys_addr_t sr_base; |
794 | eacc3249 | j_mayer | target_ulong vsid, page_mask; |
795 | eacc3249 | j_mayer | uint64_t tmp64; |
796 | eacc3249 | j_mayer | int attr;
|
797 | eacc3249 | j_mayer | int n;
|
798 | eacc3249 | j_mayer | |
799 | eacc3249 | j_mayer | n = slb_lookup(env, T0, &vsid, &page_mask, &attr); |
800 | eacc3249 | j_mayer | if (n >= 0) { |
801 | eacc3249 | j_mayer | sr_base = env->spr[SPR_ASR]; |
802 | eacc3249 | j_mayer | sr_base += 12 * n;
|
803 | eacc3249 | j_mayer | tmp64 = ldq_phys(sr_base); |
804 | eacc3249 | j_mayer | if (slb_is_valid(tmp64)) {
|
805 | eacc3249 | j_mayer | slb_invalidate(&tmp64); |
806 | eacc3249 | j_mayer | stq_phys(sr_base, tmp64); |
807 | eacc3249 | j_mayer | /* XXX: given the fact that segment size is 256 MB or 1TB,
|
808 | eacc3249 | j_mayer | * and we still don't have a tlb_flush_mask(env, n, mask)
|
809 | eacc3249 | j_mayer | * in Qemu, we just invalidate all TLBs
|
810 | eacc3249 | j_mayer | */
|
811 | eacc3249 | j_mayer | tlb_flush(env, 1);
|
812 | eacc3249 | j_mayer | } |
813 | eacc3249 | j_mayer | } |
814 | eacc3249 | j_mayer | } |
815 | eacc3249 | j_mayer | |
816 | 12de9a39 | j_mayer | target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr)
|
817 | 12de9a39 | j_mayer | { |
818 | 12de9a39 | j_mayer | target_phys_addr_t sr_base; |
819 | 12de9a39 | j_mayer | target_ulong rt; |
820 | 12de9a39 | j_mayer | uint64_t tmp64; |
821 | 12de9a39 | j_mayer | uint32_t tmp; |
822 | 12de9a39 | j_mayer | |
823 | 12de9a39 | j_mayer | sr_base = env->spr[SPR_ASR]; |
824 | 12de9a39 | j_mayer | sr_base += 12 * slb_nr;
|
825 | 12de9a39 | j_mayer | tmp64 = ldq_phys(sr_base); |
826 | 12de9a39 | j_mayer | tmp = ldl_phys(sr_base + 8);
|
827 | 12de9a39 | j_mayer | if (tmp64 & 0x0000000008000000ULL) { |
828 | 12de9a39 | j_mayer | /* SLB entry is valid */
|
829 | 12de9a39 | j_mayer | /* Copy SLB bits 62:88 to Rt 37:63 (VSID 23:49) */
|
830 | 12de9a39 | j_mayer | rt = tmp >> 8; /* 65:88 => 40:63 */ |
831 | 12de9a39 | j_mayer | rt |= (tmp64 & 0x7) << 24; /* 62:64 => 37:39 */ |
832 | 12de9a39 | j_mayer | /* Copy SLB bits 89:92 to Rt 33:36 (KsKpNL) */
|
833 | 12de9a39 | j_mayer | rt |= ((tmp >> 4) & 0xF) << 27; |
834 | 12de9a39 | j_mayer | } else {
|
835 | 12de9a39 | j_mayer | rt = 0;
|
836 | 12de9a39 | j_mayer | } |
837 | d12d51d5 | aliguori | LOG_SLB("%s: " PADDRX " %016" PRIx64 " %08" PRIx32 " => %d " |
838 | 12de9a39 | j_mayer | ADDRX "\n", __func__, sr_base, tmp64, tmp, slb_nr, rt);
|
839 | 12de9a39 | j_mayer | |
840 | 12de9a39 | j_mayer | return rt;
|
841 | 12de9a39 | j_mayer | } |
842 | 12de9a39 | j_mayer | |
843 | 12de9a39 | j_mayer | void ppc_store_slb (CPUPPCState *env, int slb_nr, target_ulong rs) |
844 | 12de9a39 | j_mayer | { |
845 | 12de9a39 | j_mayer | target_phys_addr_t sr_base; |
846 | 12de9a39 | j_mayer | uint64_t tmp64; |
847 | 12de9a39 | j_mayer | uint32_t tmp; |
848 | 12de9a39 | j_mayer | |
849 | 12de9a39 | j_mayer | sr_base = env->spr[SPR_ASR]; |
850 | 12de9a39 | j_mayer | sr_base += 12 * slb_nr;
|
851 | 12de9a39 | j_mayer | /* Copy Rs bits 37:63 to SLB 62:88 */
|
852 | 12de9a39 | j_mayer | tmp = rs << 8;
|
853 | 12de9a39 | j_mayer | tmp64 = (rs >> 24) & 0x7; |
854 | 12de9a39 | j_mayer | /* Copy Rs bits 33:36 to SLB 89:92 */
|
855 | 12de9a39 | j_mayer | tmp |= ((rs >> 27) & 0xF) << 4; |
856 | 12de9a39 | j_mayer | /* Set the valid bit */
|
857 | 12de9a39 | j_mayer | tmp64 |= 1 << 27; |
858 | 12de9a39 | j_mayer | /* Set ESID */
|
859 | 12de9a39 | j_mayer | tmp64 |= (uint32_t)slb_nr << 28;
|
860 | d12d51d5 | aliguori | LOG_SLB("%s: %d " ADDRX " => " PADDRX " %016" PRIx64 |
861 | 6b542af7 | j_mayer | " %08" PRIx32 "\n", __func__, |
862 | 6b542af7 | j_mayer | slb_nr, rs, sr_base, tmp64, tmp); |
863 | 12de9a39 | j_mayer | /* Write SLB entry to memory */
|
864 | 12de9a39 | j_mayer | stq_phys(sr_base, tmp64); |
865 | 12de9a39 | j_mayer | stl_phys(sr_base + 8, tmp);
|
866 | 12de9a39 | j_mayer | } |
867 | caa4039c | j_mayer | #endif /* defined(TARGET_PPC64) */ |
868 | 79aceca5 | bellard | |
869 | 9a64fbe4 | bellard | /* Perform segment based translation */
|
870 | b068d6a7 | j_mayer | static always_inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1,
|
871 | b068d6a7 | j_mayer | int sdr_sh,
|
872 | b068d6a7 | j_mayer | target_phys_addr_t hash, |
873 | b068d6a7 | j_mayer | target_phys_addr_t mask) |
874 | 12de9a39 | j_mayer | { |
875 | 6f2d8978 | j_mayer | return (sdr1 & ((target_phys_addr_t)(-1ULL) << sdr_sh)) | (hash & mask); |
876 | 12de9a39 | j_mayer | } |
877 | 12de9a39 | j_mayer | |
878 | a11b8151 | j_mayer | static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx, |
879 | a11b8151 | j_mayer | target_ulong eaddr, int rw, int type) |
880 | 79aceca5 | bellard | { |
881 | 12de9a39 | j_mayer | target_phys_addr_t sdr, hash, mask, sdr_mask, htab_mask; |
882 | caa4039c | j_mayer | target_ulong sr, vsid, vsid_mask, pgidx, page_mask; |
883 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
884 | caa4039c | j_mayer | int attr;
|
885 | 9a64fbe4 | bellard | #endif
|
886 | 0411a972 | j_mayer | int ds, vsid_sh, sdr_sh, pr;
|
887 | caa4039c | j_mayer | int ret, ret2;
|
888 | caa4039c | j_mayer | |
889 | 0411a972 | j_mayer | pr = msr_pr; |
890 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
891 | add78955 | j_mayer | if (env->mmu_model & POWERPC_MMU_64) {
|
892 | d12d51d5 | aliguori | LOG_MMU("Check SLBs\n");
|
893 | caa4039c | j_mayer | ret = slb_lookup(env, eaddr, &vsid, &page_mask, &attr); |
894 | caa4039c | j_mayer | if (ret < 0) |
895 | caa4039c | j_mayer | return ret;
|
896 | 0411a972 | j_mayer | ctx->key = ((attr & 0x40) && (pr != 0)) || |
897 | 0411a972 | j_mayer | ((attr & 0x80) && (pr == 0)) ? 1 : 0; |
898 | caa4039c | j_mayer | ds = 0;
|
899 | b227a8e9 | j_mayer | ctx->nx = attr & 0x20 ? 1 : 0; |
900 | caa4039c | j_mayer | vsid_mask = 0x00003FFFFFFFFF80ULL;
|
901 | caa4039c | j_mayer | vsid_sh = 7;
|
902 | caa4039c | j_mayer | sdr_sh = 18;
|
903 | caa4039c | j_mayer | sdr_mask = 0x3FF80;
|
904 | caa4039c | j_mayer | } else
|
905 | caa4039c | j_mayer | #endif /* defined(TARGET_PPC64) */ |
906 | caa4039c | j_mayer | { |
907 | caa4039c | j_mayer | sr = env->sr[eaddr >> 28];
|
908 | caa4039c | j_mayer | page_mask = 0x0FFFFFFF;
|
909 | 0411a972 | j_mayer | ctx->key = (((sr & 0x20000000) && (pr != 0)) || |
910 | 0411a972 | j_mayer | ((sr & 0x40000000) && (pr == 0))) ? 1 : 0; |
911 | caa4039c | j_mayer | ds = sr & 0x80000000 ? 1 : 0; |
912 | b227a8e9 | j_mayer | ctx->nx = sr & 0x10000000 ? 1 : 0; |
913 | caa4039c | j_mayer | vsid = sr & 0x00FFFFFF;
|
914 | caa4039c | j_mayer | vsid_mask = 0x01FFFFC0;
|
915 | caa4039c | j_mayer | vsid_sh = 6;
|
916 | caa4039c | j_mayer | sdr_sh = 16;
|
917 | caa4039c | j_mayer | sdr_mask = 0xFFC0;
|
918 | d12d51d5 | aliguori | LOG_MMU("Check segment v=" ADDRX " %d " ADDRX |
919 | 6b542af7 | j_mayer | " nip=" ADDRX " lr=" ADDRX " ir=%d dr=%d pr=%d %d t=%d\n", |
920 | caa4039c | j_mayer | eaddr, (int)(eaddr >> 28), sr, env->nip, |
921 | 0411a972 | j_mayer | env->lr, (int)msr_ir, (int)msr_dr, pr != 0 ? 1 : 0, |
922 | 0411a972 | j_mayer | rw, type); |
923 | caa4039c | j_mayer | } |
924 | d12d51d5 | aliguori | LOG_MMU("pte segment: key=%d ds %d nx %d vsid " ADDRX "\n", |
925 | b227a8e9 | j_mayer | ctx->key, ds, ctx->nx, vsid); |
926 | caa4039c | j_mayer | ret = -1;
|
927 | caa4039c | j_mayer | if (!ds) {
|
928 | 9a64fbe4 | bellard | /* Check if instruction fetch is allowed, if needed */
|
929 | b227a8e9 | j_mayer | if (type != ACCESS_CODE || ctx->nx == 0) { |
930 | 9a64fbe4 | bellard | /* Page address translation */
|
931 | 76a66253 | j_mayer | /* Primary table address */
|
932 | 76a66253 | j_mayer | sdr = env->sdr1; |
933 | 12de9a39 | j_mayer | pgidx = (eaddr & page_mask) >> TARGET_PAGE_BITS; |
934 | 12de9a39 | j_mayer | #if defined(TARGET_PPC64)
|
935 | add78955 | j_mayer | if (env->mmu_model & POWERPC_MMU_64) {
|
936 | 12de9a39 | j_mayer | htab_mask = 0x0FFFFFFF >> (28 - (sdr & 0x1F)); |
937 | 12de9a39 | j_mayer | /* XXX: this is false for 1 TB segments */
|
938 | 12de9a39 | j_mayer | hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask; |
939 | 12de9a39 | j_mayer | } else
|
940 | 12de9a39 | j_mayer | #endif
|
941 | 12de9a39 | j_mayer | { |
942 | 12de9a39 | j_mayer | htab_mask = sdr & 0x000001FF;
|
943 | 12de9a39 | j_mayer | hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask; |
944 | 12de9a39 | j_mayer | } |
945 | 12de9a39 | j_mayer | mask = (htab_mask << sdr_sh) | sdr_mask; |
946 | d12d51d5 | aliguori | LOG_MMU("sdr " PADDRX " sh %d hash " PADDRX |
947 | 6b542af7 | j_mayer | " mask " PADDRX " " ADDRX "\n", |
948 | 6b542af7 | j_mayer | sdr, sdr_sh, hash, mask, page_mask); |
949 | caa4039c | j_mayer | ctx->pg_addr[0] = get_pgaddr(sdr, sdr_sh, hash, mask);
|
950 | 76a66253 | j_mayer | /* Secondary table address */
|
951 | caa4039c | j_mayer | hash = (~hash) & vsid_mask; |
952 | d12d51d5 | aliguori | LOG_MMU("sdr " PADDRX " sh %d hash " PADDRX |
953 | 6b542af7 | j_mayer | " mask " PADDRX "\n", |
954 | 6b542af7 | j_mayer | sdr, sdr_sh, hash, mask); |
955 | caa4039c | j_mayer | ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask);
|
956 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
957 | add78955 | j_mayer | if (env->mmu_model & POWERPC_MMU_64) {
|
958 | caa4039c | j_mayer | /* Only 5 bits of the page index are used in the AVPN */
|
959 | caa4039c | j_mayer | ctx->ptem = (vsid << 12) | ((pgidx >> 4) & 0x0F80); |
960 | caa4039c | j_mayer | } else
|
961 | caa4039c | j_mayer | #endif
|
962 | caa4039c | j_mayer | { |
963 | caa4039c | j_mayer | ctx->ptem = (vsid << 7) | (pgidx >> 10); |
964 | caa4039c | j_mayer | } |
965 | 76a66253 | j_mayer | /* Initialize real address with an invalid value */
|
966 | 6f2d8978 | j_mayer | ctx->raddr = (target_phys_addr_t)-1ULL;
|
967 | 7dbe11ac | j_mayer | if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx ||
|
968 | 7dbe11ac | j_mayer | env->mmu_model == POWERPC_MMU_SOFT_74xx)) { |
969 | 76a66253 | j_mayer | /* Software TLB search */
|
970 | 76a66253 | j_mayer | ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type); |
971 | 76a66253 | j_mayer | } else {
|
972 | d12d51d5 | aliguori | LOG_MMU("0 sdr1=" PADDRX " vsid=" ADDRX " " |
973 | 6b542af7 | j_mayer | "api=" ADDRX " hash=" PADDRX |
974 | 6b542af7 | j_mayer | " pg_addr=" PADDRX "\n", |
975 | 6b542af7 | j_mayer | sdr, vsid, pgidx, hash, ctx->pg_addr[0]);
|
976 | 76a66253 | j_mayer | /* Primary table lookup */
|
977 | b227a8e9 | j_mayer | ret = find_pte(env, ctx, 0, rw, type);
|
978 | 76a66253 | j_mayer | if (ret < 0) { |
979 | 76a66253 | j_mayer | /* Secondary table lookup */
|
980 | d12d51d5 | aliguori | if (eaddr != 0xEFFFFFFF) |
981 | d12d51d5 | aliguori | LOG_MMU("1 sdr1=" PADDRX " vsid=" ADDRX " " |
982 | 6b542af7 | j_mayer | "api=" ADDRX " hash=" PADDRX |
983 | 6b542af7 | j_mayer | " pg_addr=" PADDRX "\n", |
984 | 6b542af7 | j_mayer | sdr, vsid, pgidx, hash, ctx->pg_addr[1]);
|
985 | b227a8e9 | j_mayer | ret2 = find_pte(env, ctx, 1, rw, type);
|
986 | 76a66253 | j_mayer | if (ret2 != -1) |
987 | 76a66253 | j_mayer | ret = ret2; |
988 | 76a66253 | j_mayer | } |
989 | 9a64fbe4 | bellard | } |
990 | 0411a972 | j_mayer | #if defined (DUMP_PAGE_TABLES)
|
991 | b33c17e1 | j_mayer | if (loglevel != 0) { |
992 | b33c17e1 | j_mayer | target_phys_addr_t curaddr; |
993 | b33c17e1 | j_mayer | uint32_t a0, a1, a2, a3; |
994 | 6b542af7 | j_mayer | fprintf(logfile, "Page table: " PADDRX " len " PADDRX "\n", |
995 | b33c17e1 | j_mayer | sdr, mask + 0x80);
|
996 | b33c17e1 | j_mayer | for (curaddr = sdr; curaddr < (sdr + mask + 0x80); |
997 | b33c17e1 | j_mayer | curaddr += 16) {
|
998 | b33c17e1 | j_mayer | a0 = ldl_phys(curaddr); |
999 | b33c17e1 | j_mayer | a1 = ldl_phys(curaddr + 4);
|
1000 | b33c17e1 | j_mayer | a2 = ldl_phys(curaddr + 8);
|
1001 | b33c17e1 | j_mayer | a3 = ldl_phys(curaddr + 12);
|
1002 | b33c17e1 | j_mayer | if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) { |
1003 | 6b542af7 | j_mayer | fprintf(logfile, PADDRX ": %08x %08x %08x %08x\n",
|
1004 | b33c17e1 | j_mayer | curaddr, a0, a1, a2, a3); |
1005 | 12de9a39 | j_mayer | } |
1006 | b33c17e1 | j_mayer | } |
1007 | b33c17e1 | j_mayer | } |
1008 | 12de9a39 | j_mayer | #endif
|
1009 | 9a64fbe4 | bellard | } else {
|
1010 | d12d51d5 | aliguori | LOG_MMU("No access allowed\n");
|
1011 | 76a66253 | j_mayer | ret = -3;
|
1012 | 9a64fbe4 | bellard | } |
1013 | 9a64fbe4 | bellard | } else {
|
1014 | d12d51d5 | aliguori | LOG_MMU("direct store...\n");
|
1015 | 9a64fbe4 | bellard | /* Direct-store segment : absolutely *BUGGY* for now */
|
1016 | 9a64fbe4 | bellard | switch (type) {
|
1017 | 9a64fbe4 | bellard | case ACCESS_INT:
|
1018 | 9a64fbe4 | bellard | /* Integer load/store : only access allowed */
|
1019 | 9a64fbe4 | bellard | break;
|
1020 | 9a64fbe4 | bellard | case ACCESS_CODE:
|
1021 | 9a64fbe4 | bellard | /* No code fetch is allowed in direct-store areas */
|
1022 | 9a64fbe4 | bellard | return -4; |
1023 | 9a64fbe4 | bellard | case ACCESS_FLOAT:
|
1024 | 9a64fbe4 | bellard | /* Floating point load/store */
|
1025 | 9a64fbe4 | bellard | return -4; |
1026 | 9a64fbe4 | bellard | case ACCESS_RES:
|
1027 | 9a64fbe4 | bellard | /* lwarx, ldarx or srwcx. */
|
1028 | 9a64fbe4 | bellard | return -4; |
1029 | 9a64fbe4 | bellard | case ACCESS_CACHE:
|
1030 | 9a64fbe4 | bellard | /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
|
1031 | 9a64fbe4 | bellard | /* Should make the instruction do no-op.
|
1032 | 9a64fbe4 | bellard | * As it already do no-op, it's quite easy :-)
|
1033 | 9a64fbe4 | bellard | */
|
1034 | 76a66253 | j_mayer | ctx->raddr = eaddr; |
1035 | 9a64fbe4 | bellard | return 0; |
1036 | 9a64fbe4 | bellard | case ACCESS_EXT:
|
1037 | 9a64fbe4 | bellard | /* eciwx or ecowx */
|
1038 | 9a64fbe4 | bellard | return -4; |
1039 | 9a64fbe4 | bellard | default:
|
1040 | 9a64fbe4 | bellard | if (logfile) {
|
1041 | 9a64fbe4 | bellard | fprintf(logfile, "ERROR: instruction should not need "
|
1042 | 9a64fbe4 | bellard | "address translation\n");
|
1043 | 9a64fbe4 | bellard | } |
1044 | 9a64fbe4 | bellard | return -4; |
1045 | 9a64fbe4 | bellard | } |
1046 | 76a66253 | j_mayer | if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) { |
1047 | 76a66253 | j_mayer | ctx->raddr = eaddr; |
1048 | 9a64fbe4 | bellard | ret = 2;
|
1049 | 9a64fbe4 | bellard | } else {
|
1050 | 9a64fbe4 | bellard | ret = -2;
|
1051 | 9a64fbe4 | bellard | } |
1052 | 79aceca5 | bellard | } |
1053 | 9a64fbe4 | bellard | |
1054 | 9a64fbe4 | bellard | return ret;
|
1055 | 79aceca5 | bellard | } |
1056 | 79aceca5 | bellard | |
1057 | c294fc58 | j_mayer | /* Generic TLB check function for embedded PowerPC implementations */
|
1058 | a11b8151 | j_mayer | static always_inline int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb, |
1059 | a11b8151 | j_mayer | target_phys_addr_t *raddrp, |
1060 | a11b8151 | j_mayer | target_ulong address, |
1061 | a11b8151 | j_mayer | uint32_t pid, int ext, int i) |
1062 | c294fc58 | j_mayer | { |
1063 | c294fc58 | j_mayer | target_ulong mask; |
1064 | c294fc58 | j_mayer | |
1065 | c294fc58 | j_mayer | /* Check valid flag */
|
1066 | c294fc58 | j_mayer | if (!(tlb->prot & PAGE_VALID)) {
|
1067 | c294fc58 | j_mayer | if (loglevel != 0) |
1068 | c294fc58 | j_mayer | fprintf(logfile, "%s: TLB %d not valid\n", __func__, i);
|
1069 | c294fc58 | j_mayer | return -1; |
1070 | c294fc58 | j_mayer | } |
1071 | c294fc58 | j_mayer | mask = ~(tlb->size - 1);
|
1072 | d12d51d5 | aliguori | LOG_SWTLB("%s: TLB %d address " ADDRX " PID %u <=> " ADDRX |
1073 | 6b542af7 | j_mayer | " " ADDRX " %u\n", |
1074 | 6b542af7 | j_mayer | __func__, i, address, pid, tlb->EPN, mask, (uint32_t)tlb->PID); |
1075 | c294fc58 | j_mayer | /* Check PID */
|
1076 | 36081602 | j_mayer | if (tlb->PID != 0 && tlb->PID != pid) |
1077 | c294fc58 | j_mayer | return -1; |
1078 | c294fc58 | j_mayer | /* Check effective address */
|
1079 | c294fc58 | j_mayer | if ((address & mask) != tlb->EPN)
|
1080 | c294fc58 | j_mayer | return -1; |
1081 | c294fc58 | j_mayer | *raddrp = (tlb->RPN & mask) | (address & ~mask); |
1082 | 9706285b | j_mayer | #if (TARGET_PHYS_ADDR_BITS >= 36) |
1083 | 36081602 | j_mayer | if (ext) {
|
1084 | 36081602 | j_mayer | /* Extend the physical address to 36 bits */
|
1085 | 36081602 | j_mayer | *raddrp |= (target_phys_addr_t)(tlb->RPN & 0xF) << 32; |
1086 | 36081602 | j_mayer | } |
1087 | 9706285b | j_mayer | #endif
|
1088 | c294fc58 | j_mayer | |
1089 | c294fc58 | j_mayer | return 0; |
1090 | c294fc58 | j_mayer | } |
1091 | c294fc58 | j_mayer | |
1092 | c294fc58 | j_mayer | /* Generic TLB search function for PowerPC embedded implementations */
|
1093 | 36081602 | j_mayer | int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid)
|
1094 | c294fc58 | j_mayer | { |
1095 | c294fc58 | j_mayer | ppcemb_tlb_t *tlb; |
1096 | c294fc58 | j_mayer | target_phys_addr_t raddr; |
1097 | c294fc58 | j_mayer | int i, ret;
|
1098 | c294fc58 | j_mayer | |
1099 | c294fc58 | j_mayer | /* Default return value is no match */
|
1100 | c294fc58 | j_mayer | ret = -1;
|
1101 | a750fc0b | j_mayer | for (i = 0; i < env->nb_tlb; i++) { |
1102 | c294fc58 | j_mayer | tlb = &env->tlb[i].tlbe; |
1103 | 36081602 | j_mayer | if (ppcemb_tlb_check(env, tlb, &raddr, address, pid, 0, i) == 0) { |
1104 | c294fc58 | j_mayer | ret = i; |
1105 | c294fc58 | j_mayer | break;
|
1106 | c294fc58 | j_mayer | } |
1107 | c294fc58 | j_mayer | } |
1108 | c294fc58 | j_mayer | |
1109 | c294fc58 | j_mayer | return ret;
|
1110 | c294fc58 | j_mayer | } |
1111 | c294fc58 | j_mayer | |
1112 | daf4f96e | j_mayer | /* Helpers specific to PowerPC 40x implementations */
|
1113 | a11b8151 | j_mayer | static always_inline void ppc4xx_tlb_invalidate_all (CPUState *env) |
1114 | a750fc0b | j_mayer | { |
1115 | a750fc0b | j_mayer | ppcemb_tlb_t *tlb; |
1116 | a750fc0b | j_mayer | int i;
|
1117 | a750fc0b | j_mayer | |
1118 | a750fc0b | j_mayer | for (i = 0; i < env->nb_tlb; i++) { |
1119 | a750fc0b | j_mayer | tlb = &env->tlb[i].tlbe; |
1120 | daf4f96e | j_mayer | tlb->prot &= ~PAGE_VALID; |
1121 | a750fc0b | j_mayer | } |
1122 | daf4f96e | j_mayer | tlb_flush(env, 1);
|
1123 | a750fc0b | j_mayer | } |
1124 | a750fc0b | j_mayer | |
1125 | a11b8151 | j_mayer | static always_inline void ppc4xx_tlb_invalidate_virt (CPUState *env, |
1126 | a11b8151 | j_mayer | target_ulong eaddr, |
1127 | a11b8151 | j_mayer | uint32_t pid) |
1128 | 0a032cbe | j_mayer | { |
1129 | daf4f96e | j_mayer | #if !defined(FLUSH_ALL_TLBS)
|
1130 | 0a032cbe | j_mayer | ppcemb_tlb_t *tlb; |
1131 | daf4f96e | j_mayer | target_phys_addr_t raddr; |
1132 | daf4f96e | j_mayer | target_ulong page, end; |
1133 | 0a032cbe | j_mayer | int i;
|
1134 | 0a032cbe | j_mayer | |
1135 | 0a032cbe | j_mayer | for (i = 0; i < env->nb_tlb; i++) { |
1136 | 0a032cbe | j_mayer | tlb = &env->tlb[i].tlbe; |
1137 | daf4f96e | j_mayer | if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) { |
1138 | 0a032cbe | j_mayer | end = tlb->EPN + tlb->size; |
1139 | 0a032cbe | j_mayer | for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
|
1140 | 0a032cbe | j_mayer | tlb_flush_page(env, page); |
1141 | 0a032cbe | j_mayer | tlb->prot &= ~PAGE_VALID; |
1142 | daf4f96e | j_mayer | break;
|
1143 | 0a032cbe | j_mayer | } |
1144 | 0a032cbe | j_mayer | } |
1145 | daf4f96e | j_mayer | #else
|
1146 | daf4f96e | j_mayer | ppc4xx_tlb_invalidate_all(env); |
1147 | daf4f96e | j_mayer | #endif
|
1148 | 0a032cbe | j_mayer | } |
1149 | 0a032cbe | j_mayer | |
1150 | 93220573 | aurel32 | static int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx, |
1151 | e96efcfc | j_mayer | target_ulong address, int rw, int access_type) |
1152 | a8dea12f | j_mayer | { |
1153 | a8dea12f | j_mayer | ppcemb_tlb_t *tlb; |
1154 | a8dea12f | j_mayer | target_phys_addr_t raddr; |
1155 | 0411a972 | j_mayer | int i, ret, zsel, zpr, pr;
|
1156 | 3b46e624 | ths | |
1157 | c55e9aef | j_mayer | ret = -1;
|
1158 | 6f2d8978 | j_mayer | raddr = (target_phys_addr_t)-1ULL;
|
1159 | 0411a972 | j_mayer | pr = msr_pr; |
1160 | a8dea12f | j_mayer | for (i = 0; i < env->nb_tlb; i++) { |
1161 | a8dea12f | j_mayer | tlb = &env->tlb[i].tlbe; |
1162 | 36081602 | j_mayer | if (ppcemb_tlb_check(env, tlb, &raddr, address,
|
1163 | 36081602 | j_mayer | env->spr[SPR_40x_PID], 0, i) < 0) |
1164 | a8dea12f | j_mayer | continue;
|
1165 | a8dea12f | j_mayer | zsel = (tlb->attr >> 4) & 0xF; |
1166 | a8dea12f | j_mayer | zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3; |
1167 | d12d51d5 | aliguori | LOG_SWTLB("%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
|
1168 | a8dea12f | j_mayer | __func__, i, zsel, zpr, rw, tlb->attr); |
1169 | b227a8e9 | j_mayer | /* Check execute enable bit */
|
1170 | b227a8e9 | j_mayer | switch (zpr) {
|
1171 | b227a8e9 | j_mayer | case 0x2: |
1172 | 0411a972 | j_mayer | if (pr != 0) |
1173 | b227a8e9 | j_mayer | goto check_perms;
|
1174 | b227a8e9 | j_mayer | /* No break here */
|
1175 | b227a8e9 | j_mayer | case 0x3: |
1176 | b227a8e9 | j_mayer | /* All accesses granted */
|
1177 | b227a8e9 | j_mayer | ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
1178 | b227a8e9 | j_mayer | ret = 0;
|
1179 | b227a8e9 | j_mayer | break;
|
1180 | b227a8e9 | j_mayer | case 0x0: |
1181 | 0411a972 | j_mayer | if (pr != 0) { |
1182 | b227a8e9 | j_mayer | ctx->prot = 0;
|
1183 | b227a8e9 | j_mayer | ret = -2;
|
1184 | a8dea12f | j_mayer | break;
|
1185 | a8dea12f | j_mayer | } |
1186 | b227a8e9 | j_mayer | /* No break here */
|
1187 | b227a8e9 | j_mayer | case 0x1: |
1188 | b227a8e9 | j_mayer | check_perms:
|
1189 | b227a8e9 | j_mayer | /* Check from TLB entry */
|
1190 | b227a8e9 | j_mayer | /* XXX: there is a problem here or in the TLB fill code... */
|
1191 | b227a8e9 | j_mayer | ctx->prot = tlb->prot; |
1192 | b227a8e9 | j_mayer | ctx->prot |= PAGE_EXEC; |
1193 | b227a8e9 | j_mayer | ret = check_prot(ctx->prot, rw, access_type); |
1194 | b227a8e9 | j_mayer | break;
|
1195 | a8dea12f | j_mayer | } |
1196 | a8dea12f | j_mayer | if (ret >= 0) { |
1197 | a8dea12f | j_mayer | ctx->raddr = raddr; |
1198 | d12d51d5 | aliguori | LOG_SWTLB("%s: access granted " ADDRX " => " PADDRX |
1199 | c55e9aef | j_mayer | " %d %d\n", __func__, address, ctx->raddr, ctx->prot,
|
1200 | c55e9aef | j_mayer | ret); |
1201 | c55e9aef | j_mayer | return 0; |
1202 | a8dea12f | j_mayer | } |
1203 | a8dea12f | j_mayer | } |
1204 | d12d51d5 | aliguori | LOG_SWTLB("%s: access refused " ADDRX " => " PADDRX |
1205 | c55e9aef | j_mayer | " %d %d\n", __func__, address, raddr, ctx->prot,
|
1206 | c55e9aef | j_mayer | ret); |
1207 | 3b46e624 | ths | |
1208 | a8dea12f | j_mayer | return ret;
|
1209 | a8dea12f | j_mayer | } |
1210 | a8dea12f | j_mayer | |
1211 | c294fc58 | j_mayer | void store_40x_sler (CPUPPCState *env, uint32_t val)
|
1212 | c294fc58 | j_mayer | { |
1213 | c294fc58 | j_mayer | /* XXX: TO BE FIXED */
|
1214 | c294fc58 | j_mayer | if (val != 0x00000000) { |
1215 | c294fc58 | j_mayer | cpu_abort(env, "Little-endian regions are not supported by now\n");
|
1216 | c294fc58 | j_mayer | } |
1217 | c294fc58 | j_mayer | env->spr[SPR_405_SLER] = val; |
1218 | c294fc58 | j_mayer | } |
1219 | c294fc58 | j_mayer | |
1220 | 93220573 | aurel32 | static int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx, |
1221 | 93220573 | aurel32 | target_ulong address, int rw,
|
1222 | 93220573 | aurel32 | int access_type)
|
1223 | 5eb7995e | j_mayer | { |
1224 | 5eb7995e | j_mayer | ppcemb_tlb_t *tlb; |
1225 | 5eb7995e | j_mayer | target_phys_addr_t raddr; |
1226 | 5eb7995e | j_mayer | int i, prot, ret;
|
1227 | 5eb7995e | j_mayer | |
1228 | 5eb7995e | j_mayer | ret = -1;
|
1229 | 6f2d8978 | j_mayer | raddr = (target_phys_addr_t)-1ULL;
|
1230 | 5eb7995e | j_mayer | for (i = 0; i < env->nb_tlb; i++) { |
1231 | 5eb7995e | j_mayer | tlb = &env->tlb[i].tlbe; |
1232 | 5eb7995e | j_mayer | if (ppcemb_tlb_check(env, tlb, &raddr, address,
|
1233 | 5eb7995e | j_mayer | env->spr[SPR_BOOKE_PID], 1, i) < 0) |
1234 | 5eb7995e | j_mayer | continue;
|
1235 | 0411a972 | j_mayer | if (msr_pr != 0) |
1236 | 5eb7995e | j_mayer | prot = tlb->prot & 0xF;
|
1237 | 5eb7995e | j_mayer | else
|
1238 | 5eb7995e | j_mayer | prot = (tlb->prot >> 4) & 0xF; |
1239 | 5eb7995e | j_mayer | /* Check the address space */
|
1240 | 5eb7995e | j_mayer | if (access_type == ACCESS_CODE) {
|
1241 | d26bfc9a | j_mayer | if (msr_ir != (tlb->attr & 1)) |
1242 | 5eb7995e | j_mayer | continue;
|
1243 | 5eb7995e | j_mayer | ctx->prot = prot; |
1244 | 5eb7995e | j_mayer | if (prot & PAGE_EXEC) {
|
1245 | 5eb7995e | j_mayer | ret = 0;
|
1246 | 5eb7995e | j_mayer | break;
|
1247 | 5eb7995e | j_mayer | } |
1248 | 5eb7995e | j_mayer | ret = -3;
|
1249 | 5eb7995e | j_mayer | } else {
|
1250 | d26bfc9a | j_mayer | if (msr_dr != (tlb->attr & 1)) |
1251 | 5eb7995e | j_mayer | continue;
|
1252 | 5eb7995e | j_mayer | ctx->prot = prot; |
1253 | 5eb7995e | j_mayer | if ((!rw && prot & PAGE_READ) || (rw && (prot & PAGE_WRITE))) {
|
1254 | 5eb7995e | j_mayer | ret = 0;
|
1255 | 5eb7995e | j_mayer | break;
|
1256 | 5eb7995e | j_mayer | } |
1257 | 5eb7995e | j_mayer | ret = -2;
|
1258 | 5eb7995e | j_mayer | } |
1259 | 5eb7995e | j_mayer | } |
1260 | 5eb7995e | j_mayer | if (ret >= 0) |
1261 | 5eb7995e | j_mayer | ctx->raddr = raddr; |
1262 | 5eb7995e | j_mayer | |
1263 | 5eb7995e | j_mayer | return ret;
|
1264 | 5eb7995e | j_mayer | } |
1265 | 5eb7995e | j_mayer | |
1266 | a11b8151 | j_mayer | static always_inline int check_physical (CPUState *env, mmu_ctx_t *ctx, |
1267 | a11b8151 | j_mayer | target_ulong eaddr, int rw)
|
1268 | 76a66253 | j_mayer | { |
1269 | 76a66253 | j_mayer | int in_plb, ret;
|
1270 | 3b46e624 | ths | |
1271 | 76a66253 | j_mayer | ctx->raddr = eaddr; |
1272 | b227a8e9 | j_mayer | ctx->prot = PAGE_READ | PAGE_EXEC; |
1273 | 76a66253 | j_mayer | ret = 0;
|
1274 | a750fc0b | j_mayer | switch (env->mmu_model) {
|
1275 | a750fc0b | j_mayer | case POWERPC_MMU_32B:
|
1276 | faadf50e | j_mayer | case POWERPC_MMU_601:
|
1277 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1278 | 7dbe11ac | j_mayer | case POWERPC_MMU_SOFT_74xx:
|
1279 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1280 | b4095fed | j_mayer | case POWERPC_MMU_REAL:
|
1281 | 7dbe11ac | j_mayer | case POWERPC_MMU_BOOKE:
|
1282 | caa4039c | j_mayer | ctx->prot |= PAGE_WRITE; |
1283 | caa4039c | j_mayer | break;
|
1284 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
1285 | add78955 | j_mayer | case POWERPC_MMU_620:
|
1286 | a750fc0b | j_mayer | case POWERPC_MMU_64B:
|
1287 | caa4039c | j_mayer | /* Real address are 60 bits long */
|
1288 | a750fc0b | j_mayer | ctx->raddr &= 0x0FFFFFFFFFFFFFFFULL;
|
1289 | caa4039c | j_mayer | ctx->prot |= PAGE_WRITE; |
1290 | caa4039c | j_mayer | break;
|
1291 | 9706285b | j_mayer | #endif
|
1292 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1293 | caa4039c | j_mayer | if (unlikely(msr_pe != 0)) { |
1294 | caa4039c | j_mayer | /* 403 family add some particular protections,
|
1295 | caa4039c | j_mayer | * using PBL/PBU registers for accesses with no translation.
|
1296 | caa4039c | j_mayer | */
|
1297 | caa4039c | j_mayer | in_plb = |
1298 | caa4039c | j_mayer | /* Check PLB validity */
|
1299 | caa4039c | j_mayer | (env->pb[0] < env->pb[1] && |
1300 | caa4039c | j_mayer | /* and address in plb area */
|
1301 | caa4039c | j_mayer | eaddr >= env->pb[0] && eaddr < env->pb[1]) || |
1302 | caa4039c | j_mayer | (env->pb[2] < env->pb[3] && |
1303 | caa4039c | j_mayer | eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0; |
1304 | caa4039c | j_mayer | if (in_plb ^ msr_px) {
|
1305 | caa4039c | j_mayer | /* Access in protected area */
|
1306 | caa4039c | j_mayer | if (rw == 1) { |
1307 | caa4039c | j_mayer | /* Access is not allowed */
|
1308 | caa4039c | j_mayer | ret = -2;
|
1309 | caa4039c | j_mayer | } |
1310 | caa4039c | j_mayer | } else {
|
1311 | caa4039c | j_mayer | /* Read-write access is allowed */
|
1312 | caa4039c | j_mayer | ctx->prot |= PAGE_WRITE; |
1313 | 76a66253 | j_mayer | } |
1314 | 76a66253 | j_mayer | } |
1315 | e1833e1f | j_mayer | break;
|
1316 | b4095fed | j_mayer | case POWERPC_MMU_MPC8xx:
|
1317 | b4095fed | j_mayer | /* XXX: TODO */
|
1318 | b4095fed | j_mayer | cpu_abort(env, "MPC8xx MMU model is not implemented\n");
|
1319 | b4095fed | j_mayer | break;
|
1320 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1321 | caa4039c | j_mayer | /* XXX: TODO */
|
1322 | caa4039c | j_mayer | cpu_abort(env, "BookE FSL MMU model not implemented\n");
|
1323 | caa4039c | j_mayer | break;
|
1324 | caa4039c | j_mayer | default:
|
1325 | caa4039c | j_mayer | cpu_abort(env, "Unknown or invalid MMU model\n");
|
1326 | caa4039c | j_mayer | return -1; |
1327 | 76a66253 | j_mayer | } |
1328 | 76a66253 | j_mayer | |
1329 | 76a66253 | j_mayer | return ret;
|
1330 | 76a66253 | j_mayer | } |
1331 | 76a66253 | j_mayer | |
1332 | 76a66253 | j_mayer | int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
|
1333 | faadf50e | j_mayer | int rw, int access_type) |
1334 | 9a64fbe4 | bellard | { |
1335 | 9a64fbe4 | bellard | int ret;
|
1336 | 0411a972 | j_mayer | |
1337 | 514fb8c1 | bellard | #if 0
|
1338 | 4a057712 | j_mayer | if (loglevel != 0) {
|
1339 | 9a64fbe4 | bellard | fprintf(logfile, "%s\n", __func__);
|
1340 | 9a64fbe4 | bellard | }
|
1341 | d9bce9d9 | j_mayer | #endif
|
1342 | 4b3686fa | bellard | if ((access_type == ACCESS_CODE && msr_ir == 0) || |
1343 | 4b3686fa | bellard | (access_type != ACCESS_CODE && msr_dr == 0)) {
|
1344 | 9a64fbe4 | bellard | /* No address translation */
|
1345 | 76a66253 | j_mayer | ret = check_physical(env, ctx, eaddr, rw); |
1346 | 9a64fbe4 | bellard | } else {
|
1347 | c55e9aef | j_mayer | ret = -1;
|
1348 | a750fc0b | j_mayer | switch (env->mmu_model) {
|
1349 | a750fc0b | j_mayer | case POWERPC_MMU_32B:
|
1350 | faadf50e | j_mayer | case POWERPC_MMU_601:
|
1351 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1352 | 7dbe11ac | j_mayer | case POWERPC_MMU_SOFT_74xx:
|
1353 | c55e9aef | j_mayer | #if defined(TARGET_PPC64)
|
1354 | add78955 | j_mayer | case POWERPC_MMU_620:
|
1355 | a750fc0b | j_mayer | case POWERPC_MMU_64B:
|
1356 | c55e9aef | j_mayer | #endif
|
1357 | faadf50e | j_mayer | /* Try to find a BAT */
|
1358 | faadf50e | j_mayer | if (env->nb_BATs != 0) |
1359 | faadf50e | j_mayer | ret = get_bat(env, ctx, eaddr, rw, access_type); |
1360 | a8dea12f | j_mayer | if (ret < 0) { |
1361 | c55e9aef | j_mayer | /* We didn't match any BAT entry or don't have BATs */
|
1362 | a8dea12f | j_mayer | ret = get_segment(env, ctx, eaddr, rw, access_type); |
1363 | a8dea12f | j_mayer | } |
1364 | a8dea12f | j_mayer | break;
|
1365 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1366 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1367 | 36081602 | j_mayer | ret = mmu40x_get_physical_address(env, ctx, eaddr, |
1368 | a8dea12f | j_mayer | rw, access_type); |
1369 | a8dea12f | j_mayer | break;
|
1370 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE:
|
1371 | 5eb7995e | j_mayer | ret = mmubooke_get_physical_address(env, ctx, eaddr, |
1372 | 5eb7995e | j_mayer | rw, access_type); |
1373 | 5eb7995e | j_mayer | break;
|
1374 | b4095fed | j_mayer | case POWERPC_MMU_MPC8xx:
|
1375 | b4095fed | j_mayer | /* XXX: TODO */
|
1376 | b4095fed | j_mayer | cpu_abort(env, "MPC8xx MMU model is not implemented\n");
|
1377 | b4095fed | j_mayer | break;
|
1378 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1379 | c55e9aef | j_mayer | /* XXX: TODO */
|
1380 | c55e9aef | j_mayer | cpu_abort(env, "BookE FSL MMU model not implemented\n");
|
1381 | c55e9aef | j_mayer | return -1; |
1382 | b4095fed | j_mayer | case POWERPC_MMU_REAL:
|
1383 | b4095fed | j_mayer | cpu_abort(env, "PowerPC in real mode do not do any translation\n");
|
1384 | 2662a059 | j_mayer | return -1; |
1385 | c55e9aef | j_mayer | default:
|
1386 | c55e9aef | j_mayer | cpu_abort(env, "Unknown or invalid MMU model\n");
|
1387 | a8dea12f | j_mayer | return -1; |
1388 | 9a64fbe4 | bellard | } |
1389 | 9a64fbe4 | bellard | } |
1390 | 514fb8c1 | bellard | #if 0
|
1391 | 4a057712 | j_mayer | if (loglevel != 0) {
|
1392 | 4a057712 | j_mayer | fprintf(logfile, "%s address " ADDRX " => %d " PADDRX "\n",
|
1393 | c55e9aef | j_mayer | __func__, eaddr, ret, ctx->raddr);
|
1394 | a541f297 | bellard | }
|
1395 | 76a66253 | j_mayer | #endif
|
1396 | d9bce9d9 | j_mayer | |
1397 | 9a64fbe4 | bellard | return ret;
|
1398 | 9a64fbe4 | bellard | } |
1399 | 9a64fbe4 | bellard | |
1400 | 9b3c35e0 | j_mayer | target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr) |
1401 | a6b025d3 | bellard | { |
1402 | 76a66253 | j_mayer | mmu_ctx_t ctx; |
1403 | a6b025d3 | bellard | |
1404 | faadf50e | j_mayer | if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT) != 0)) |
1405 | a6b025d3 | bellard | return -1; |
1406 | 76a66253 | j_mayer | |
1407 | 76a66253 | j_mayer | return ctx.raddr & TARGET_PAGE_MASK;
|
1408 | a6b025d3 | bellard | } |
1409 | 9a64fbe4 | bellard | |
1410 | 9a64fbe4 | bellard | /* Perform address translation */
|
1411 | e96efcfc | j_mayer | int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
1412 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
1413 | 9a64fbe4 | bellard | { |
1414 | 76a66253 | j_mayer | mmu_ctx_t ctx; |
1415 | a541f297 | bellard | int access_type;
|
1416 | 9a64fbe4 | bellard | int ret = 0; |
1417 | d9bce9d9 | j_mayer | |
1418 | b769d8fe | bellard | if (rw == 2) { |
1419 | b769d8fe | bellard | /* code access */
|
1420 | b769d8fe | bellard | rw = 0;
|
1421 | b769d8fe | bellard | access_type = ACCESS_CODE; |
1422 | b769d8fe | bellard | } else {
|
1423 | b769d8fe | bellard | /* data access */
|
1424 | b4cec7b4 | aurel32 | access_type = env->access_type; |
1425 | b769d8fe | bellard | } |
1426 | faadf50e | j_mayer | ret = get_physical_address(env, &ctx, address, rw, access_type); |
1427 | 9a64fbe4 | bellard | if (ret == 0) { |
1428 | b227a8e9 | j_mayer | ret = tlb_set_page_exec(env, address & TARGET_PAGE_MASK, |
1429 | b227a8e9 | j_mayer | ctx.raddr & TARGET_PAGE_MASK, ctx.prot, |
1430 | b227a8e9 | j_mayer | mmu_idx, is_softmmu); |
1431 | 9a64fbe4 | bellard | } else if (ret < 0) { |
1432 | d12d51d5 | aliguori | LOG_MMU_STATE(env); |
1433 | 9a64fbe4 | bellard | if (access_type == ACCESS_CODE) {
|
1434 | 9a64fbe4 | bellard | switch (ret) {
|
1435 | 9a64fbe4 | bellard | case -1: |
1436 | 76a66253 | j_mayer | /* No matches in page tables or TLB */
|
1437 | a750fc0b | j_mayer | switch (env->mmu_model) {
|
1438 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1439 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_IFTLB; |
1440 | 8f793433 | j_mayer | env->error_code = 1 << 18; |
1441 | 76a66253 | j_mayer | env->spr[SPR_IMISS] = address; |
1442 | 76a66253 | j_mayer | env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
|
1443 | 76a66253 | j_mayer | goto tlb_miss;
|
1444 | 7dbe11ac | j_mayer | case POWERPC_MMU_SOFT_74xx:
|
1445 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_IFTLB; |
1446 | 7dbe11ac | j_mayer | goto tlb_miss_74xx;
|
1447 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1448 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1449 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ITLB; |
1450 | 8f793433 | j_mayer | env->error_code = 0;
|
1451 | a8dea12f | j_mayer | env->spr[SPR_40x_DEAR] = address; |
1452 | a8dea12f | j_mayer | env->spr[SPR_40x_ESR] = 0x00000000;
|
1453 | c55e9aef | j_mayer | break;
|
1454 | a750fc0b | j_mayer | case POWERPC_MMU_32B:
|
1455 | faadf50e | j_mayer | case POWERPC_MMU_601:
|
1456 | c55e9aef | j_mayer | #if defined(TARGET_PPC64)
|
1457 | add78955 | j_mayer | case POWERPC_MMU_620:
|
1458 | a750fc0b | j_mayer | case POWERPC_MMU_64B:
|
1459 | c55e9aef | j_mayer | #endif
|
1460 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ISI; |
1461 | 8f793433 | j_mayer | env->error_code = 0x40000000;
|
1462 | 8f793433 | j_mayer | break;
|
1463 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE:
|
1464 | c55e9aef | j_mayer | /* XXX: TODO */
|
1465 | b4095fed | j_mayer | cpu_abort(env, "BookE MMU model is not implemented\n");
|
1466 | c55e9aef | j_mayer | return -1; |
1467 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1468 | c55e9aef | j_mayer | /* XXX: TODO */
|
1469 | b4095fed | j_mayer | cpu_abort(env, "BookE FSL MMU model is not implemented\n");
|
1470 | c55e9aef | j_mayer | return -1; |
1471 | b4095fed | j_mayer | case POWERPC_MMU_MPC8xx:
|
1472 | b4095fed | j_mayer | /* XXX: TODO */
|
1473 | b4095fed | j_mayer | cpu_abort(env, "MPC8xx MMU model is not implemented\n");
|
1474 | b4095fed | j_mayer | break;
|
1475 | b4095fed | j_mayer | case POWERPC_MMU_REAL:
|
1476 | b4095fed | j_mayer | cpu_abort(env, "PowerPC in real mode should never raise "
|
1477 | b4095fed | j_mayer | "any MMU exceptions\n");
|
1478 | 2662a059 | j_mayer | return -1; |
1479 | c55e9aef | j_mayer | default:
|
1480 | c55e9aef | j_mayer | cpu_abort(env, "Unknown or invalid MMU model\n");
|
1481 | c55e9aef | j_mayer | return -1; |
1482 | 76a66253 | j_mayer | } |
1483 | 9a64fbe4 | bellard | break;
|
1484 | 9a64fbe4 | bellard | case -2: |
1485 | 9a64fbe4 | bellard | /* Access rights violation */
|
1486 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ISI; |
1487 | 8f793433 | j_mayer | env->error_code = 0x08000000;
|
1488 | 9a64fbe4 | bellard | break;
|
1489 | 9a64fbe4 | bellard | case -3: |
1490 | 76a66253 | j_mayer | /* No execute protection violation */
|
1491 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ISI; |
1492 | 8f793433 | j_mayer | env->error_code = 0x10000000;
|
1493 | 9a64fbe4 | bellard | break;
|
1494 | 9a64fbe4 | bellard | case -4: |
1495 | 9a64fbe4 | bellard | /* Direct store exception */
|
1496 | 9a64fbe4 | bellard | /* No code fetch is allowed in direct-store areas */
|
1497 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ISI; |
1498 | 8f793433 | j_mayer | env->error_code = 0x10000000;
|
1499 | 2be0071f | bellard | break;
|
1500 | e1833e1f | j_mayer | #if defined(TARGET_PPC64)
|
1501 | 2be0071f | bellard | case -5: |
1502 | 2be0071f | bellard | /* No match in segment table */
|
1503 | add78955 | j_mayer | if (env->mmu_model == POWERPC_MMU_620) {
|
1504 | add78955 | j_mayer | env->exception_index = POWERPC_EXCP_ISI; |
1505 | add78955 | j_mayer | /* XXX: this might be incorrect */
|
1506 | add78955 | j_mayer | env->error_code = 0x40000000;
|
1507 | add78955 | j_mayer | } else {
|
1508 | add78955 | j_mayer | env->exception_index = POWERPC_EXCP_ISEG; |
1509 | add78955 | j_mayer | env->error_code = 0;
|
1510 | add78955 | j_mayer | } |
1511 | 9a64fbe4 | bellard | break;
|
1512 | e1833e1f | j_mayer | #endif
|
1513 | 9a64fbe4 | bellard | } |
1514 | 9a64fbe4 | bellard | } else {
|
1515 | 9a64fbe4 | bellard | switch (ret) {
|
1516 | 9a64fbe4 | bellard | case -1: |
1517 | 76a66253 | j_mayer | /* No matches in page tables or TLB */
|
1518 | a750fc0b | j_mayer | switch (env->mmu_model) {
|
1519 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1520 | 76a66253 | j_mayer | if (rw == 1) { |
1521 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSTLB; |
1522 | 8f793433 | j_mayer | env->error_code = 1 << 16; |
1523 | 76a66253 | j_mayer | } else {
|
1524 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DLTLB; |
1525 | 8f793433 | j_mayer | env->error_code = 0;
|
1526 | 76a66253 | j_mayer | } |
1527 | 76a66253 | j_mayer | env->spr[SPR_DMISS] = address; |
1528 | 76a66253 | j_mayer | env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
|
1529 | 76a66253 | j_mayer | tlb_miss:
|
1530 | 8f793433 | j_mayer | env->error_code |= ctx.key << 19;
|
1531 | 76a66253 | j_mayer | env->spr[SPR_HASH1] = ctx.pg_addr[0];
|
1532 | 76a66253 | j_mayer | env->spr[SPR_HASH2] = ctx.pg_addr[1];
|
1533 | 8f793433 | j_mayer | break;
|
1534 | 7dbe11ac | j_mayer | case POWERPC_MMU_SOFT_74xx:
|
1535 | 7dbe11ac | j_mayer | if (rw == 1) { |
1536 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSTLB; |
1537 | 7dbe11ac | j_mayer | } else {
|
1538 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DLTLB; |
1539 | 7dbe11ac | j_mayer | } |
1540 | 7dbe11ac | j_mayer | tlb_miss_74xx:
|
1541 | 7dbe11ac | j_mayer | /* Implement LRU algorithm */
|
1542 | 8f793433 | j_mayer | env->error_code = ctx.key << 19;
|
1543 | 7dbe11ac | j_mayer | env->spr[SPR_TLBMISS] = (address & ~((target_ulong)0x3)) |
|
1544 | 7dbe11ac | j_mayer | ((env->last_way + 1) & (env->nb_ways - 1)); |
1545 | 7dbe11ac | j_mayer | env->spr[SPR_PTEHI] = 0x80000000 | ctx.ptem;
|
1546 | 7dbe11ac | j_mayer | break;
|
1547 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1548 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1549 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DTLB; |
1550 | 8f793433 | j_mayer | env->error_code = 0;
|
1551 | a8dea12f | j_mayer | env->spr[SPR_40x_DEAR] = address; |
1552 | a8dea12f | j_mayer | if (rw)
|
1553 | a8dea12f | j_mayer | env->spr[SPR_40x_ESR] = 0x00800000;
|
1554 | a8dea12f | j_mayer | else
|
1555 | a8dea12f | j_mayer | env->spr[SPR_40x_ESR] = 0x00000000;
|
1556 | c55e9aef | j_mayer | break;
|
1557 | a750fc0b | j_mayer | case POWERPC_MMU_32B:
|
1558 | faadf50e | j_mayer | case POWERPC_MMU_601:
|
1559 | c55e9aef | j_mayer | #if defined(TARGET_PPC64)
|
1560 | add78955 | j_mayer | case POWERPC_MMU_620:
|
1561 | a750fc0b | j_mayer | case POWERPC_MMU_64B:
|
1562 | c55e9aef | j_mayer | #endif
|
1563 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSI; |
1564 | 8f793433 | j_mayer | env->error_code = 0;
|
1565 | 8f793433 | j_mayer | env->spr[SPR_DAR] = address; |
1566 | 8f793433 | j_mayer | if (rw == 1) |
1567 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x42000000;
|
1568 | 8f793433 | j_mayer | else
|
1569 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x40000000;
|
1570 | 8f793433 | j_mayer | break;
|
1571 | b4095fed | j_mayer | case POWERPC_MMU_MPC8xx:
|
1572 | b4095fed | j_mayer | /* XXX: TODO */
|
1573 | b4095fed | j_mayer | cpu_abort(env, "MPC8xx MMU model is not implemented\n");
|
1574 | b4095fed | j_mayer | break;
|
1575 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE:
|
1576 | c55e9aef | j_mayer | /* XXX: TODO */
|
1577 | b4095fed | j_mayer | cpu_abort(env, "BookE MMU model is not implemented\n");
|
1578 | c55e9aef | j_mayer | return -1; |
1579 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1580 | c55e9aef | j_mayer | /* XXX: TODO */
|
1581 | b4095fed | j_mayer | cpu_abort(env, "BookE FSL MMU model is not implemented\n");
|
1582 | c55e9aef | j_mayer | return -1; |
1583 | b4095fed | j_mayer | case POWERPC_MMU_REAL:
|
1584 | b4095fed | j_mayer | cpu_abort(env, "PowerPC in real mode should never raise "
|
1585 | b4095fed | j_mayer | "any MMU exceptions\n");
|
1586 | 2662a059 | j_mayer | return -1; |
1587 | c55e9aef | j_mayer | default:
|
1588 | c55e9aef | j_mayer | cpu_abort(env, "Unknown or invalid MMU model\n");
|
1589 | c55e9aef | j_mayer | return -1; |
1590 | 76a66253 | j_mayer | } |
1591 | 9a64fbe4 | bellard | break;
|
1592 | 9a64fbe4 | bellard | case -2: |
1593 | 9a64fbe4 | bellard | /* Access rights violation */
|
1594 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSI; |
1595 | 8f793433 | j_mayer | env->error_code = 0;
|
1596 | 8f793433 | j_mayer | env->spr[SPR_DAR] = address; |
1597 | 8f793433 | j_mayer | if (rw == 1) |
1598 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x0A000000;
|
1599 | 8f793433 | j_mayer | else
|
1600 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x08000000;
|
1601 | 9a64fbe4 | bellard | break;
|
1602 | 9a64fbe4 | bellard | case -4: |
1603 | 9a64fbe4 | bellard | /* Direct store exception */
|
1604 | 9a64fbe4 | bellard | switch (access_type) {
|
1605 | 9a64fbe4 | bellard | case ACCESS_FLOAT:
|
1606 | 9a64fbe4 | bellard | /* Floating point load/store */
|
1607 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ALIGN; |
1608 | 8f793433 | j_mayer | env->error_code = POWERPC_EXCP_ALIGN_FP; |
1609 | 8f793433 | j_mayer | env->spr[SPR_DAR] = address; |
1610 | 9a64fbe4 | bellard | break;
|
1611 | 9a64fbe4 | bellard | case ACCESS_RES:
|
1612 | 8f793433 | j_mayer | /* lwarx, ldarx or stwcx. */
|
1613 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSI; |
1614 | 8f793433 | j_mayer | env->error_code = 0;
|
1615 | 8f793433 | j_mayer | env->spr[SPR_DAR] = address; |
1616 | 8f793433 | j_mayer | if (rw == 1) |
1617 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x06000000;
|
1618 | 8f793433 | j_mayer | else
|
1619 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x04000000;
|
1620 | 9a64fbe4 | bellard | break;
|
1621 | 9a64fbe4 | bellard | case ACCESS_EXT:
|
1622 | 9a64fbe4 | bellard | /* eciwx or ecowx */
|
1623 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSI; |
1624 | 8f793433 | j_mayer | env->error_code = 0;
|
1625 | 8f793433 | j_mayer | env->spr[SPR_DAR] = address; |
1626 | 8f793433 | j_mayer | if (rw == 1) |
1627 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x06100000;
|
1628 | 8f793433 | j_mayer | else
|
1629 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x04100000;
|
1630 | 9a64fbe4 | bellard | break;
|
1631 | 9a64fbe4 | bellard | default:
|
1632 | 76a66253 | j_mayer | printf("DSI: invalid exception (%d)\n", ret);
|
1633 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_PROGRAM; |
1634 | 8f793433 | j_mayer | env->error_code = |
1635 | 8f793433 | j_mayer | POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL; |
1636 | 8f793433 | j_mayer | env->spr[SPR_DAR] = address; |
1637 | 9a64fbe4 | bellard | break;
|
1638 | 9a64fbe4 | bellard | } |
1639 | fdabc366 | bellard | break;
|
1640 | e1833e1f | j_mayer | #if defined(TARGET_PPC64)
|
1641 | 2be0071f | bellard | case -5: |
1642 | 2be0071f | bellard | /* No match in segment table */
|
1643 | add78955 | j_mayer | if (env->mmu_model == POWERPC_MMU_620) {
|
1644 | add78955 | j_mayer | env->exception_index = POWERPC_EXCP_DSI; |
1645 | add78955 | j_mayer | env->error_code = 0;
|
1646 | add78955 | j_mayer | env->spr[SPR_DAR] = address; |
1647 | add78955 | j_mayer | /* XXX: this might be incorrect */
|
1648 | add78955 | j_mayer | if (rw == 1) |
1649 | add78955 | j_mayer | env->spr[SPR_DSISR] = 0x42000000;
|
1650 | add78955 | j_mayer | else
|
1651 | add78955 | j_mayer | env->spr[SPR_DSISR] = 0x40000000;
|
1652 | add78955 | j_mayer | } else {
|
1653 | add78955 | j_mayer | env->exception_index = POWERPC_EXCP_DSEG; |
1654 | add78955 | j_mayer | env->error_code = 0;
|
1655 | add78955 | j_mayer | env->spr[SPR_DAR] = address; |
1656 | add78955 | j_mayer | } |
1657 | 2be0071f | bellard | break;
|
1658 | e1833e1f | j_mayer | #endif
|
1659 | 9a64fbe4 | bellard | } |
1660 | 9a64fbe4 | bellard | } |
1661 | 9a64fbe4 | bellard | #if 0
|
1662 | 8f793433 | j_mayer | printf("%s: set exception to %d %02x\n", __func__,
|
1663 | 8f793433 | j_mayer | env->exception, env->error_code);
|
1664 | 9a64fbe4 | bellard | #endif
|
1665 | 9a64fbe4 | bellard | ret = 1;
|
1666 | 9a64fbe4 | bellard | } |
1667 | 76a66253 | j_mayer | |
1668 | 9a64fbe4 | bellard | return ret;
|
1669 | 9a64fbe4 | bellard | } |
1670 | 9a64fbe4 | bellard | |
1671 | 3fc6c082 | bellard | /*****************************************************************************/
|
1672 | 3fc6c082 | bellard | /* BATs management */
|
1673 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS)
|
1674 | b068d6a7 | j_mayer | static always_inline void do_invalidate_BAT (CPUPPCState *env, |
1675 | b068d6a7 | j_mayer | target_ulong BATu, |
1676 | b068d6a7 | j_mayer | target_ulong mask) |
1677 | 3fc6c082 | bellard | { |
1678 | 3fc6c082 | bellard | target_ulong base, end, page; |
1679 | 76a66253 | j_mayer | |
1680 | 3fc6c082 | bellard | base = BATu & ~0x0001FFFF;
|
1681 | 3fc6c082 | bellard | end = base + mask + 0x00020000;
|
1682 | d12d51d5 | aliguori | LOG_BATS("Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n", |
1683 | 76a66253 | j_mayer | base, end, mask); |
1684 | 3fc6c082 | bellard | for (page = base; page != end; page += TARGET_PAGE_SIZE)
|
1685 | 3fc6c082 | bellard | tlb_flush_page(env, page); |
1686 | d12d51d5 | aliguori | LOG_BATS("Flush done\n");
|
1687 | 3fc6c082 | bellard | } |
1688 | 3fc6c082 | bellard | #endif
|
1689 | 3fc6c082 | bellard | |
1690 | b068d6a7 | j_mayer | static always_inline void dump_store_bat (CPUPPCState *env, char ID, |
1691 | b068d6a7 | j_mayer | int ul, int nr, target_ulong value) |
1692 | 3fc6c082 | bellard | { |
1693 | d12d51d5 | aliguori | LOG_BATS("Set %cBAT%d%c to " ADDRX " (" ADDRX ")\n", |
1694 | 1b9eb036 | j_mayer | ID, nr, ul == 0 ? 'u' : 'l', value, env->nip); |
1695 | 3fc6c082 | bellard | } |
1696 | 3fc6c082 | bellard | |
1697 | 45d827d2 | aurel32 | void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value) |
1698 | 3fc6c082 | bellard | { |
1699 | 3fc6c082 | bellard | target_ulong mask; |
1700 | 3fc6c082 | bellard | |
1701 | 3fc6c082 | bellard | dump_store_bat(env, 'I', 0, nr, value); |
1702 | 3fc6c082 | bellard | if (env->IBAT[0][nr] != value) { |
1703 | 3fc6c082 | bellard | mask = (value << 15) & 0x0FFE0000UL; |
1704 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS)
|
1705 | 3fc6c082 | bellard | do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
1706 | 3fc6c082 | bellard | #endif
|
1707 | 3fc6c082 | bellard | /* When storing valid upper BAT, mask BEPI and BRPN
|
1708 | 3fc6c082 | bellard | * and invalidate all TLBs covered by this BAT
|
1709 | 3fc6c082 | bellard | */
|
1710 | 3fc6c082 | bellard | mask = (value << 15) & 0x0FFE0000UL; |
1711 | 3fc6c082 | bellard | env->IBAT[0][nr] = (value & 0x00001FFFUL) | |
1712 | 3fc6c082 | bellard | (value & ~0x0001FFFFUL & ~mask);
|
1713 | 3fc6c082 | bellard | env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) | |
1714 | 3fc6c082 | bellard | (env->IBAT[1][nr] & ~0x0001FFFF & ~mask); |
1715 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS)
|
1716 | 3fc6c082 | bellard | do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
1717 | 76a66253 | j_mayer | #else
|
1718 | 3fc6c082 | bellard | tlb_flush(env, 1);
|
1719 | 3fc6c082 | bellard | #endif
|
1720 | 3fc6c082 | bellard | } |
1721 | 3fc6c082 | bellard | } |
1722 | 3fc6c082 | bellard | |
1723 | 45d827d2 | aurel32 | void ppc_store_ibatl (CPUPPCState *env, int nr, target_ulong value) |
1724 | 3fc6c082 | bellard | { |
1725 | 3fc6c082 | bellard | dump_store_bat(env, 'I', 1, nr, value); |
1726 | 3fc6c082 | bellard | env->IBAT[1][nr] = value;
|
1727 | 3fc6c082 | bellard | } |
1728 | 3fc6c082 | bellard | |
1729 | 45d827d2 | aurel32 | void ppc_store_dbatu (CPUPPCState *env, int nr, target_ulong value) |
1730 | 3fc6c082 | bellard | { |
1731 | 3fc6c082 | bellard | target_ulong mask; |
1732 | 3fc6c082 | bellard | |
1733 | 3fc6c082 | bellard | dump_store_bat(env, 'D', 0, nr, value); |
1734 | 3fc6c082 | bellard | if (env->DBAT[0][nr] != value) { |
1735 | 3fc6c082 | bellard | /* When storing valid upper BAT, mask BEPI and BRPN
|
1736 | 3fc6c082 | bellard | * and invalidate all TLBs covered by this BAT
|
1737 | 3fc6c082 | bellard | */
|
1738 | 3fc6c082 | bellard | mask = (value << 15) & 0x0FFE0000UL; |
1739 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS)
|
1740 | 3fc6c082 | bellard | do_invalidate_BAT(env, env->DBAT[0][nr], mask);
|
1741 | 3fc6c082 | bellard | #endif
|
1742 | 3fc6c082 | bellard | mask = (value << 15) & 0x0FFE0000UL; |
1743 | 3fc6c082 | bellard | env->DBAT[0][nr] = (value & 0x00001FFFUL) | |
1744 | 3fc6c082 | bellard | (value & ~0x0001FFFFUL & ~mask);
|
1745 | 3fc6c082 | bellard | env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) | |
1746 | 3fc6c082 | bellard | (env->DBAT[1][nr] & ~0x0001FFFF & ~mask); |
1747 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS)
|
1748 | 3fc6c082 | bellard | do_invalidate_BAT(env, env->DBAT[0][nr], mask);
|
1749 | 3fc6c082 | bellard | #else
|
1750 | 3fc6c082 | bellard | tlb_flush(env, 1);
|
1751 | 3fc6c082 | bellard | #endif
|
1752 | 3fc6c082 | bellard | } |
1753 | 3fc6c082 | bellard | } |
1754 | 3fc6c082 | bellard | |
1755 | 45d827d2 | aurel32 | void ppc_store_dbatl (CPUPPCState *env, int nr, target_ulong value) |
1756 | 3fc6c082 | bellard | { |
1757 | 3fc6c082 | bellard | dump_store_bat(env, 'D', 1, nr, value); |
1758 | 3fc6c082 | bellard | env->DBAT[1][nr] = value;
|
1759 | 3fc6c082 | bellard | } |
1760 | 3fc6c082 | bellard | |
1761 | 45d827d2 | aurel32 | void ppc_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value) |
1762 | 056401ea | j_mayer | { |
1763 | 056401ea | j_mayer | target_ulong mask; |
1764 | 056401ea | j_mayer | int do_inval;
|
1765 | 056401ea | j_mayer | |
1766 | 056401ea | j_mayer | dump_store_bat(env, 'I', 0, nr, value); |
1767 | 056401ea | j_mayer | if (env->IBAT[0][nr] != value) { |
1768 | 056401ea | j_mayer | do_inval = 0;
|
1769 | 056401ea | j_mayer | mask = (env->IBAT[1][nr] << 17) & 0x0FFE0000UL; |
1770 | 056401ea | j_mayer | if (env->IBAT[1][nr] & 0x40) { |
1771 | 056401ea | j_mayer | /* Invalidate BAT only if it is valid */
|
1772 | 056401ea | j_mayer | #if !defined(FLUSH_ALL_TLBS)
|
1773 | 056401ea | j_mayer | do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
1774 | 056401ea | j_mayer | #else
|
1775 | 056401ea | j_mayer | do_inval = 1;
|
1776 | 056401ea | j_mayer | #endif
|
1777 | 056401ea | j_mayer | } |
1778 | 056401ea | j_mayer | /* When storing valid upper BAT, mask BEPI and BRPN
|
1779 | 056401ea | j_mayer | * and invalidate all TLBs covered by this BAT
|
1780 | 056401ea | j_mayer | */
|
1781 | 056401ea | j_mayer | env->IBAT[0][nr] = (value & 0x00001FFFUL) | |
1782 | 056401ea | j_mayer | (value & ~0x0001FFFFUL & ~mask);
|
1783 | 056401ea | j_mayer | env->DBAT[0][nr] = env->IBAT[0][nr]; |
1784 | 056401ea | j_mayer | if (env->IBAT[1][nr] & 0x40) { |
1785 | 056401ea | j_mayer | #if !defined(FLUSH_ALL_TLBS)
|
1786 | 056401ea | j_mayer | do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
1787 | 056401ea | j_mayer | #else
|
1788 | 056401ea | j_mayer | do_inval = 1;
|
1789 | 056401ea | j_mayer | #endif
|
1790 | 056401ea | j_mayer | } |
1791 | 056401ea | j_mayer | #if defined(FLUSH_ALL_TLBS)
|
1792 | 056401ea | j_mayer | if (do_inval)
|
1793 | 056401ea | j_mayer | tlb_flush(env, 1);
|
1794 | 056401ea | j_mayer | #endif
|
1795 | 056401ea | j_mayer | } |
1796 | 056401ea | j_mayer | } |
1797 | 056401ea | j_mayer | |
1798 | 45d827d2 | aurel32 | void ppc_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value) |
1799 | 056401ea | j_mayer | { |
1800 | 056401ea | j_mayer | target_ulong mask; |
1801 | 056401ea | j_mayer | int do_inval;
|
1802 | 056401ea | j_mayer | |
1803 | 056401ea | j_mayer | dump_store_bat(env, 'I', 1, nr, value); |
1804 | 056401ea | j_mayer | if (env->IBAT[1][nr] != value) { |
1805 | 056401ea | j_mayer | do_inval = 0;
|
1806 | 056401ea | j_mayer | if (env->IBAT[1][nr] & 0x40) { |
1807 | 056401ea | j_mayer | #if !defined(FLUSH_ALL_TLBS)
|
1808 | 056401ea | j_mayer | mask = (env->IBAT[1][nr] << 17) & 0x0FFE0000UL; |
1809 | 056401ea | j_mayer | do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
1810 | 056401ea | j_mayer | #else
|
1811 | 056401ea | j_mayer | do_inval = 1;
|
1812 | 056401ea | j_mayer | #endif
|
1813 | 056401ea | j_mayer | } |
1814 | 056401ea | j_mayer | if (value & 0x40) { |
1815 | 056401ea | j_mayer | #if !defined(FLUSH_ALL_TLBS)
|
1816 | 056401ea | j_mayer | mask = (value << 17) & 0x0FFE0000UL; |
1817 | 056401ea | j_mayer | do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
1818 | 056401ea | j_mayer | #else
|
1819 | 056401ea | j_mayer | do_inval = 1;
|
1820 | 056401ea | j_mayer | #endif
|
1821 | 056401ea | j_mayer | } |
1822 | 056401ea | j_mayer | env->IBAT[1][nr] = value;
|
1823 | 056401ea | j_mayer | env->DBAT[1][nr] = value;
|
1824 | 056401ea | j_mayer | #if defined(FLUSH_ALL_TLBS)
|
1825 | 056401ea | j_mayer | if (do_inval)
|
1826 | 056401ea | j_mayer | tlb_flush(env, 1);
|
1827 | 056401ea | j_mayer | #endif
|
1828 | 056401ea | j_mayer | } |
1829 | 056401ea | j_mayer | } |
1830 | 056401ea | j_mayer | |
1831 | 0a032cbe | j_mayer | /*****************************************************************************/
|
1832 | 0a032cbe | j_mayer | /* TLB management */
|
1833 | 0a032cbe | j_mayer | void ppc_tlb_invalidate_all (CPUPPCState *env)
|
1834 | 0a032cbe | j_mayer | { |
1835 | daf4f96e | j_mayer | switch (env->mmu_model) {
|
1836 | daf4f96e | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1837 | 7dbe11ac | j_mayer | case POWERPC_MMU_SOFT_74xx:
|
1838 | 0a032cbe | j_mayer | ppc6xx_tlb_invalidate_all(env); |
1839 | daf4f96e | j_mayer | break;
|
1840 | daf4f96e | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1841 | daf4f96e | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1842 | 0a032cbe | j_mayer | ppc4xx_tlb_invalidate_all(env); |
1843 | daf4f96e | j_mayer | break;
|
1844 | b4095fed | j_mayer | case POWERPC_MMU_REAL:
|
1845 | 7dbe11ac | j_mayer | cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
|
1846 | 7dbe11ac | j_mayer | break;
|
1847 | b4095fed | j_mayer | case POWERPC_MMU_MPC8xx:
|
1848 | b4095fed | j_mayer | /* XXX: TODO */
|
1849 | b4095fed | j_mayer | cpu_abort(env, "MPC8xx MMU model is not implemented\n");
|
1850 | b4095fed | j_mayer | break;
|
1851 | 7dbe11ac | j_mayer | case POWERPC_MMU_BOOKE:
|
1852 | 7dbe11ac | j_mayer | /* XXX: TODO */
|
1853 | b4095fed | j_mayer | cpu_abort(env, "BookE MMU model is not implemented\n");
|
1854 | 7dbe11ac | j_mayer | break;
|
1855 | 7dbe11ac | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1856 | 7dbe11ac | j_mayer | /* XXX: TODO */
|
1857 | da07cf59 | aliguori | if (!kvm_enabled())
|
1858 | da07cf59 | aliguori | cpu_abort(env, "BookE MMU model is not implemented\n");
|
1859 | 7dbe11ac | j_mayer | break;
|
1860 | 7dbe11ac | j_mayer | case POWERPC_MMU_32B:
|
1861 | faadf50e | j_mayer | case POWERPC_MMU_601:
|
1862 | 00af685f | j_mayer | #if defined(TARGET_PPC64)
|
1863 | add78955 | j_mayer | case POWERPC_MMU_620:
|
1864 | 7dbe11ac | j_mayer | case POWERPC_MMU_64B:
|
1865 | 00af685f | j_mayer | #endif /* defined(TARGET_PPC64) */ |
1866 | 0a032cbe | j_mayer | tlb_flush(env, 1);
|
1867 | daf4f96e | j_mayer | break;
|
1868 | 00af685f | j_mayer | default:
|
1869 | 00af685f | j_mayer | /* XXX: TODO */
|
1870 | 12de9a39 | j_mayer | cpu_abort(env, "Unknown MMU model\n");
|
1871 | 00af685f | j_mayer | break;
|
1872 | 0a032cbe | j_mayer | } |
1873 | 0a032cbe | j_mayer | } |
1874 | 0a032cbe | j_mayer | |
1875 | daf4f96e | j_mayer | void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr)
|
1876 | daf4f96e | j_mayer | { |
1877 | daf4f96e | j_mayer | #if !defined(FLUSH_ALL_TLBS)
|
1878 | daf4f96e | j_mayer | addr &= TARGET_PAGE_MASK; |
1879 | daf4f96e | j_mayer | switch (env->mmu_model) {
|
1880 | daf4f96e | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1881 | 7dbe11ac | j_mayer | case POWERPC_MMU_SOFT_74xx:
|
1882 | daf4f96e | j_mayer | ppc6xx_tlb_invalidate_virt(env, addr, 0);
|
1883 | daf4f96e | j_mayer | if (env->id_tlbs == 1) |
1884 | daf4f96e | j_mayer | ppc6xx_tlb_invalidate_virt(env, addr, 1);
|
1885 | daf4f96e | j_mayer | break;
|
1886 | daf4f96e | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1887 | daf4f96e | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1888 | daf4f96e | j_mayer | ppc4xx_tlb_invalidate_virt(env, addr, env->spr[SPR_40x_PID]); |
1889 | daf4f96e | j_mayer | break;
|
1890 | b4095fed | j_mayer | case POWERPC_MMU_REAL:
|
1891 | 7dbe11ac | j_mayer | cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
|
1892 | 7dbe11ac | j_mayer | break;
|
1893 | b4095fed | j_mayer | case POWERPC_MMU_MPC8xx:
|
1894 | b4095fed | j_mayer | /* XXX: TODO */
|
1895 | b4095fed | j_mayer | cpu_abort(env, "MPC8xx MMU model is not implemented\n");
|
1896 | b4095fed | j_mayer | break;
|
1897 | 7dbe11ac | j_mayer | case POWERPC_MMU_BOOKE:
|
1898 | 7dbe11ac | j_mayer | /* XXX: TODO */
|
1899 | b4095fed | j_mayer | cpu_abort(env, "BookE MMU model is not implemented\n");
|
1900 | 7dbe11ac | j_mayer | break;
|
1901 | 7dbe11ac | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1902 | 7dbe11ac | j_mayer | /* XXX: TODO */
|
1903 | b4095fed | j_mayer | cpu_abort(env, "BookE FSL MMU model is not implemented\n");
|
1904 | 7dbe11ac | j_mayer | break;
|
1905 | 7dbe11ac | j_mayer | case POWERPC_MMU_32B:
|
1906 | faadf50e | j_mayer | case POWERPC_MMU_601:
|
1907 | daf4f96e | j_mayer | /* tlbie invalidate TLBs for all segments */
|
1908 | 6f2d8978 | j_mayer | addr &= ~((target_ulong)-1ULL << 28); |
1909 | daf4f96e | j_mayer | /* XXX: this case should be optimized,
|
1910 | daf4f96e | j_mayer | * giving a mask to tlb_flush_page
|
1911 | daf4f96e | j_mayer | */
|
1912 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x0 << 28)); |
1913 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x1 << 28)); |
1914 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x2 << 28)); |
1915 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x3 << 28)); |
1916 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x4 << 28)); |
1917 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x5 << 28)); |
1918 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x6 << 28)); |
1919 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x7 << 28)); |
1920 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x8 << 28)); |
1921 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x9 << 28)); |
1922 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0xA << 28)); |
1923 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0xB << 28)); |
1924 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0xC << 28)); |
1925 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0xD << 28)); |
1926 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0xE << 28)); |
1927 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0xF << 28)); |
1928 | 7dbe11ac | j_mayer | break;
|
1929 | 00af685f | j_mayer | #if defined(TARGET_PPC64)
|
1930 | add78955 | j_mayer | case POWERPC_MMU_620:
|
1931 | 7dbe11ac | j_mayer | case POWERPC_MMU_64B:
|
1932 | 7dbe11ac | j_mayer | /* tlbie invalidate TLBs for all segments */
|
1933 | 7dbe11ac | j_mayer | /* XXX: given the fact that there are too many segments to invalidate,
|
1934 | 00af685f | j_mayer | * and we still don't have a tlb_flush_mask(env, n, mask) in Qemu,
|
1935 | 7dbe11ac | j_mayer | * we just invalidate all TLBs
|
1936 | 7dbe11ac | j_mayer | */
|
1937 | 7dbe11ac | j_mayer | tlb_flush(env, 1);
|
1938 | 7dbe11ac | j_mayer | break;
|
1939 | 00af685f | j_mayer | #endif /* defined(TARGET_PPC64) */ |
1940 | 00af685f | j_mayer | default:
|
1941 | 00af685f | j_mayer | /* XXX: TODO */
|
1942 | 12de9a39 | j_mayer | cpu_abort(env, "Unknown MMU model\n");
|
1943 | 00af685f | j_mayer | break;
|
1944 | daf4f96e | j_mayer | } |
1945 | daf4f96e | j_mayer | #else
|
1946 | daf4f96e | j_mayer | ppc_tlb_invalidate_all(env); |
1947 | daf4f96e | j_mayer | #endif
|
1948 | daf4f96e | j_mayer | } |
1949 | daf4f96e | j_mayer | |
1950 | 3fc6c082 | bellard | /*****************************************************************************/
|
1951 | 3fc6c082 | bellard | /* Special registers manipulation */
|
1952 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1953 | d9bce9d9 | j_mayer | void ppc_store_asr (CPUPPCState *env, target_ulong value)
|
1954 | d9bce9d9 | j_mayer | { |
1955 | d9bce9d9 | j_mayer | if (env->asr != value) {
|
1956 | d9bce9d9 | j_mayer | env->asr = value; |
1957 | d9bce9d9 | j_mayer | tlb_flush(env, 1);
|
1958 | d9bce9d9 | j_mayer | } |
1959 | d9bce9d9 | j_mayer | } |
1960 | d9bce9d9 | j_mayer | #endif
|
1961 | d9bce9d9 | j_mayer | |
1962 | 45d827d2 | aurel32 | void ppc_store_sdr1 (CPUPPCState *env, target_ulong value)
|
1963 | 3fc6c082 | bellard | { |
1964 | d12d51d5 | aliguori | LOG_MMU("%s: " ADDRX "\n", __func__, value); |
1965 | 3fc6c082 | bellard | if (env->sdr1 != value) {
|
1966 | 12de9a39 | j_mayer | /* XXX: for PowerPC 64, should check that the HTABSIZE value
|
1967 | 12de9a39 | j_mayer | * is <= 28
|
1968 | 12de9a39 | j_mayer | */
|
1969 | 3fc6c082 | bellard | env->sdr1 = value; |
1970 | 76a66253 | j_mayer | tlb_flush(env, 1);
|
1971 | 3fc6c082 | bellard | } |
1972 | 3fc6c082 | bellard | } |
1973 | 3fc6c082 | bellard | |
1974 | 45d827d2 | aurel32 | void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value) |
1975 | 3fc6c082 | bellard | { |
1976 | d12d51d5 | aliguori | LOG_MMU("%s: reg=%d " ADDRX " " ADDRX "\n", |
1977 | 1b9eb036 | j_mayer | __func__, srnum, value, env->sr[srnum]); |
1978 | 3fc6c082 | bellard | if (env->sr[srnum] != value) {
|
1979 | 3fc6c082 | bellard | env->sr[srnum] = value; |
1980 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS) && 0 |
1981 | 3fc6c082 | bellard | { |
1982 | 3fc6c082 | bellard | target_ulong page, end; |
1983 | 3fc6c082 | bellard | /* Invalidate 256 MB of virtual memory */
|
1984 | 3fc6c082 | bellard | page = (16 << 20) * srnum; |
1985 | 3fc6c082 | bellard | end = page + (16 << 20); |
1986 | 3fc6c082 | bellard | for (; page != end; page += TARGET_PAGE_SIZE)
|
1987 | 3fc6c082 | bellard | tlb_flush_page(env, page); |
1988 | 3fc6c082 | bellard | } |
1989 | 3fc6c082 | bellard | #else
|
1990 | 76a66253 | j_mayer | tlb_flush(env, 1);
|
1991 | 3fc6c082 | bellard | #endif
|
1992 | 3fc6c082 | bellard | } |
1993 | 3fc6c082 | bellard | } |
1994 | 76a66253 | j_mayer | #endif /* !defined (CONFIG_USER_ONLY) */ |
1995 | 3fc6c082 | bellard | |
1996 | 76a66253 | j_mayer | /* GDBstub can read and write MSR... */
|
1997 | 0411a972 | j_mayer | void ppc_store_msr (CPUPPCState *env, target_ulong value)
|
1998 | 3fc6c082 | bellard | { |
1999 | a4f30719 | j_mayer | hreg_store_msr(env, value, 0);
|
2000 | 3fc6c082 | bellard | } |
2001 | 3fc6c082 | bellard | |
2002 | 3fc6c082 | bellard | /*****************************************************************************/
|
2003 | 3fc6c082 | bellard | /* Exception processing */
|
2004 | 18fba28c | bellard | #if defined (CONFIG_USER_ONLY)
|
2005 | 9a64fbe4 | bellard | void do_interrupt (CPUState *env)
|
2006 | 79aceca5 | bellard | { |
2007 | e1833e1f | j_mayer | env->exception_index = POWERPC_EXCP_NONE; |
2008 | e1833e1f | j_mayer | env->error_code = 0;
|
2009 | 18fba28c | bellard | } |
2010 | 47103572 | j_mayer | |
2011 | e9df014c | j_mayer | void ppc_hw_interrupt (CPUState *env)
|
2012 | 47103572 | j_mayer | { |
2013 | e1833e1f | j_mayer | env->exception_index = POWERPC_EXCP_NONE; |
2014 | e1833e1f | j_mayer | env->error_code = 0;
|
2015 | 47103572 | j_mayer | } |
2016 | 76a66253 | j_mayer | #else /* defined (CONFIG_USER_ONLY) */ |
2017 | a11b8151 | j_mayer | static always_inline void dump_syscall (CPUState *env) |
2018 | d094807b | bellard | { |
2019 | 6b542af7 | j_mayer | fprintf(logfile, "syscall r0=" REGX " r3=" REGX " r4=" REGX |
2020 | 6b542af7 | j_mayer | " r5=" REGX " r6=" REGX " nip=" ADDRX "\n", |
2021 | 6b542af7 | j_mayer | ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3), ppc_dump_gpr(env, 4), |
2022 | 6b542af7 | j_mayer | ppc_dump_gpr(env, 5), ppc_dump_gpr(env, 6), env->nip); |
2023 | d094807b | bellard | } |
2024 | d094807b | bellard | |
2025 | e1833e1f | j_mayer | /* Note that this function should be greatly optimized
|
2026 | e1833e1f | j_mayer | * when called with a constant excp, from ppc_hw_interrupt
|
2027 | e1833e1f | j_mayer | */
|
2028 | e1833e1f | j_mayer | static always_inline void powerpc_excp (CPUState *env, |
2029 | e1833e1f | j_mayer | int excp_model, int excp) |
2030 | 18fba28c | bellard | { |
2031 | 0411a972 | j_mayer | target_ulong msr, new_msr, vector; |
2032 | e1833e1f | j_mayer | int srr0, srr1, asrr0, asrr1;
|
2033 | a4f30719 | j_mayer | int lpes0, lpes1, lev;
|
2034 | 79aceca5 | bellard | |
2035 | b172c56a | j_mayer | if (0) { |
2036 | b172c56a | j_mayer | /* XXX: find a suitable condition to enable the hypervisor mode */
|
2037 | b172c56a | j_mayer | lpes0 = (env->spr[SPR_LPCR] >> 1) & 1; |
2038 | b172c56a | j_mayer | lpes1 = (env->spr[SPR_LPCR] >> 2) & 1; |
2039 | b172c56a | j_mayer | } else {
|
2040 | b172c56a | j_mayer | /* Those values ensure we won't enter the hypervisor mode */
|
2041 | b172c56a | j_mayer | lpes0 = 0;
|
2042 | b172c56a | j_mayer | lpes1 = 1;
|
2043 | b172c56a | j_mayer | } |
2044 | b172c56a | j_mayer | |
2045 | b769d8fe | bellard | if (loglevel & CPU_LOG_INT) {
|
2046 | 6b542af7 | j_mayer | fprintf(logfile, "Raise exception at " ADDRX " => %08x (%02x)\n", |
2047 | 1b9eb036 | j_mayer | env->nip, excp, env->error_code); |
2048 | b769d8fe | bellard | } |
2049 | 0411a972 | j_mayer | msr = env->msr; |
2050 | 0411a972 | j_mayer | new_msr = msr; |
2051 | e1833e1f | j_mayer | srr0 = SPR_SRR0; |
2052 | e1833e1f | j_mayer | srr1 = SPR_SRR1; |
2053 | e1833e1f | j_mayer | asrr0 = -1;
|
2054 | e1833e1f | j_mayer | asrr1 = -1;
|
2055 | e1833e1f | j_mayer | msr &= ~((target_ulong)0x783F0000);
|
2056 | 9a64fbe4 | bellard | switch (excp) {
|
2057 | e1833e1f | j_mayer | case POWERPC_EXCP_NONE:
|
2058 | e1833e1f | j_mayer | /* Should never happen */
|
2059 | e1833e1f | j_mayer | return;
|
2060 | e1833e1f | j_mayer | case POWERPC_EXCP_CRITICAL: /* Critical input */ |
2061 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2062 | e1833e1f | j_mayer | switch (excp_model) {
|
2063 | a750fc0b | j_mayer | case POWERPC_EXCP_40x:
|
2064 | e1833e1f | j_mayer | srr0 = SPR_40x_SRR2; |
2065 | e1833e1f | j_mayer | srr1 = SPR_40x_SRR3; |
2066 | c62db105 | j_mayer | break;
|
2067 | a750fc0b | j_mayer | case POWERPC_EXCP_BOOKE:
|
2068 | e1833e1f | j_mayer | srr0 = SPR_BOOKE_CSRR0; |
2069 | e1833e1f | j_mayer | srr1 = SPR_BOOKE_CSRR1; |
2070 | c62db105 | j_mayer | break;
|
2071 | e1833e1f | j_mayer | case POWERPC_EXCP_G2:
|
2072 | c62db105 | j_mayer | break;
|
2073 | e1833e1f | j_mayer | default:
|
2074 | e1833e1f | j_mayer | goto excp_invalid;
|
2075 | 2be0071f | bellard | } |
2076 | 9a64fbe4 | bellard | goto store_next;
|
2077 | e1833e1f | j_mayer | case POWERPC_EXCP_MCHECK: /* Machine check exception */ |
2078 | e1833e1f | j_mayer | if (msr_me == 0) { |
2079 | e63ecc6f | j_mayer | /* Machine check exception is not enabled.
|
2080 | e63ecc6f | j_mayer | * Enter checkstop state.
|
2081 | e63ecc6f | j_mayer | */
|
2082 | e63ecc6f | j_mayer | if (loglevel != 0) { |
2083 | e63ecc6f | j_mayer | fprintf(logfile, "Machine check while not allowed. "
|
2084 | e63ecc6f | j_mayer | "Entering checkstop state\n");
|
2085 | e63ecc6f | j_mayer | } else {
|
2086 | e63ecc6f | j_mayer | fprintf(stderr, "Machine check while not allowed. "
|
2087 | e63ecc6f | j_mayer | "Entering checkstop state\n");
|
2088 | e63ecc6f | j_mayer | } |
2089 | e63ecc6f | j_mayer | env->halted = 1;
|
2090 | e63ecc6f | j_mayer | env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
2091 | e1833e1f | j_mayer | } |
2092 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2093 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_ME);
|
2094 | b172c56a | j_mayer | if (0) { |
2095 | b172c56a | j_mayer | /* XXX: find a suitable condition to enable the hypervisor mode */
|
2096 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2097 | b172c56a | j_mayer | } |
2098 | e1833e1f | j_mayer | /* XXX: should also have something loaded in DAR / DSISR */
|
2099 | e1833e1f | j_mayer | switch (excp_model) {
|
2100 | a750fc0b | j_mayer | case POWERPC_EXCP_40x:
|
2101 | e1833e1f | j_mayer | srr0 = SPR_40x_SRR2; |
2102 | e1833e1f | j_mayer | srr1 = SPR_40x_SRR3; |
2103 | c62db105 | j_mayer | break;
|
2104 | a750fc0b | j_mayer | case POWERPC_EXCP_BOOKE:
|
2105 | e1833e1f | j_mayer | srr0 = SPR_BOOKE_MCSRR0; |
2106 | e1833e1f | j_mayer | srr1 = SPR_BOOKE_MCSRR1; |
2107 | e1833e1f | j_mayer | asrr0 = SPR_BOOKE_CSRR0; |
2108 | e1833e1f | j_mayer | asrr1 = SPR_BOOKE_CSRR1; |
2109 | c62db105 | j_mayer | break;
|
2110 | c62db105 | j_mayer | default:
|
2111 | c62db105 | j_mayer | break;
|
2112 | 2be0071f | bellard | } |
2113 | e1833e1f | j_mayer | goto store_next;
|
2114 | e1833e1f | j_mayer | case POWERPC_EXCP_DSI: /* Data storage exception */ |
2115 | d12d51d5 | aliguori | LOG_EXCP("DSI exception: DSISR=" ADDRX" DAR=" ADDRX "\n", |
2116 | 6b542af7 | j_mayer | env->spr[SPR_DSISR], env->spr[SPR_DAR]); |
2117 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2118 | e1833e1f | j_mayer | if (lpes1 == 0) |
2119 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2120 | a541f297 | bellard | goto store_next;
|
2121 | e1833e1f | j_mayer | case POWERPC_EXCP_ISI: /* Instruction storage exception */ |
2122 | d12d51d5 | aliguori | LOG_EXCP("ISI exception: msr=" ADDRX ", nip=" ADDRX "\n", |
2123 | 6b542af7 | j_mayer | msr, env->nip); |
2124 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2125 | e1833e1f | j_mayer | if (lpes1 == 0) |
2126 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2127 | e1833e1f | j_mayer | msr |= env->error_code; |
2128 | 9a64fbe4 | bellard | goto store_next;
|
2129 | e1833e1f | j_mayer | case POWERPC_EXCP_EXTERNAL: /* External input */ |
2130 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2131 | e1833e1f | j_mayer | if (lpes0 == 1) |
2132 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2133 | 9a64fbe4 | bellard | goto store_next;
|
2134 | e1833e1f | j_mayer | case POWERPC_EXCP_ALIGN: /* Alignment exception */ |
2135 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2136 | e1833e1f | j_mayer | if (lpes1 == 0) |
2137 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2138 | e1833e1f | j_mayer | /* XXX: this is false */
|
2139 | e1833e1f | j_mayer | /* Get rS/rD and rA from faulting opcode */
|
2140 | e1833e1f | j_mayer | env->spr[SPR_DSISR] |= (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16; |
2141 | 9a64fbe4 | bellard | goto store_current;
|
2142 | e1833e1f | j_mayer | case POWERPC_EXCP_PROGRAM: /* Program exception */ |
2143 | 9a64fbe4 | bellard | switch (env->error_code & ~0xF) { |
2144 | e1833e1f | j_mayer | case POWERPC_EXCP_FP:
|
2145 | e1833e1f | j_mayer | if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) { |
2146 | d12d51d5 | aliguori | LOG_EXCP("Ignore floating point exception\n");
|
2147 | 7c58044c | j_mayer | env->exception_index = POWERPC_EXCP_NONE; |
2148 | 7c58044c | j_mayer | env->error_code = 0;
|
2149 | 9a64fbe4 | bellard | return;
|
2150 | 76a66253 | j_mayer | } |
2151 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2152 | e1833e1f | j_mayer | if (lpes1 == 0) |
2153 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2154 | 9a64fbe4 | bellard | msr |= 0x00100000;
|
2155 | 5b52b991 | j_mayer | if (msr_fe0 == msr_fe1)
|
2156 | 5b52b991 | j_mayer | goto store_next;
|
2157 | 5b52b991 | j_mayer | msr |= 0x00010000;
|
2158 | 76a66253 | j_mayer | break;
|
2159 | e1833e1f | j_mayer | case POWERPC_EXCP_INVAL:
|
2160 | d12d51d5 | aliguori | LOG_EXCP("Invalid instruction at " ADDRX "\n", |
2161 | a496775f | j_mayer | env->nip); |
2162 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2163 | e1833e1f | j_mayer | if (lpes1 == 0) |
2164 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2165 | 9a64fbe4 | bellard | msr |= 0x00080000;
|
2166 | 76a66253 | j_mayer | break;
|
2167 | e1833e1f | j_mayer | case POWERPC_EXCP_PRIV:
|
2168 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2169 | e1833e1f | j_mayer | if (lpes1 == 0) |
2170 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2171 | 9a64fbe4 | bellard | msr |= 0x00040000;
|
2172 | 76a66253 | j_mayer | break;
|
2173 | e1833e1f | j_mayer | case POWERPC_EXCP_TRAP:
|
2174 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2175 | e1833e1f | j_mayer | if (lpes1 == 0) |
2176 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2177 | 9a64fbe4 | bellard | msr |= 0x00020000;
|
2178 | 9a64fbe4 | bellard | break;
|
2179 | 9a64fbe4 | bellard | default:
|
2180 | 9a64fbe4 | bellard | /* Should never occur */
|
2181 | e1833e1f | j_mayer | cpu_abort(env, "Invalid program exception %d. Aborting\n",
|
2182 | e1833e1f | j_mayer | env->error_code); |
2183 | 76a66253 | j_mayer | break;
|
2184 | 76a66253 | j_mayer | } |
2185 | 5b52b991 | j_mayer | goto store_current;
|
2186 | e1833e1f | j_mayer | case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ |
2187 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2188 | e1833e1f | j_mayer | if (lpes1 == 0) |
2189 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2190 | e1833e1f | j_mayer | goto store_current;
|
2191 | e1833e1f | j_mayer | case POWERPC_EXCP_SYSCALL: /* System call exception */ |
2192 | d094807b | bellard | /* NOTE: this is a temporary hack to support graphics OSI
|
2193 | d094807b | bellard | calls from the MOL driver */
|
2194 | e1833e1f | j_mayer | /* XXX: To be removed */
|
2195 | d094807b | bellard | if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b && |
2196 | d094807b | bellard | env->osi_call) { |
2197 | 7c58044c | j_mayer | if (env->osi_call(env) != 0) { |
2198 | 7c58044c | j_mayer | env->exception_index = POWERPC_EXCP_NONE; |
2199 | 7c58044c | j_mayer | env->error_code = 0;
|
2200 | d094807b | bellard | return;
|
2201 | 7c58044c | j_mayer | } |
2202 | d094807b | bellard | } |
2203 | b769d8fe | bellard | if (loglevel & CPU_LOG_INT) {
|
2204 | d094807b | bellard | dump_syscall(env); |
2205 | b769d8fe | bellard | } |
2206 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2207 | f9fdea6b | j_mayer | lev = env->error_code; |
2208 | e1833e1f | j_mayer | if (lev == 1 || (lpes0 == 0 && lpes1 == 0)) |
2209 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2210 | e1833e1f | j_mayer | goto store_next;
|
2211 | e1833e1f | j_mayer | case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ |
2212 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2213 | e1833e1f | j_mayer | goto store_current;
|
2214 | e1833e1f | j_mayer | case POWERPC_EXCP_DECR: /* Decrementer exception */ |
2215 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2216 | e1833e1f | j_mayer | if (lpes1 == 0) |
2217 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2218 | e1833e1f | j_mayer | goto store_next;
|
2219 | e1833e1f | j_mayer | case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ |
2220 | e1833e1f | j_mayer | /* FIT on 4xx */
|
2221 | d12d51d5 | aliguori | LOG_EXCP("FIT exception\n");
|
2222 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2223 | 9a64fbe4 | bellard | goto store_next;
|
2224 | e1833e1f | j_mayer | case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ |
2225 | d12d51d5 | aliguori | LOG_EXCP("WDT exception\n");
|
2226 | e1833e1f | j_mayer | switch (excp_model) {
|
2227 | e1833e1f | j_mayer | case POWERPC_EXCP_BOOKE:
|
2228 | e1833e1f | j_mayer | srr0 = SPR_BOOKE_CSRR0; |
2229 | e1833e1f | j_mayer | srr1 = SPR_BOOKE_CSRR1; |
2230 | e1833e1f | j_mayer | break;
|
2231 | e1833e1f | j_mayer | default:
|
2232 | e1833e1f | j_mayer | break;
|
2233 | e1833e1f | j_mayer | } |
2234 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2235 | 2be0071f | bellard | goto store_next;
|
2236 | e1833e1f | j_mayer | case POWERPC_EXCP_DTLB: /* Data TLB error */ |
2237 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2238 | e1833e1f | j_mayer | goto store_next;
|
2239 | e1833e1f | j_mayer | case POWERPC_EXCP_ITLB: /* Instruction TLB error */ |
2240 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2241 | e1833e1f | j_mayer | goto store_next;
|
2242 | e1833e1f | j_mayer | case POWERPC_EXCP_DEBUG: /* Debug interrupt */ |
2243 | e1833e1f | j_mayer | switch (excp_model) {
|
2244 | e1833e1f | j_mayer | case POWERPC_EXCP_BOOKE:
|
2245 | e1833e1f | j_mayer | srr0 = SPR_BOOKE_DSRR0; |
2246 | e1833e1f | j_mayer | srr1 = SPR_BOOKE_DSRR1; |
2247 | e1833e1f | j_mayer | asrr0 = SPR_BOOKE_CSRR0; |
2248 | e1833e1f | j_mayer | asrr1 = SPR_BOOKE_CSRR1; |
2249 | e1833e1f | j_mayer | break;
|
2250 | e1833e1f | j_mayer | default:
|
2251 | e1833e1f | j_mayer | break;
|
2252 | e1833e1f | j_mayer | } |
2253 | 2be0071f | bellard | /* XXX: TODO */
|
2254 | e1833e1f | j_mayer | cpu_abort(env, "Debug exception is not implemented yet !\n");
|
2255 | 2be0071f | bellard | goto store_next;
|
2256 | e1833e1f | j_mayer | case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */ |
2257 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2258 | e1833e1f | j_mayer | goto store_current;
|
2259 | e1833e1f | j_mayer | case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */ |
2260 | 2be0071f | bellard | /* XXX: TODO */
|
2261 | e1833e1f | j_mayer | cpu_abort(env, "Embedded floating point data exception "
|
2262 | 2be0071f | bellard | "is not implemented yet !\n");
|
2263 | 2be0071f | bellard | goto store_next;
|
2264 | e1833e1f | j_mayer | case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */ |
2265 | 2be0071f | bellard | /* XXX: TODO */
|
2266 | e1833e1f | j_mayer | cpu_abort(env, "Embedded floating point round exception "
|
2267 | e1833e1f | j_mayer | "is not implemented yet !\n");
|
2268 | 9a64fbe4 | bellard | goto store_next;
|
2269 | e1833e1f | j_mayer | case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */ |
2270 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2271 | 2be0071f | bellard | /* XXX: TODO */
|
2272 | 2be0071f | bellard | cpu_abort(env, |
2273 | e1833e1f | j_mayer | "Performance counter exception is not implemented yet !\n");
|
2274 | 9a64fbe4 | bellard | goto store_next;
|
2275 | e1833e1f | j_mayer | case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ |
2276 | 76a66253 | j_mayer | /* XXX: TODO */
|
2277 | e1833e1f | j_mayer | cpu_abort(env, |
2278 | e1833e1f | j_mayer | "Embedded doorbell interrupt is not implemented yet !\n");
|
2279 | 2be0071f | bellard | goto store_next;
|
2280 | e1833e1f | j_mayer | case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */ |
2281 | e1833e1f | j_mayer | switch (excp_model) {
|
2282 | e1833e1f | j_mayer | case POWERPC_EXCP_BOOKE:
|
2283 | e1833e1f | j_mayer | srr0 = SPR_BOOKE_CSRR0; |
2284 | e1833e1f | j_mayer | srr1 = SPR_BOOKE_CSRR1; |
2285 | a750fc0b | j_mayer | break;
|
2286 | 2be0071f | bellard | default:
|
2287 | 2be0071f | bellard | break;
|
2288 | 2be0071f | bellard | } |
2289 | e1833e1f | j_mayer | /* XXX: TODO */
|
2290 | e1833e1f | j_mayer | cpu_abort(env, "Embedded doorbell critical interrupt "
|
2291 | e1833e1f | j_mayer | "is not implemented yet !\n");
|
2292 | e1833e1f | j_mayer | goto store_next;
|
2293 | e1833e1f | j_mayer | case POWERPC_EXCP_RESET: /* System reset exception */ |
2294 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2295 | a4f30719 | j_mayer | if (0) { |
2296 | a4f30719 | j_mayer | /* XXX: find a suitable condition to enable the hypervisor mode */
|
2297 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2298 | a4f30719 | j_mayer | } |
2299 | e1833e1f | j_mayer | goto store_next;
|
2300 | e1833e1f | j_mayer | case POWERPC_EXCP_DSEG: /* Data segment exception */ |
2301 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2302 | e1833e1f | j_mayer | if (lpes1 == 0) |
2303 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2304 | e1833e1f | j_mayer | goto store_next;
|
2305 | e1833e1f | j_mayer | case POWERPC_EXCP_ISEG: /* Instruction segment exception */ |
2306 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2307 | e1833e1f | j_mayer | if (lpes1 == 0) |
2308 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2309 | e1833e1f | j_mayer | goto store_next;
|
2310 | e1833e1f | j_mayer | case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ |
2311 | e1833e1f | j_mayer | srr0 = SPR_HSRR0; |
2312 | f9fdea6b | j_mayer | srr1 = SPR_HSRR1; |
2313 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2314 | b172c56a | j_mayer | goto store_next;
|
2315 | e1833e1f | j_mayer | case POWERPC_EXCP_TRACE: /* Trace exception */ |
2316 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2317 | e1833e1f | j_mayer | if (lpes1 == 0) |
2318 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2319 | e1833e1f | j_mayer | goto store_next;
|
2320 | e1833e1f | j_mayer | case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ |
2321 | e1833e1f | j_mayer | srr0 = SPR_HSRR0; |
2322 | f9fdea6b | j_mayer | srr1 = SPR_HSRR1; |
2323 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2324 | e1833e1f | j_mayer | goto store_next;
|
2325 | e1833e1f | j_mayer | case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */ |
2326 | e1833e1f | j_mayer | srr0 = SPR_HSRR0; |
2327 | f9fdea6b | j_mayer | srr1 = SPR_HSRR1; |
2328 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2329 | e1833e1f | j_mayer | goto store_next;
|
2330 | e1833e1f | j_mayer | case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */ |
2331 | e1833e1f | j_mayer | srr0 = SPR_HSRR0; |
2332 | f9fdea6b | j_mayer | srr1 = SPR_HSRR1; |
2333 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2334 | e1833e1f | j_mayer | goto store_next;
|
2335 | e1833e1f | j_mayer | case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */ |
2336 | e1833e1f | j_mayer | srr0 = SPR_HSRR0; |
2337 | f9fdea6b | j_mayer | srr1 = SPR_HSRR1; |
2338 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2339 | e1833e1f | j_mayer | goto store_next;
|
2340 | e1833e1f | j_mayer | case POWERPC_EXCP_VPU: /* Vector unavailable exception */ |
2341 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2342 | e1833e1f | j_mayer | if (lpes1 == 0) |
2343 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2344 | e1833e1f | j_mayer | goto store_current;
|
2345 | e1833e1f | j_mayer | case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */ |
2346 | d12d51d5 | aliguori | LOG_EXCP("PIT exception\n");
|
2347 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2348 | e1833e1f | j_mayer | goto store_next;
|
2349 | e1833e1f | j_mayer | case POWERPC_EXCP_IO: /* IO error exception */ |
2350 | e1833e1f | j_mayer | /* XXX: TODO */
|
2351 | e1833e1f | j_mayer | cpu_abort(env, "601 IO error exception is not implemented yet !\n");
|
2352 | e1833e1f | j_mayer | goto store_next;
|
2353 | e1833e1f | j_mayer | case POWERPC_EXCP_RUNM: /* Run mode exception */ |
2354 | e1833e1f | j_mayer | /* XXX: TODO */
|
2355 | e1833e1f | j_mayer | cpu_abort(env, "601 run mode exception is not implemented yet !\n");
|
2356 | e1833e1f | j_mayer | goto store_next;
|
2357 | e1833e1f | j_mayer | case POWERPC_EXCP_EMUL: /* Emulation trap exception */ |
2358 | e1833e1f | j_mayer | /* XXX: TODO */
|
2359 | e1833e1f | j_mayer | cpu_abort(env, "602 emulation trap exception "
|
2360 | e1833e1f | j_mayer | "is not implemented yet !\n");
|
2361 | e1833e1f | j_mayer | goto store_next;
|
2362 | e1833e1f | j_mayer | case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ |
2363 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2364 | a4f30719 | j_mayer | if (lpes1 == 0) /* XXX: check this */ |
2365 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2366 | e1833e1f | j_mayer | switch (excp_model) {
|
2367 | a750fc0b | j_mayer | case POWERPC_EXCP_602:
|
2368 | a750fc0b | j_mayer | case POWERPC_EXCP_603:
|
2369 | a750fc0b | j_mayer | case POWERPC_EXCP_603E:
|
2370 | a750fc0b | j_mayer | case POWERPC_EXCP_G2:
|
2371 | e1833e1f | j_mayer | goto tlb_miss_tgpr;
|
2372 | a750fc0b | j_mayer | case POWERPC_EXCP_7x5:
|
2373 | 76a66253 | j_mayer | goto tlb_miss;
|
2374 | 7dbe11ac | j_mayer | case POWERPC_EXCP_74xx:
|
2375 | 7dbe11ac | j_mayer | goto tlb_miss_74xx;
|
2376 | 2be0071f | bellard | default:
|
2377 | e1833e1f | j_mayer | cpu_abort(env, "Invalid instruction TLB miss exception\n");
|
2378 | 2be0071f | bellard | break;
|
2379 | 2be0071f | bellard | } |
2380 | e1833e1f | j_mayer | break;
|
2381 | e1833e1f | j_mayer | case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ |
2382 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2383 | a4f30719 | j_mayer | if (lpes1 == 0) /* XXX: check this */ |
2384 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2385 | e1833e1f | j_mayer | switch (excp_model) {
|
2386 | a750fc0b | j_mayer | case POWERPC_EXCP_602:
|
2387 | a750fc0b | j_mayer | case POWERPC_EXCP_603:
|
2388 | a750fc0b | j_mayer | case POWERPC_EXCP_603E:
|
2389 | a750fc0b | j_mayer | case POWERPC_EXCP_G2:
|
2390 | e1833e1f | j_mayer | goto tlb_miss_tgpr;
|
2391 | a750fc0b | j_mayer | case POWERPC_EXCP_7x5:
|
2392 | 76a66253 | j_mayer | goto tlb_miss;
|
2393 | 7dbe11ac | j_mayer | case POWERPC_EXCP_74xx:
|
2394 | 7dbe11ac | j_mayer | goto tlb_miss_74xx;
|
2395 | 2be0071f | bellard | default:
|
2396 | e1833e1f | j_mayer | cpu_abort(env, "Invalid data load TLB miss exception\n");
|
2397 | 2be0071f | bellard | break;
|
2398 | 2be0071f | bellard | } |
2399 | e1833e1f | j_mayer | break;
|
2400 | e1833e1f | j_mayer | case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ |
2401 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2402 | a4f30719 | j_mayer | if (lpes1 == 0) /* XXX: check this */ |
2403 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2404 | e1833e1f | j_mayer | switch (excp_model) {
|
2405 | a750fc0b | j_mayer | case POWERPC_EXCP_602:
|
2406 | a750fc0b | j_mayer | case POWERPC_EXCP_603:
|
2407 | a750fc0b | j_mayer | case POWERPC_EXCP_603E:
|
2408 | a750fc0b | j_mayer | case POWERPC_EXCP_G2:
|
2409 | e1833e1f | j_mayer | tlb_miss_tgpr:
|
2410 | 76a66253 | j_mayer | /* Swap temporary saved registers with GPRs */
|
2411 | 0411a972 | j_mayer | if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) { |
2412 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_TGPR;
|
2413 | 0411a972 | j_mayer | hreg_swap_gpr_tgpr(env); |
2414 | 0411a972 | j_mayer | } |
2415 | e1833e1f | j_mayer | goto tlb_miss;
|
2416 | e1833e1f | j_mayer | case POWERPC_EXCP_7x5:
|
2417 | e1833e1f | j_mayer | tlb_miss:
|
2418 | 2be0071f | bellard | #if defined (DEBUG_SOFTWARE_TLB)
|
2419 | 2be0071f | bellard | if (loglevel != 0) { |
2420 | 76a66253 | j_mayer | const unsigned char *es; |
2421 | 76a66253 | j_mayer | target_ulong *miss, *cmp; |
2422 | 76a66253 | j_mayer | int en;
|
2423 | 1e6784f9 | j_mayer | if (excp == POWERPC_EXCP_IFTLB) {
|
2424 | 76a66253 | j_mayer | es = "I";
|
2425 | 76a66253 | j_mayer | en = 'I';
|
2426 | 76a66253 | j_mayer | miss = &env->spr[SPR_IMISS]; |
2427 | 76a66253 | j_mayer | cmp = &env->spr[SPR_ICMP]; |
2428 | 76a66253 | j_mayer | } else {
|
2429 | 1e6784f9 | j_mayer | if (excp == POWERPC_EXCP_DLTLB)
|
2430 | 76a66253 | j_mayer | es = "DL";
|
2431 | 76a66253 | j_mayer | else
|
2432 | 76a66253 | j_mayer | es = "DS";
|
2433 | 76a66253 | j_mayer | en = 'D';
|
2434 | 76a66253 | j_mayer | miss = &env->spr[SPR_DMISS]; |
2435 | 76a66253 | j_mayer | cmp = &env->spr[SPR_DCMP]; |
2436 | 76a66253 | j_mayer | } |
2437 | 1b9eb036 | j_mayer | fprintf(logfile, "6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX |
2438 | 4a057712 | j_mayer | " H1 " ADDRX " H2 " ADDRX " %08x\n", |
2439 | 1b9eb036 | j_mayer | es, en, *miss, en, *cmp, |
2440 | 76a66253 | j_mayer | env->spr[SPR_HASH1], env->spr[SPR_HASH2], |
2441 | 2be0071f | bellard | env->error_code); |
2442 | 2be0071f | bellard | } |
2443 | 9a64fbe4 | bellard | #endif
|
2444 | 2be0071f | bellard | msr |= env->crf[0] << 28; |
2445 | 2be0071f | bellard | msr |= env->error_code; /* key, D/I, S/L bits */
|
2446 | 2be0071f | bellard | /* Set way using a LRU mechanism */
|
2447 | 76a66253 | j_mayer | msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17; |
2448 | c62db105 | j_mayer | break;
|
2449 | 7dbe11ac | j_mayer | case POWERPC_EXCP_74xx:
|
2450 | 7dbe11ac | j_mayer | tlb_miss_74xx:
|
2451 | 7dbe11ac | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
|
2452 | 7dbe11ac | j_mayer | if (loglevel != 0) { |
2453 | 7dbe11ac | j_mayer | const unsigned char *es; |
2454 | 7dbe11ac | j_mayer | target_ulong *miss, *cmp; |
2455 | 7dbe11ac | j_mayer | int en;
|
2456 | 7dbe11ac | j_mayer | if (excp == POWERPC_EXCP_IFTLB) {
|
2457 | 7dbe11ac | j_mayer | es = "I";
|
2458 | 7dbe11ac | j_mayer | en = 'I';
|
2459 | 0411a972 | j_mayer | miss = &env->spr[SPR_TLBMISS]; |
2460 | 0411a972 | j_mayer | cmp = &env->spr[SPR_PTEHI]; |
2461 | 7dbe11ac | j_mayer | } else {
|
2462 | 7dbe11ac | j_mayer | if (excp == POWERPC_EXCP_DLTLB)
|
2463 | 7dbe11ac | j_mayer | es = "DL";
|
2464 | 7dbe11ac | j_mayer | else
|
2465 | 7dbe11ac | j_mayer | es = "DS";
|
2466 | 7dbe11ac | j_mayer | en = 'D';
|
2467 | 7dbe11ac | j_mayer | miss = &env->spr[SPR_TLBMISS]; |
2468 | 7dbe11ac | j_mayer | cmp = &env->spr[SPR_PTEHI]; |
2469 | 7dbe11ac | j_mayer | } |
2470 | 7dbe11ac | j_mayer | fprintf(logfile, "74xx %sTLB miss: %cM " ADDRX " %cC " ADDRX |
2471 | 7dbe11ac | j_mayer | " %08x\n",
|
2472 | 7dbe11ac | j_mayer | es, en, *miss, en, *cmp, env->error_code); |
2473 | 7dbe11ac | j_mayer | } |
2474 | 7dbe11ac | j_mayer | #endif
|
2475 | 7dbe11ac | j_mayer | msr |= env->error_code; /* key bit */
|
2476 | 7dbe11ac | j_mayer | break;
|
2477 | 2be0071f | bellard | default:
|
2478 | e1833e1f | j_mayer | cpu_abort(env, "Invalid data store TLB miss exception\n");
|
2479 | 2be0071f | bellard | break;
|
2480 | 2be0071f | bellard | } |
2481 | e1833e1f | j_mayer | goto store_next;
|
2482 | e1833e1f | j_mayer | case POWERPC_EXCP_FPA: /* Floating-point assist exception */ |
2483 | e1833e1f | j_mayer | /* XXX: TODO */
|
2484 | e1833e1f | j_mayer | cpu_abort(env, "Floating point assist exception "
|
2485 | e1833e1f | j_mayer | "is not implemented yet !\n");
|
2486 | e1833e1f | j_mayer | goto store_next;
|
2487 | b4095fed | j_mayer | case POWERPC_EXCP_DABR: /* Data address breakpoint */ |
2488 | b4095fed | j_mayer | /* XXX: TODO */
|
2489 | b4095fed | j_mayer | cpu_abort(env, "DABR exception is not implemented yet !\n");
|
2490 | b4095fed | j_mayer | goto store_next;
|
2491 | e1833e1f | j_mayer | case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ |
2492 | e1833e1f | j_mayer | /* XXX: TODO */
|
2493 | e1833e1f | j_mayer | cpu_abort(env, "IABR exception is not implemented yet !\n");
|
2494 | e1833e1f | j_mayer | goto store_next;
|
2495 | e1833e1f | j_mayer | case POWERPC_EXCP_SMI: /* System management interrupt */ |
2496 | e1833e1f | j_mayer | /* XXX: TODO */
|
2497 | e1833e1f | j_mayer | cpu_abort(env, "SMI exception is not implemented yet !\n");
|
2498 | e1833e1f | j_mayer | goto store_next;
|
2499 | e1833e1f | j_mayer | case POWERPC_EXCP_THERM: /* Thermal interrupt */ |
2500 | e1833e1f | j_mayer | /* XXX: TODO */
|
2501 | e1833e1f | j_mayer | cpu_abort(env, "Thermal management exception "
|
2502 | e1833e1f | j_mayer | "is not implemented yet !\n");
|
2503 | e1833e1f | j_mayer | goto store_next;
|
2504 | e1833e1f | j_mayer | case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */ |
2505 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2506 | e1833e1f | j_mayer | if (lpes1 == 0) |
2507 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2508 | e1833e1f | j_mayer | /* XXX: TODO */
|
2509 | e1833e1f | j_mayer | cpu_abort(env, |
2510 | e1833e1f | j_mayer | "Performance counter exception is not implemented yet !\n");
|
2511 | e1833e1f | j_mayer | goto store_next;
|
2512 | e1833e1f | j_mayer | case POWERPC_EXCP_VPUA: /* Vector assist exception */ |
2513 | e1833e1f | j_mayer | /* XXX: TODO */
|
2514 | e1833e1f | j_mayer | cpu_abort(env, "VPU assist exception is not implemented yet !\n");
|
2515 | e1833e1f | j_mayer | goto store_next;
|
2516 | e1833e1f | j_mayer | case POWERPC_EXCP_SOFTP: /* Soft patch exception */ |
2517 | e1833e1f | j_mayer | /* XXX: TODO */
|
2518 | e1833e1f | j_mayer | cpu_abort(env, |
2519 | e1833e1f | j_mayer | "970 soft-patch exception is not implemented yet !\n");
|
2520 | e1833e1f | j_mayer | goto store_next;
|
2521 | e1833e1f | j_mayer | case POWERPC_EXCP_MAINT: /* Maintenance exception */ |
2522 | e1833e1f | j_mayer | /* XXX: TODO */
|
2523 | e1833e1f | j_mayer | cpu_abort(env, |
2524 | e1833e1f | j_mayer | "970 maintenance exception is not implemented yet !\n");
|
2525 | e1833e1f | j_mayer | goto store_next;
|
2526 | b4095fed | j_mayer | case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */ |
2527 | b4095fed | j_mayer | /* XXX: TODO */
|
2528 | b4095fed | j_mayer | cpu_abort(env, "Maskable external exception "
|
2529 | b4095fed | j_mayer | "is not implemented yet !\n");
|
2530 | b4095fed | j_mayer | goto store_next;
|
2531 | b4095fed | j_mayer | case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */ |
2532 | b4095fed | j_mayer | /* XXX: TODO */
|
2533 | b4095fed | j_mayer | cpu_abort(env, "Non maskable external exception "
|
2534 | b4095fed | j_mayer | "is not implemented yet !\n");
|
2535 | b4095fed | j_mayer | goto store_next;
|
2536 | 2be0071f | bellard | default:
|
2537 | e1833e1f | j_mayer | excp_invalid:
|
2538 | e1833e1f | j_mayer | cpu_abort(env, "Invalid PowerPC exception %d. Aborting\n", excp);
|
2539 | e1833e1f | j_mayer | break;
|
2540 | 9a64fbe4 | bellard | store_current:
|
2541 | 2be0071f | bellard | /* save current instruction location */
|
2542 | e1833e1f | j_mayer | env->spr[srr0] = env->nip - 4;
|
2543 | 9a64fbe4 | bellard | break;
|
2544 | 9a64fbe4 | bellard | store_next:
|
2545 | 2be0071f | bellard | /* save next instruction location */
|
2546 | e1833e1f | j_mayer | env->spr[srr0] = env->nip; |
2547 | 9a64fbe4 | bellard | break;
|
2548 | 9a64fbe4 | bellard | } |
2549 | e1833e1f | j_mayer | /* Save MSR */
|
2550 | e1833e1f | j_mayer | env->spr[srr1] = msr; |
2551 | e1833e1f | j_mayer | /* If any alternate SRR register are defined, duplicate saved values */
|
2552 | e1833e1f | j_mayer | if (asrr0 != -1) |
2553 | e1833e1f | j_mayer | env->spr[asrr0] = env->spr[srr0]; |
2554 | e1833e1f | j_mayer | if (asrr1 != -1) |
2555 | e1833e1f | j_mayer | env->spr[asrr1] = env->spr[srr1]; |
2556 | 2be0071f | bellard | /* If we disactivated any translation, flush TLBs */
|
2557 | 0411a972 | j_mayer | if (new_msr & ((1 << MSR_IR) | (1 << MSR_DR))) |
2558 | 2be0071f | bellard | tlb_flush(env, 1);
|
2559 | 9a64fbe4 | bellard | /* reload MSR with correct bits */
|
2560 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_EE);
|
2561 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_PR);
|
2562 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_FP);
|
2563 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_FE0);
|
2564 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_SE);
|
2565 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_BE);
|
2566 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_FE1);
|
2567 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_IR);
|
2568 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_DR);
|
2569 | e1833e1f | j_mayer | #if 0 /* Fix this: not on all targets */
|
2570 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_PMM);
|
2571 | e1833e1f | j_mayer | #endif
|
2572 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_LE);
|
2573 | 0411a972 | j_mayer | if (msr_ile)
|
2574 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_LE;
|
2575 | 0411a972 | j_mayer | else
|
2576 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_LE);
|
2577 | e1833e1f | j_mayer | /* Jump to handler */
|
2578 | e1833e1f | j_mayer | vector = env->excp_vectors[excp]; |
2579 | 6f2d8978 | j_mayer | if (vector == (target_ulong)-1ULL) { |
2580 | e1833e1f | j_mayer | cpu_abort(env, "Raised an exception without defined vector %d\n",
|
2581 | e1833e1f | j_mayer | excp); |
2582 | e1833e1f | j_mayer | } |
2583 | e1833e1f | j_mayer | vector |= env->excp_prefix; |
2584 | c62db105 | j_mayer | #if defined(TARGET_PPC64)
|
2585 | e1833e1f | j_mayer | if (excp_model == POWERPC_EXCP_BOOKE) {
|
2586 | 0411a972 | j_mayer | if (!msr_icm) {
|
2587 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_CM);
|
2588 | e1833e1f | j_mayer | vector = (uint32_t)vector; |
2589 | 0411a972 | j_mayer | } else {
|
2590 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_CM;
|
2591 | 0411a972 | j_mayer | } |
2592 | c62db105 | j_mayer | } else {
|
2593 | 0411a972 | j_mayer | if (!msr_isf) {
|
2594 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_SF);
|
2595 | e1833e1f | j_mayer | vector = (uint32_t)vector; |
2596 | 0411a972 | j_mayer | } else {
|
2597 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_SF;
|
2598 | 0411a972 | j_mayer | } |
2599 | c62db105 | j_mayer | } |
2600 | e1833e1f | j_mayer | #endif
|
2601 | 0411a972 | j_mayer | /* XXX: we don't use hreg_store_msr here as already have treated
|
2602 | 0411a972 | j_mayer | * any special case that could occur. Just store MSR and update hflags
|
2603 | 0411a972 | j_mayer | */
|
2604 | a4f30719 | j_mayer | env->msr = new_msr & env->msr_mask; |
2605 | 0411a972 | j_mayer | hreg_compute_hflags(env); |
2606 | e1833e1f | j_mayer | env->nip = vector; |
2607 | e1833e1f | j_mayer | /* Reset exception state */
|
2608 | e1833e1f | j_mayer | env->exception_index = POWERPC_EXCP_NONE; |
2609 | e1833e1f | j_mayer | env->error_code = 0;
|
2610 | fb0eaffc | bellard | } |
2611 | 47103572 | j_mayer | |
2612 | e1833e1f | j_mayer | void do_interrupt (CPUState *env)
|
2613 | 47103572 | j_mayer | { |
2614 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, env->exception_index); |
2615 | e1833e1f | j_mayer | } |
2616 | 47103572 | j_mayer | |
2617 | e1833e1f | j_mayer | void ppc_hw_interrupt (CPUPPCState *env)
|
2618 | e1833e1f | j_mayer | { |
2619 | f9fdea6b | j_mayer | int hdice;
|
2620 | f9fdea6b | j_mayer | |
2621 | 0411a972 | j_mayer | #if 0
|
2622 | a496775f | j_mayer | if (loglevel & CPU_LOG_INT) {
|
2623 | a496775f | j_mayer | fprintf(logfile, "%s: %p pending %08x req %08x me %d ee %d\n",
|
2624 | a496775f | j_mayer | __func__, env, env->pending_interrupts,
|
2625 | 0411a972 | j_mayer | env->interrupt_request, (int)msr_me, (int)msr_ee);
|
2626 | a496775f | j_mayer | }
|
2627 | 47103572 | j_mayer | #endif
|
2628 | e1833e1f | j_mayer | /* External reset */
|
2629 | 47103572 | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) { |
2630 | 47103572 | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
|
2631 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_RESET); |
2632 | e1833e1f | j_mayer | return;
|
2633 | e1833e1f | j_mayer | } |
2634 | e1833e1f | j_mayer | /* Machine check exception */
|
2635 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) { |
2636 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
|
2637 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_MCHECK); |
2638 | e1833e1f | j_mayer | return;
|
2639 | 47103572 | j_mayer | } |
2640 | e1833e1f | j_mayer | #if 0 /* TODO */
|
2641 | e1833e1f | j_mayer | /* External debug exception */
|
2642 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
|
2643 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
|
2644 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DEBUG);
|
2645 | e1833e1f | j_mayer | return;
|
2646 | e1833e1f | j_mayer | }
|
2647 | e1833e1f | j_mayer | #endif
|
2648 | b172c56a | j_mayer | if (0) { |
2649 | b172c56a | j_mayer | /* XXX: find a suitable condition to enable the hypervisor mode */
|
2650 | b172c56a | j_mayer | hdice = env->spr[SPR_LPCR] & 1;
|
2651 | b172c56a | j_mayer | } else {
|
2652 | b172c56a | j_mayer | hdice = 0;
|
2653 | b172c56a | j_mayer | } |
2654 | f9fdea6b | j_mayer | if ((msr_ee != 0 || msr_hv == 0 || msr_pr != 0) && hdice != 0) { |
2655 | 47103572 | j_mayer | /* Hypervisor decrementer exception */
|
2656 | 47103572 | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) { |
2657 | 47103572 | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
|
2658 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_HDECR); |
2659 | e1833e1f | j_mayer | return;
|
2660 | e1833e1f | j_mayer | } |
2661 | e1833e1f | j_mayer | } |
2662 | e1833e1f | j_mayer | if (msr_ce != 0) { |
2663 | e1833e1f | j_mayer | /* External critical interrupt */
|
2664 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) { |
2665 | e1833e1f | j_mayer | /* Taking a critical external interrupt does not clear the external
|
2666 | e1833e1f | j_mayer | * critical interrupt status
|
2667 | e1833e1f | j_mayer | */
|
2668 | e1833e1f | j_mayer | #if 0
|
2669 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CEXT);
|
2670 | 47103572 | j_mayer | #endif
|
2671 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_CRITICAL); |
2672 | e1833e1f | j_mayer | return;
|
2673 | e1833e1f | j_mayer | } |
2674 | e1833e1f | j_mayer | } |
2675 | e1833e1f | j_mayer | if (msr_ee != 0) { |
2676 | e1833e1f | j_mayer | /* Watchdog timer on embedded PowerPC */
|
2677 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) { |
2678 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
|
2679 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_WDT); |
2680 | e1833e1f | j_mayer | return;
|
2681 | e1833e1f | j_mayer | } |
2682 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) { |
2683 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL);
|
2684 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORCI); |
2685 | e1833e1f | j_mayer | return;
|
2686 | e1833e1f | j_mayer | } |
2687 | e1833e1f | j_mayer | /* Fixed interval timer on embedded PowerPC */
|
2688 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) { |
2689 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
|
2690 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_FIT); |
2691 | e1833e1f | j_mayer | return;
|
2692 | e1833e1f | j_mayer | } |
2693 | e1833e1f | j_mayer | /* Programmable interval timer on embedded PowerPC */
|
2694 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) { |
2695 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
|
2696 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_PIT); |
2697 | e1833e1f | j_mayer | return;
|
2698 | e1833e1f | j_mayer | } |
2699 | 47103572 | j_mayer | /* Decrementer exception */
|
2700 | 47103572 | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) { |
2701 | 47103572 | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
|
2702 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DECR); |
2703 | e1833e1f | j_mayer | return;
|
2704 | e1833e1f | j_mayer | } |
2705 | 47103572 | j_mayer | /* External interrupt */
|
2706 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) { |
2707 | e9df014c | j_mayer | /* Taking an external interrupt does not clear the external
|
2708 | e9df014c | j_mayer | * interrupt status
|
2709 | e9df014c | j_mayer | */
|
2710 | e9df014c | j_mayer | #if 0
|
2711 | 47103572 | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
|
2712 | e9df014c | j_mayer | #endif
|
2713 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL); |
2714 | e1833e1f | j_mayer | return;
|
2715 | e1833e1f | j_mayer | } |
2716 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) { |
2717 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
|
2718 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORI); |
2719 | e1833e1f | j_mayer | return;
|
2720 | 47103572 | j_mayer | } |
2721 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) { |
2722 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM);
|
2723 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_PERFM); |
2724 | e1833e1f | j_mayer | return;
|
2725 | e1833e1f | j_mayer | } |
2726 | e1833e1f | j_mayer | /* Thermal interrupt */
|
2727 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) { |
2728 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
|
2729 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_THERM); |
2730 | e1833e1f | j_mayer | return;
|
2731 | e1833e1f | j_mayer | } |
2732 | 47103572 | j_mayer | } |
2733 | 47103572 | j_mayer | } |
2734 | 18fba28c | bellard | #endif /* !CONFIG_USER_ONLY */ |
2735 | a496775f | j_mayer | |
2736 | 4a057712 | j_mayer | void cpu_dump_rfi (target_ulong RA, target_ulong msr)
|
2737 | 4a057712 | j_mayer | { |
2738 | 4a057712 | j_mayer | FILE *f; |
2739 | 4a057712 | j_mayer | |
2740 | 4a057712 | j_mayer | if (logfile) {
|
2741 | 4a057712 | j_mayer | f = logfile; |
2742 | 4a057712 | j_mayer | } else {
|
2743 | 4a057712 | j_mayer | f = stdout; |
2744 | 4a057712 | j_mayer | return;
|
2745 | 4a057712 | j_mayer | } |
2746 | 4a057712 | j_mayer | fprintf(f, "Return from exception at " ADDRX " with flags " ADDRX "\n", |
2747 | 4a057712 | j_mayer | RA, msr); |
2748 | a496775f | j_mayer | } |
2749 | a496775f | j_mayer | |
2750 | 0a032cbe | j_mayer | void cpu_ppc_reset (void *opaque) |
2751 | 0a032cbe | j_mayer | { |
2752 | 0a032cbe | j_mayer | CPUPPCState *env; |
2753 | 0411a972 | j_mayer | target_ulong msr; |
2754 | 0a032cbe | j_mayer | |
2755 | 0a032cbe | j_mayer | env = opaque; |
2756 | 0411a972 | j_mayer | msr = (target_ulong)0;
|
2757 | a4f30719 | j_mayer | if (0) { |
2758 | a4f30719 | j_mayer | /* XXX: find a suitable condition to enable the hypervisor mode */
|
2759 | a4f30719 | j_mayer | msr |= (target_ulong)MSR_HVB; |
2760 | a4f30719 | j_mayer | } |
2761 | 0411a972 | j_mayer | msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */ |
2762 | 0411a972 | j_mayer | msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */ |
2763 | 0411a972 | j_mayer | msr |= (target_ulong)1 << MSR_EP;
|
2764 | 0a032cbe | j_mayer | #if defined (DO_SINGLE_STEP) && 0 |
2765 | 0a032cbe | j_mayer | /* Single step trace mode */
|
2766 | 0411a972 | j_mayer | msr |= (target_ulong)1 << MSR_SE;
|
2767 | 0411a972 | j_mayer | msr |= (target_ulong)1 << MSR_BE;
|
2768 | 0a032cbe | j_mayer | #endif
|
2769 | 0a032cbe | j_mayer | #if defined(CONFIG_USER_ONLY)
|
2770 | 0411a972 | j_mayer | msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ |
2771 | 4c2ab988 | aurel32 | msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ |
2772 | 4c2ab988 | aurel32 | msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ |
2773 | 0411a972 | j_mayer | msr |= (target_ulong)1 << MSR_PR;
|
2774 | fe463b7d | aurel32 | env->msr = msr & env->msr_mask; |
2775 | 0a032cbe | j_mayer | #else
|
2776 | 1c27f8fb | j_mayer | env->nip = env->hreset_vector | env->excp_prefix; |
2777 | b4095fed | j_mayer | if (env->mmu_model != POWERPC_MMU_REAL)
|
2778 | 141c8ae2 | j_mayer | ppc_tlb_invalidate_all(env); |
2779 | 0a032cbe | j_mayer | #endif
|
2780 | 0411a972 | j_mayer | hreg_compute_hflags(env); |
2781 | 6f2d8978 | j_mayer | env->reserve = (target_ulong)-1ULL;
|
2782 | 5eb7995e | j_mayer | /* Be sure no exception or interrupt is pending */
|
2783 | 5eb7995e | j_mayer | env->pending_interrupts = 0;
|
2784 | e1833e1f | j_mayer | env->exception_index = POWERPC_EXCP_NONE; |
2785 | e1833e1f | j_mayer | env->error_code = 0;
|
2786 | 5eb7995e | j_mayer | /* Flush all TLBs */
|
2787 | 5eb7995e | j_mayer | tlb_flush(env, 1);
|
2788 | 0a032cbe | j_mayer | } |
2789 | 0a032cbe | j_mayer | |
2790 | aaed909a | bellard | CPUPPCState *cpu_ppc_init (const char *cpu_model) |
2791 | 0a032cbe | j_mayer | { |
2792 | 0a032cbe | j_mayer | CPUPPCState *env; |
2793 | aaed909a | bellard | const ppc_def_t *def;
|
2794 | aaed909a | bellard | |
2795 | aaed909a | bellard | def = cpu_ppc_find_by_name(cpu_model); |
2796 | aaed909a | bellard | if (!def)
|
2797 | aaed909a | bellard | return NULL; |
2798 | 0a032cbe | j_mayer | |
2799 | 0a032cbe | j_mayer | env = qemu_mallocz(sizeof(CPUPPCState));
|
2800 | 0a032cbe | j_mayer | if (!env)
|
2801 | 0a032cbe | j_mayer | return NULL; |
2802 | 0a032cbe | j_mayer | cpu_exec_init(env); |
2803 | 2e70f6ef | pbrook | ppc_translate_init(); |
2804 | 01ba9816 | ths | env->cpu_model_str = cpu_model; |
2805 | aaed909a | bellard | cpu_ppc_register_internal(env, def); |
2806 | aaed909a | bellard | cpu_ppc_reset(env); |
2807 | d76d1650 | aurel32 | |
2808 | d76d1650 | aurel32 | if (kvm_enabled())
|
2809 | d76d1650 | aurel32 | kvm_init_vcpu(env); |
2810 | d76d1650 | aurel32 | |
2811 | 0a032cbe | j_mayer | return env;
|
2812 | 0a032cbe | j_mayer | } |
2813 | 0a032cbe | j_mayer | |
2814 | 0a032cbe | j_mayer | void cpu_ppc_close (CPUPPCState *env)
|
2815 | 0a032cbe | j_mayer | { |
2816 | 0a032cbe | j_mayer | /* Should also remove all opcode tables... */
|
2817 | aaed909a | bellard | qemu_free(env); |
2818 | 0a032cbe | j_mayer | } |