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1 | 05ee37eb | balrog | /*
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2 | 05ee37eb | balrog | * CFI parallel flash with Intel command set emulation
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3 | 05ee37eb | balrog | *
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4 | 05ee37eb | balrog | * Copyright (c) 2006 Thorsten Zitterell
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5 | 05ee37eb | balrog | * Copyright (c) 2005 Jocelyn Mayer
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6 | 05ee37eb | balrog | *
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7 | 05ee37eb | balrog | * This library is free software; you can redistribute it and/or
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8 | 05ee37eb | balrog | * modify it under the terms of the GNU Lesser General Public
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9 | 05ee37eb | balrog | * License as published by the Free Software Foundation; either
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10 | 05ee37eb | balrog | * version 2 of the License, or (at your option) any later version.
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11 | 05ee37eb | balrog | *
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12 | 05ee37eb | balrog | * This library is distributed in the hope that it will be useful,
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13 | 05ee37eb | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 05ee37eb | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 05ee37eb | balrog | * Lesser General Public License for more details.
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16 | 05ee37eb | balrog | *
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17 | 05ee37eb | balrog | * You should have received a copy of the GNU Lesser General Public
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18 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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19 | 05ee37eb | balrog | */
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20 | 05ee37eb | balrog | |
21 | 05ee37eb | balrog | /*
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22 | 05ee37eb | balrog | * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
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23 | 05ee37eb | balrog | * Supported commands/modes are:
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24 | 05ee37eb | balrog | * - flash read
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25 | 05ee37eb | balrog | * - flash write
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26 | 05ee37eb | balrog | * - flash ID read
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27 | 05ee37eb | balrog | * - sector erase
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28 | 05ee37eb | balrog | * - CFI queries
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29 | 05ee37eb | balrog | *
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30 | 05ee37eb | balrog | * It does not support timings
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31 | 05ee37eb | balrog | * It does not support flash interleaving
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32 | 05ee37eb | balrog | * It does not implement software data protection as found in many real chips
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33 | 05ee37eb | balrog | * It does not implement erase suspend/resume commands
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34 | 05ee37eb | balrog | * It does not implement multiple sectors erase
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35 | 05ee37eb | balrog | *
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36 | 05ee37eb | balrog | * It does not implement much more ...
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37 | 05ee37eb | balrog | */
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38 | 05ee37eb | balrog | |
39 | 87ecb68b | pbrook | #include "hw.h" |
40 | 87ecb68b | pbrook | #include "flash.h" |
41 | 87ecb68b | pbrook | #include "block.h" |
42 | 87ecb68b | pbrook | #include "qemu-timer.h" |
43 | 05ee37eb | balrog | |
44 | 001faf32 | Blue Swirl | #define PFLASH_BUG(fmt, ...) \
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45 | 05ee37eb | balrog | do { \
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46 | 001faf32 | Blue Swirl | printf("PFLASH: Possible BUG - " fmt, ## __VA_ARGS__); \ |
47 | 05ee37eb | balrog | exit(1); \
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48 | 05ee37eb | balrog | } while(0) |
49 | 05ee37eb | balrog | |
50 | 05ee37eb | balrog | /* #define PFLASH_DEBUG */
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51 | 05ee37eb | balrog | #ifdef PFLASH_DEBUG
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52 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) \
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53 | 05ee37eb | balrog | do { \
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54 | 001faf32 | Blue Swirl | printf("PFLASH: " fmt , ## __VA_ARGS__); \ |
55 | 05ee37eb | balrog | } while (0) |
56 | 05ee37eb | balrog | #else
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57 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) do { } while (0) |
58 | 05ee37eb | balrog | #endif
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59 | 05ee37eb | balrog | |
60 | c227f099 | Anthony Liguori | struct pflash_t {
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61 | 05ee37eb | balrog | BlockDriverState *bs; |
62 | c227f099 | Anthony Liguori | target_phys_addr_t base; |
63 | c227f099 | Anthony Liguori | target_phys_addr_t sector_len; |
64 | c227f099 | Anthony Liguori | target_phys_addr_t total_len; |
65 | 05ee37eb | balrog | int width;
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66 | 05ee37eb | balrog | int wcycle; /* if 0, the flash is read normally */ |
67 | 05ee37eb | balrog | int bypass;
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68 | 05ee37eb | balrog | int ro;
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69 | 05ee37eb | balrog | uint8_t cmd; |
70 | 05ee37eb | balrog | uint8_t status; |
71 | 05ee37eb | balrog | uint16_t ident[4];
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72 | 05ee37eb | balrog | uint8_t cfi_len; |
73 | 05ee37eb | balrog | uint8_t cfi_table[0x52];
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74 | c227f099 | Anthony Liguori | target_phys_addr_t counter; |
75 | b4bf0a9a | Edgar E. Iglesias | unsigned int writeblock_size; |
76 | 05ee37eb | balrog | QEMUTimer *timer; |
77 | c227f099 | Anthony Liguori | ram_addr_t off; |
78 | 05ee37eb | balrog | int fl_mem;
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79 | 05ee37eb | balrog | void *storage;
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80 | 05ee37eb | balrog | }; |
81 | 05ee37eb | balrog | |
82 | 05ee37eb | balrog | static void pflash_timer (void *opaque) |
83 | 05ee37eb | balrog | { |
84 | c227f099 | Anthony Liguori | pflash_t *pfl = opaque; |
85 | 05ee37eb | balrog | |
86 | 05ee37eb | balrog | DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
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87 | 05ee37eb | balrog | /* Reset flash */
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88 | 05ee37eb | balrog | pfl->status ^= 0x80;
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89 | 05ee37eb | balrog | if (pfl->bypass) {
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90 | 05ee37eb | balrog | pfl->wcycle = 2;
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91 | 05ee37eb | balrog | } else {
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92 | 05ee37eb | balrog | cpu_register_physical_memory(pfl->base, pfl->total_len, |
93 | 05ee37eb | balrog | pfl->off | IO_MEM_ROMD | pfl->fl_mem); |
94 | 05ee37eb | balrog | pfl->wcycle = 0;
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95 | 05ee37eb | balrog | } |
96 | 05ee37eb | balrog | pfl->cmd = 0;
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97 | 05ee37eb | balrog | } |
98 | 05ee37eb | balrog | |
99 | c227f099 | Anthony Liguori | static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset,
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100 | 3d08ff69 | Blue Swirl | int width, int be) |
101 | 05ee37eb | balrog | { |
102 | c227f099 | Anthony Liguori | target_phys_addr_t boff; |
103 | 05ee37eb | balrog | uint32_t ret; |
104 | 05ee37eb | balrog | uint8_t *p; |
105 | 05ee37eb | balrog | |
106 | 05ee37eb | balrog | ret = -1;
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107 | 05ee37eb | balrog | boff = offset & 0xFF; /* why this here ?? */ |
108 | 05ee37eb | balrog | |
109 | 05ee37eb | balrog | if (pfl->width == 2) |
110 | 05ee37eb | balrog | boff = boff >> 1;
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111 | 05ee37eb | balrog | else if (pfl->width == 4) |
112 | 05ee37eb | balrog | boff = boff >> 2;
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113 | 05ee37eb | balrog | |
114 | fad8c772 | Edgar E. Iglesias | #if 0
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115 | fad8c772 | Edgar E. Iglesias | DPRINTF("%s: reading offset " TARGET_FMT_plx " under cmd %02x width %d\n",
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116 | 06adb549 | balrog | __func__, offset, pfl->cmd, width);
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117 | fad8c772 | Edgar E. Iglesias | #endif
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118 | 05ee37eb | balrog | switch (pfl->cmd) {
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119 | 05ee37eb | balrog | case 0x00: |
120 | 05ee37eb | balrog | /* Flash area read */
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121 | 05ee37eb | balrog | p = pfl->storage; |
122 | 05ee37eb | balrog | switch (width) {
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123 | 05ee37eb | balrog | case 1: |
124 | 05ee37eb | balrog | ret = p[offset]; |
125 | fad8c772 | Edgar E. Iglesias | DPRINTF("%s: data offset " TARGET_FMT_plx " %02x\n", |
126 | c8b153d7 | ths | __func__, offset, ret); |
127 | 05ee37eb | balrog | break;
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128 | 05ee37eb | balrog | case 2: |
129 | 3d08ff69 | Blue Swirl | if (be) {
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130 | 3d08ff69 | Blue Swirl | ret = p[offset] << 8;
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131 | 3d08ff69 | Blue Swirl | ret |= p[offset + 1];
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132 | 3d08ff69 | Blue Swirl | } else {
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133 | 3d08ff69 | Blue Swirl | ret = p[offset]; |
134 | 3d08ff69 | Blue Swirl | ret |= p[offset + 1] << 8; |
135 | 3d08ff69 | Blue Swirl | } |
136 | fad8c772 | Edgar E. Iglesias | DPRINTF("%s: data offset " TARGET_FMT_plx " %04x\n", |
137 | c8b153d7 | ths | __func__, offset, ret); |
138 | 05ee37eb | balrog | break;
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139 | 05ee37eb | balrog | case 4: |
140 | 3d08ff69 | Blue Swirl | if (be) {
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141 | 3d08ff69 | Blue Swirl | ret = p[offset] << 24;
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142 | 3d08ff69 | Blue Swirl | ret |= p[offset + 1] << 16; |
143 | 3d08ff69 | Blue Swirl | ret |= p[offset + 2] << 8; |
144 | 3d08ff69 | Blue Swirl | ret |= p[offset + 3];
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145 | 3d08ff69 | Blue Swirl | } else {
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146 | 3d08ff69 | Blue Swirl | ret = p[offset]; |
147 | 3d08ff69 | Blue Swirl | ret |= p[offset + 1] << 8; |
148 | 3d08ff69 | Blue Swirl | ret |= p[offset + 1] << 8; |
149 | 3d08ff69 | Blue Swirl | ret |= p[offset + 2] << 16; |
150 | 3d08ff69 | Blue Swirl | ret |= p[offset + 3] << 24; |
151 | 3d08ff69 | Blue Swirl | } |
152 | fad8c772 | Edgar E. Iglesias | DPRINTF("%s: data offset " TARGET_FMT_plx " %08x\n", |
153 | c8b153d7 | ths | __func__, offset, ret); |
154 | 05ee37eb | balrog | break;
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155 | 05ee37eb | balrog | default:
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156 | 05ee37eb | balrog | DPRINTF("BUG in %s\n", __func__);
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157 | 05ee37eb | balrog | } |
158 | 05ee37eb | balrog | |
159 | 05ee37eb | balrog | break;
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160 | 05ee37eb | balrog | case 0x20: /* Block erase */ |
161 | 05ee37eb | balrog | case 0x50: /* Clear status register */ |
162 | 05ee37eb | balrog | case 0x60: /* Block /un)lock */ |
163 | 05ee37eb | balrog | case 0x70: /* Status Register */ |
164 | 05ee37eb | balrog | case 0xe8: /* Write block */ |
165 | 05ee37eb | balrog | /* Status register read */
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166 | 05ee37eb | balrog | ret = pfl->status; |
167 | 05ee37eb | balrog | DPRINTF("%s: status %x\n", __func__, ret);
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168 | 05ee37eb | balrog | break;
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169 | 0b2ec6fc | Michael Walle | case 0x90: |
170 | 0b2ec6fc | Michael Walle | switch (boff) {
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171 | 0b2ec6fc | Michael Walle | case 0: |
172 | 0b2ec6fc | Michael Walle | ret = pfl->ident[0] << 8 | pfl->ident[1]; |
173 | 0b2ec6fc | Michael Walle | DPRINTF("%s: Manufacturer Code %04x\n", __func__, ret);
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174 | 0b2ec6fc | Michael Walle | break;
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175 | 0b2ec6fc | Michael Walle | case 1: |
176 | 0b2ec6fc | Michael Walle | ret = pfl->ident[2] << 8 | pfl->ident[3]; |
177 | 0b2ec6fc | Michael Walle | DPRINTF("%s: Device ID Code %04x\n", __func__, ret);
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178 | 0b2ec6fc | Michael Walle | break;
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179 | 0b2ec6fc | Michael Walle | default:
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180 | 0b2ec6fc | Michael Walle | DPRINTF("%s: Read Device Information boff=%x\n", __func__, boff);
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181 | 0b2ec6fc | Michael Walle | ret = 0;
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182 | 0b2ec6fc | Michael Walle | break;
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183 | 0b2ec6fc | Michael Walle | } |
184 | 0b2ec6fc | Michael Walle | break;
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185 | 05ee37eb | balrog | case 0x98: /* Query mode */ |
186 | 05ee37eb | balrog | if (boff > pfl->cfi_len)
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187 | 05ee37eb | balrog | ret = 0;
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188 | 05ee37eb | balrog | else
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189 | 05ee37eb | balrog | ret = pfl->cfi_table[boff]; |
190 | 05ee37eb | balrog | break;
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191 | 05ee37eb | balrog | default:
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192 | 05ee37eb | balrog | /* This should never happen : reset state & treat it as a read */
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193 | 05ee37eb | balrog | DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
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194 | 05ee37eb | balrog | pfl->wcycle = 0;
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195 | 05ee37eb | balrog | pfl->cmd = 0;
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196 | 05ee37eb | balrog | } |
197 | 05ee37eb | balrog | return ret;
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198 | 05ee37eb | balrog | } |
199 | 05ee37eb | balrog | |
200 | 05ee37eb | balrog | /* update flash content on disk */
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201 | c227f099 | Anthony Liguori | static void pflash_update(pflash_t *pfl, int offset, |
202 | 05ee37eb | balrog | int size)
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203 | 05ee37eb | balrog | { |
204 | 05ee37eb | balrog | int offset_end;
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205 | 05ee37eb | balrog | if (pfl->bs) {
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206 | 05ee37eb | balrog | offset_end = offset + size; |
207 | 05ee37eb | balrog | /* round to sectors */
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208 | 05ee37eb | balrog | offset = offset >> 9;
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209 | 05ee37eb | balrog | offset_end = (offset_end + 511) >> 9; |
210 | 05ee37eb | balrog | bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9),
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211 | 05ee37eb | balrog | offset_end - offset); |
212 | 05ee37eb | balrog | } |
213 | 05ee37eb | balrog | } |
214 | 05ee37eb | balrog | |
215 | c227f099 | Anthony Liguori | static inline void pflash_data_write(pflash_t *pfl, target_phys_addr_t offset, |
216 | 3d08ff69 | Blue Swirl | uint32_t value, int width, int be) |
217 | d361be25 | balrog | { |
218 | d361be25 | balrog | uint8_t *p = pfl->storage; |
219 | d361be25 | balrog | |
220 | fad8c772 | Edgar E. Iglesias | DPRINTF("%s: block write offset " TARGET_FMT_plx
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221 | fad8c772 | Edgar E. Iglesias | " value %x counter " TARGET_FMT_plx "\n", |
222 | d361be25 | balrog | __func__, offset, value, pfl->counter); |
223 | d361be25 | balrog | switch (width) {
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224 | d361be25 | balrog | case 1: |
225 | d361be25 | balrog | p[offset] = value; |
226 | d361be25 | balrog | break;
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227 | d361be25 | balrog | case 2: |
228 | 3d08ff69 | Blue Swirl | if (be) {
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229 | 3d08ff69 | Blue Swirl | p[offset] = value >> 8;
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230 | 3d08ff69 | Blue Swirl | p[offset + 1] = value;
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231 | 3d08ff69 | Blue Swirl | } else {
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232 | 3d08ff69 | Blue Swirl | p[offset] = value; |
233 | 3d08ff69 | Blue Swirl | p[offset + 1] = value >> 8; |
234 | 3d08ff69 | Blue Swirl | } |
235 | d361be25 | balrog | break;
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236 | d361be25 | balrog | case 4: |
237 | 3d08ff69 | Blue Swirl | if (be) {
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238 | 3d08ff69 | Blue Swirl | p[offset] = value >> 24;
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239 | 3d08ff69 | Blue Swirl | p[offset + 1] = value >> 16; |
240 | 3d08ff69 | Blue Swirl | p[offset + 2] = value >> 8; |
241 | 3d08ff69 | Blue Swirl | p[offset + 3] = value;
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242 | 3d08ff69 | Blue Swirl | } else {
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243 | 3d08ff69 | Blue Swirl | p[offset] = value; |
244 | 3d08ff69 | Blue Swirl | p[offset + 1] = value >> 8; |
245 | 3d08ff69 | Blue Swirl | p[offset + 2] = value >> 16; |
246 | 3d08ff69 | Blue Swirl | p[offset + 3] = value >> 24; |
247 | 3d08ff69 | Blue Swirl | } |
248 | d361be25 | balrog | break;
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249 | d361be25 | balrog | } |
250 | d361be25 | balrog | |
251 | d361be25 | balrog | } |
252 | d361be25 | balrog | |
253 | c227f099 | Anthony Liguori | static void pflash_write(pflash_t *pfl, target_phys_addr_t offset, |
254 | 3d08ff69 | Blue Swirl | uint32_t value, int width, int be) |
255 | 05ee37eb | balrog | { |
256 | 05ee37eb | balrog | uint8_t *p; |
257 | 05ee37eb | balrog | uint8_t cmd; |
258 | 05ee37eb | balrog | |
259 | 05ee37eb | balrog | cmd = value; |
260 | 05ee37eb | balrog | |
261 | fad8c772 | Edgar E. Iglesias | DPRINTF("%s: writing offset " TARGET_FMT_plx " value %08x width %d wcycle 0x%x\n", |
262 | c8b153d7 | ths | __func__, offset, value, width, pfl->wcycle); |
263 | 05ee37eb | balrog | |
264 | e9cbbcac | Edgar E. Iglesias | if (!pfl->wcycle) {
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265 | e9cbbcac | Edgar E. Iglesias | /* Set the device in I/O access mode */
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266 | e9cbbcac | Edgar E. Iglesias | cpu_register_physical_memory(pfl->base, pfl->total_len, pfl->fl_mem); |
267 | e9cbbcac | Edgar E. Iglesias | } |
268 | 05ee37eb | balrog | |
269 | 05ee37eb | balrog | switch (pfl->wcycle) {
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270 | 05ee37eb | balrog | case 0: |
271 | 05ee37eb | balrog | /* read mode */
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272 | 05ee37eb | balrog | switch (cmd) {
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273 | 05ee37eb | balrog | case 0x00: /* ??? */ |
274 | 05ee37eb | balrog | goto reset_flash;
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275 | d361be25 | balrog | case 0x10: /* Single Byte Program */ |
276 | d361be25 | balrog | case 0x40: /* Single Byte Program */ |
277 | fad8c772 | Edgar E. Iglesias | DPRINTF("%s: Single Byte Program\n", __func__);
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278 | d361be25 | balrog | break;
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279 | 05ee37eb | balrog | case 0x20: /* Block erase */ |
280 | 05ee37eb | balrog | p = pfl->storage; |
281 | 05ee37eb | balrog | offset &= ~(pfl->sector_len - 1);
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282 | 05ee37eb | balrog | |
283 | fad8c772 | Edgar E. Iglesias | DPRINTF("%s: block erase at " TARGET_FMT_plx " bytes " |
284 | fad8c772 | Edgar E. Iglesias | TARGET_FMT_plx "\n",
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285 | c8b153d7 | ths | __func__, offset, pfl->sector_len); |
286 | 05ee37eb | balrog | |
287 | 05ee37eb | balrog | memset(p + offset, 0xff, pfl->sector_len);
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288 | 05ee37eb | balrog | pflash_update(pfl, offset, pfl->sector_len); |
289 | 05ee37eb | balrog | pfl->status |= 0x80; /* Ready! */ |
290 | 05ee37eb | balrog | break;
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291 | 05ee37eb | balrog | case 0x50: /* Clear status bits */ |
292 | 05ee37eb | balrog | DPRINTF("%s: Clear status bits\n", __func__);
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293 | 05ee37eb | balrog | pfl->status = 0x0;
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294 | 05ee37eb | balrog | goto reset_flash;
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295 | 05ee37eb | balrog | case 0x60: /* Block (un)lock */ |
296 | 05ee37eb | balrog | DPRINTF("%s: Block unlock\n", __func__);
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297 | 05ee37eb | balrog | break;
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298 | 05ee37eb | balrog | case 0x70: /* Status Register */ |
299 | 05ee37eb | balrog | DPRINTF("%s: Read status register\n", __func__);
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300 | 05ee37eb | balrog | pfl->cmd = cmd; |
301 | 05ee37eb | balrog | return;
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302 | 0b2ec6fc | Michael Walle | case 0x90: /* Read Device ID */ |
303 | 0b2ec6fc | Michael Walle | DPRINTF("%s: Read Device information\n", __func__);
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304 | 0b2ec6fc | Michael Walle | pfl->cmd = cmd; |
305 | 0b2ec6fc | Michael Walle | return;
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306 | 05ee37eb | balrog | case 0x98: /* CFI query */ |
307 | 05ee37eb | balrog | DPRINTF("%s: CFI query\n", __func__);
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308 | 05ee37eb | balrog | break;
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309 | 05ee37eb | balrog | case 0xe8: /* Write to buffer */ |
310 | 05ee37eb | balrog | DPRINTF("%s: Write to buffer\n", __func__);
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311 | 05ee37eb | balrog | pfl->status |= 0x80; /* Ready! */ |
312 | 05ee37eb | balrog | break;
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313 | 05ee37eb | balrog | case 0xff: /* Read array mode */ |
314 | 05ee37eb | balrog | DPRINTF("%s: Read array mode\n", __func__);
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315 | 05ee37eb | balrog | goto reset_flash;
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316 | 05ee37eb | balrog | default:
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317 | 05ee37eb | balrog | goto error_flash;
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318 | 05ee37eb | balrog | } |
319 | 05ee37eb | balrog | pfl->wcycle++; |
320 | 05ee37eb | balrog | pfl->cmd = cmd; |
321 | 05ee37eb | balrog | return;
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322 | 05ee37eb | balrog | case 1: |
323 | 05ee37eb | balrog | switch (pfl->cmd) {
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324 | d361be25 | balrog | case 0x10: /* Single Byte Program */ |
325 | d361be25 | balrog | case 0x40: /* Single Byte Program */ |
326 | d361be25 | balrog | DPRINTF("%s: Single Byte Program\n", __func__);
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327 | 3d08ff69 | Blue Swirl | pflash_data_write(pfl, offset, value, width, be); |
328 | b4bf0a9a | Edgar E. Iglesias | pflash_update(pfl, offset, width); |
329 | d361be25 | balrog | pfl->status |= 0x80; /* Ready! */ |
330 | d361be25 | balrog | pfl->wcycle = 0;
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331 | d361be25 | balrog | break;
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332 | 05ee37eb | balrog | case 0x20: /* Block erase */ |
333 | 05ee37eb | balrog | case 0x28: |
334 | 05ee37eb | balrog | if (cmd == 0xd0) { /* confirm */ |
335 | 3656744c | balrog | pfl->wcycle = 0;
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336 | 05ee37eb | balrog | pfl->status |= 0x80;
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337 | 9248f413 | aurel32 | } else if (cmd == 0xff) { /* read array mode */ |
338 | 05ee37eb | balrog | goto reset_flash;
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339 | 05ee37eb | balrog | } else
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340 | 05ee37eb | balrog | goto error_flash;
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341 | 05ee37eb | balrog | |
342 | 05ee37eb | balrog | break;
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343 | 05ee37eb | balrog | case 0xe8: |
344 | 71fb2348 | balrog | DPRINTF("%s: block write of %x bytes\n", __func__, value);
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345 | 71fb2348 | balrog | pfl->counter = value; |
346 | 05ee37eb | balrog | pfl->wcycle++; |
347 | 05ee37eb | balrog | break;
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348 | 05ee37eb | balrog | case 0x60: |
349 | 05ee37eb | balrog | if (cmd == 0xd0) { |
350 | 05ee37eb | balrog | pfl->wcycle = 0;
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351 | 05ee37eb | balrog | pfl->status |= 0x80;
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352 | 05ee37eb | balrog | } else if (cmd == 0x01) { |
353 | 05ee37eb | balrog | pfl->wcycle = 0;
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354 | 05ee37eb | balrog | pfl->status |= 0x80;
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355 | 05ee37eb | balrog | } else if (cmd == 0xff) { |
356 | 05ee37eb | balrog | goto reset_flash;
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357 | 05ee37eb | balrog | } else {
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358 | 05ee37eb | balrog | DPRINTF("%s: Unknown (un)locking command\n", __func__);
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359 | 05ee37eb | balrog | goto reset_flash;
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360 | 05ee37eb | balrog | } |
361 | 05ee37eb | balrog | break;
|
362 | 05ee37eb | balrog | case 0x98: |
363 | 05ee37eb | balrog | if (cmd == 0xff) { |
364 | 05ee37eb | balrog | goto reset_flash;
|
365 | 05ee37eb | balrog | } else {
|
366 | 05ee37eb | balrog | DPRINTF("%s: leaving query mode\n", __func__);
|
367 | 05ee37eb | balrog | } |
368 | 05ee37eb | balrog | break;
|
369 | 05ee37eb | balrog | default:
|
370 | 05ee37eb | balrog | goto error_flash;
|
371 | 05ee37eb | balrog | } |
372 | 05ee37eb | balrog | return;
|
373 | 05ee37eb | balrog | case 2: |
374 | 05ee37eb | balrog | switch (pfl->cmd) {
|
375 | 05ee37eb | balrog | case 0xe8: /* Block write */ |
376 | 3d08ff69 | Blue Swirl | pflash_data_write(pfl, offset, value, width, be); |
377 | 05ee37eb | balrog | |
378 | 05ee37eb | balrog | pfl->status |= 0x80;
|
379 | 05ee37eb | balrog | |
380 | 05ee37eb | balrog | if (!pfl->counter) {
|
381 | b4bf0a9a | Edgar E. Iglesias | target_phys_addr_t mask = pfl->writeblock_size - 1;
|
382 | b4bf0a9a | Edgar E. Iglesias | mask = ~mask; |
383 | b4bf0a9a | Edgar E. Iglesias | |
384 | 05ee37eb | balrog | DPRINTF("%s: block write finished\n", __func__);
|
385 | 05ee37eb | balrog | pfl->wcycle++; |
386 | b4bf0a9a | Edgar E. Iglesias | /* Flush the entire write buffer onto backing storage. */
|
387 | b4bf0a9a | Edgar E. Iglesias | pflash_update(pfl, offset & mask, pfl->writeblock_size); |
388 | 05ee37eb | balrog | } |
389 | 05ee37eb | balrog | |
390 | 05ee37eb | balrog | pfl->counter--; |
391 | 05ee37eb | balrog | break;
|
392 | 7317b8ca | balrog | default:
|
393 | 7317b8ca | balrog | goto error_flash;
|
394 | 05ee37eb | balrog | } |
395 | 05ee37eb | balrog | return;
|
396 | 05ee37eb | balrog | case 3: /* Confirm mode */ |
397 | 05ee37eb | balrog | switch (pfl->cmd) {
|
398 | 05ee37eb | balrog | case 0xe8: /* Block write */ |
399 | 05ee37eb | balrog | if (cmd == 0xd0) { |
400 | 05ee37eb | balrog | pfl->wcycle = 0;
|
401 | 05ee37eb | balrog | pfl->status |= 0x80;
|
402 | 05ee37eb | balrog | } else {
|
403 | 05ee37eb | balrog | DPRINTF("%s: unknown command for \"write block\"\n", __func__);
|
404 | 05ee37eb | balrog | PFLASH_BUG("Write block confirm");
|
405 | 7317b8ca | balrog | goto reset_flash;
|
406 | 05ee37eb | balrog | } |
407 | 7317b8ca | balrog | break;
|
408 | 7317b8ca | balrog | default:
|
409 | 7317b8ca | balrog | goto error_flash;
|
410 | 05ee37eb | balrog | } |
411 | 05ee37eb | balrog | return;
|
412 | 05ee37eb | balrog | default:
|
413 | 05ee37eb | balrog | /* Should never happen */
|
414 | 05ee37eb | balrog | DPRINTF("%s: invalid write state\n", __func__);
|
415 | 05ee37eb | balrog | goto reset_flash;
|
416 | 05ee37eb | balrog | } |
417 | 05ee37eb | balrog | return;
|
418 | 05ee37eb | balrog | |
419 | 05ee37eb | balrog | error_flash:
|
420 | 05ee37eb | balrog | printf("%s: Unimplemented flash cmd sequence "
|
421 | 42a89d77 | Paul Brook | "(offset " TARGET_FMT_plx ", wcycle 0x%x cmd 0x%x value 0x%x)\n", |
422 | c8b153d7 | ths | __func__, offset, pfl->wcycle, pfl->cmd, value); |
423 | 05ee37eb | balrog | |
424 | 05ee37eb | balrog | reset_flash:
|
425 | 05ee37eb | balrog | cpu_register_physical_memory(pfl->base, pfl->total_len, |
426 | 05ee37eb | balrog | pfl->off | IO_MEM_ROMD | pfl->fl_mem); |
427 | 05ee37eb | balrog | |
428 | 05ee37eb | balrog | pfl->bypass = 0;
|
429 | 05ee37eb | balrog | pfl->wcycle = 0;
|
430 | 05ee37eb | balrog | pfl->cmd = 0;
|
431 | 05ee37eb | balrog | return;
|
432 | 05ee37eb | balrog | } |
433 | 05ee37eb | balrog | |
434 | 05ee37eb | balrog | |
435 | 3d08ff69 | Blue Swirl | static uint32_t pflash_readb_be(void *opaque, target_phys_addr_t addr) |
436 | 3d08ff69 | Blue Swirl | { |
437 | 3d08ff69 | Blue Swirl | return pflash_read(opaque, addr, 1, 1); |
438 | 3d08ff69 | Blue Swirl | } |
439 | 3d08ff69 | Blue Swirl | |
440 | 3d08ff69 | Blue Swirl | static uint32_t pflash_readb_le(void *opaque, target_phys_addr_t addr) |
441 | 3d08ff69 | Blue Swirl | { |
442 | 3d08ff69 | Blue Swirl | return pflash_read(opaque, addr, 1, 0); |
443 | 3d08ff69 | Blue Swirl | } |
444 | 3d08ff69 | Blue Swirl | |
445 | 3d08ff69 | Blue Swirl | static uint32_t pflash_readw_be(void *opaque, target_phys_addr_t addr) |
446 | 3d08ff69 | Blue Swirl | { |
447 | 3d08ff69 | Blue Swirl | pflash_t *pfl = opaque; |
448 | 3d08ff69 | Blue Swirl | |
449 | 3d08ff69 | Blue Swirl | return pflash_read(pfl, addr, 2, 1); |
450 | 3d08ff69 | Blue Swirl | } |
451 | 3d08ff69 | Blue Swirl | |
452 | 3d08ff69 | Blue Swirl | static uint32_t pflash_readw_le(void *opaque, target_phys_addr_t addr) |
453 | 05ee37eb | balrog | { |
454 | 3d08ff69 | Blue Swirl | pflash_t *pfl = opaque; |
455 | 3d08ff69 | Blue Swirl | |
456 | 3d08ff69 | Blue Swirl | return pflash_read(pfl, addr, 2, 0); |
457 | 05ee37eb | balrog | } |
458 | 05ee37eb | balrog | |
459 | 3d08ff69 | Blue Swirl | static uint32_t pflash_readl_be(void *opaque, target_phys_addr_t addr) |
460 | 05ee37eb | balrog | { |
461 | c227f099 | Anthony Liguori | pflash_t *pfl = opaque; |
462 | 05ee37eb | balrog | |
463 | 3d08ff69 | Blue Swirl | return pflash_read(pfl, addr, 4, 1); |
464 | 05ee37eb | balrog | } |
465 | 05ee37eb | balrog | |
466 | 3d08ff69 | Blue Swirl | static uint32_t pflash_readl_le(void *opaque, target_phys_addr_t addr) |
467 | 05ee37eb | balrog | { |
468 | c227f099 | Anthony Liguori | pflash_t *pfl = opaque; |
469 | 05ee37eb | balrog | |
470 | 3d08ff69 | Blue Swirl | return pflash_read(pfl, addr, 4, 0); |
471 | 05ee37eb | balrog | } |
472 | 05ee37eb | balrog | |
473 | 3d08ff69 | Blue Swirl | static void pflash_writeb_be(void *opaque, target_phys_addr_t addr, |
474 | 3d08ff69 | Blue Swirl | uint32_t value) |
475 | 05ee37eb | balrog | { |
476 | 3d08ff69 | Blue Swirl | pflash_write(opaque, addr, value, 1, 1); |
477 | 05ee37eb | balrog | } |
478 | 05ee37eb | balrog | |
479 | 3d08ff69 | Blue Swirl | static void pflash_writeb_le(void *opaque, target_phys_addr_t addr, |
480 | 3d08ff69 | Blue Swirl | uint32_t value) |
481 | 3d08ff69 | Blue Swirl | { |
482 | 3d08ff69 | Blue Swirl | pflash_write(opaque, addr, value, 1, 0); |
483 | 3d08ff69 | Blue Swirl | } |
484 | 3d08ff69 | Blue Swirl | |
485 | 3d08ff69 | Blue Swirl | static void pflash_writew_be(void *opaque, target_phys_addr_t addr, |
486 | 3d08ff69 | Blue Swirl | uint32_t value) |
487 | 05ee37eb | balrog | { |
488 | c227f099 | Anthony Liguori | pflash_t *pfl = opaque; |
489 | 05ee37eb | balrog | |
490 | 3d08ff69 | Blue Swirl | pflash_write(pfl, addr, value, 2, 1); |
491 | 05ee37eb | balrog | } |
492 | 05ee37eb | balrog | |
493 | 3d08ff69 | Blue Swirl | static void pflash_writew_le(void *opaque, target_phys_addr_t addr, |
494 | 3d08ff69 | Blue Swirl | uint32_t value) |
495 | 05ee37eb | balrog | { |
496 | c227f099 | Anthony Liguori | pflash_t *pfl = opaque; |
497 | 05ee37eb | balrog | |
498 | 3d08ff69 | Blue Swirl | pflash_write(pfl, addr, value, 2, 0); |
499 | 05ee37eb | balrog | } |
500 | 05ee37eb | balrog | |
501 | 3d08ff69 | Blue Swirl | static void pflash_writel_be(void *opaque, target_phys_addr_t addr, |
502 | 3d08ff69 | Blue Swirl | uint32_t value) |
503 | 3d08ff69 | Blue Swirl | { |
504 | 3d08ff69 | Blue Swirl | pflash_t *pfl = opaque; |
505 | 3d08ff69 | Blue Swirl | |
506 | 3d08ff69 | Blue Swirl | pflash_write(pfl, addr, value, 4, 1); |
507 | 3d08ff69 | Blue Swirl | } |
508 | 3d08ff69 | Blue Swirl | |
509 | 3d08ff69 | Blue Swirl | static void pflash_writel_le(void *opaque, target_phys_addr_t addr, |
510 | 3d08ff69 | Blue Swirl | uint32_t value) |
511 | 3d08ff69 | Blue Swirl | { |
512 | 3d08ff69 | Blue Swirl | pflash_t *pfl = opaque; |
513 | 3d08ff69 | Blue Swirl | |
514 | 3d08ff69 | Blue Swirl | pflash_write(pfl, addr, value, 4, 0); |
515 | 3d08ff69 | Blue Swirl | } |
516 | 3d08ff69 | Blue Swirl | |
517 | 3d08ff69 | Blue Swirl | static CPUWriteMemoryFunc * const pflash_write_ops_be[] = { |
518 | 3d08ff69 | Blue Swirl | &pflash_writeb_be, |
519 | 3d08ff69 | Blue Swirl | &pflash_writew_be, |
520 | 3d08ff69 | Blue Swirl | &pflash_writel_be, |
521 | 05ee37eb | balrog | }; |
522 | 05ee37eb | balrog | |
523 | 3d08ff69 | Blue Swirl | static CPUReadMemoryFunc * const pflash_read_ops_be[] = { |
524 | 3d08ff69 | Blue Swirl | &pflash_readb_be, |
525 | 3d08ff69 | Blue Swirl | &pflash_readw_be, |
526 | 3d08ff69 | Blue Swirl | &pflash_readl_be, |
527 | 3d08ff69 | Blue Swirl | }; |
528 | 3d08ff69 | Blue Swirl | |
529 | 3d08ff69 | Blue Swirl | static CPUWriteMemoryFunc * const pflash_write_ops_le[] = { |
530 | 3d08ff69 | Blue Swirl | &pflash_writeb_le, |
531 | 3d08ff69 | Blue Swirl | &pflash_writew_le, |
532 | 3d08ff69 | Blue Swirl | &pflash_writel_le, |
533 | 3d08ff69 | Blue Swirl | }; |
534 | 3d08ff69 | Blue Swirl | |
535 | 3d08ff69 | Blue Swirl | static CPUReadMemoryFunc * const pflash_read_ops_le[] = { |
536 | 3d08ff69 | Blue Swirl | &pflash_readb_le, |
537 | 3d08ff69 | Blue Swirl | &pflash_readw_le, |
538 | 3d08ff69 | Blue Swirl | &pflash_readl_le, |
539 | 05ee37eb | balrog | }; |
540 | 05ee37eb | balrog | |
541 | 05ee37eb | balrog | /* Count trailing zeroes of a 32 bits quantity */
|
542 | 05ee37eb | balrog | static int ctz32 (uint32_t n) |
543 | 05ee37eb | balrog | { |
544 | 05ee37eb | balrog | int ret;
|
545 | 05ee37eb | balrog | |
546 | 05ee37eb | balrog | ret = 0;
|
547 | 05ee37eb | balrog | if (!(n & 0xFFFF)) { |
548 | 05ee37eb | balrog | ret += 16;
|
549 | 05ee37eb | balrog | n = n >> 16;
|
550 | 05ee37eb | balrog | } |
551 | 05ee37eb | balrog | if (!(n & 0xFF)) { |
552 | 05ee37eb | balrog | ret += 8;
|
553 | 05ee37eb | balrog | n = n >> 8;
|
554 | 05ee37eb | balrog | } |
555 | 05ee37eb | balrog | if (!(n & 0xF)) { |
556 | 05ee37eb | balrog | ret += 4;
|
557 | 05ee37eb | balrog | n = n >> 4;
|
558 | 05ee37eb | balrog | } |
559 | 05ee37eb | balrog | if (!(n & 0x3)) { |
560 | 05ee37eb | balrog | ret += 2;
|
561 | 05ee37eb | balrog | n = n >> 2;
|
562 | 05ee37eb | balrog | } |
563 | 05ee37eb | balrog | if (!(n & 0x1)) { |
564 | 05ee37eb | balrog | ret++; |
565 | 22ed1d34 | Blue Swirl | #if 0 /* This is not necessary as n is never 0 */
|
566 | 05ee37eb | balrog | n = n >> 1;
|
567 | 22ed1d34 | Blue Swirl | #endif
|
568 | 05ee37eb | balrog | } |
569 | 05ee37eb | balrog | #if 0 /* This is not necessary as n is never 0 */
|
570 | 05ee37eb | balrog | if (!n)
|
571 | 05ee37eb | balrog | ret++;
|
572 | 05ee37eb | balrog | #endif
|
573 | 05ee37eb | balrog | |
574 | 05ee37eb | balrog | return ret;
|
575 | 05ee37eb | balrog | } |
576 | 05ee37eb | balrog | |
577 | c227f099 | Anthony Liguori | pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off, |
578 | c8b153d7 | ths | BlockDriverState *bs, uint32_t sector_len, |
579 | 88eeee0a | balrog | int nb_blocs, int width, |
580 | 88eeee0a | balrog | uint16_t id0, uint16_t id1, |
581 | 3d08ff69 | Blue Swirl | uint16_t id2, uint16_t id3, |
582 | 3d08ff69 | Blue Swirl | int be)
|
583 | 05ee37eb | balrog | { |
584 | c227f099 | Anthony Liguori | pflash_t *pfl; |
585 | c227f099 | Anthony Liguori | target_phys_addr_t total_len; |
586 | d0e7605e | Vijay Kumar | int ret;
|
587 | 05ee37eb | balrog | |
588 | 05ee37eb | balrog | total_len = sector_len * nb_blocs; |
589 | 05ee37eb | balrog | |
590 | 05ee37eb | balrog | /* XXX: to be fixed */
|
591 | c8b153d7 | ths | #if 0
|
592 | 05ee37eb | balrog | if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
|
593 | 05ee37eb | balrog | total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
|
594 | 05ee37eb | balrog | return NULL;
|
595 | c8b153d7 | ths | #endif
|
596 | 05ee37eb | balrog | |
597 | c227f099 | Anthony Liguori | pfl = qemu_mallocz(sizeof(pflash_t));
|
598 | 05ee37eb | balrog | |
599 | 5c130f65 | pbrook | /* FIXME: Allocate ram ourselves. */
|
600 | 5c130f65 | pbrook | pfl->storage = qemu_get_ram_ptr(off); |
601 | 3d08ff69 | Blue Swirl | if (be) {
|
602 | 3d08ff69 | Blue Swirl | pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_be, |
603 | 2507c12a | Alexander Graf | pflash_write_ops_be, pfl, |
604 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
605 | 3d08ff69 | Blue Swirl | } else {
|
606 | 3d08ff69 | Blue Swirl | pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_le, |
607 | 2507c12a | Alexander Graf | pflash_write_ops_le, pfl, |
608 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
609 | 3d08ff69 | Blue Swirl | } |
610 | 05ee37eb | balrog | pfl->off = off; |
611 | 05ee37eb | balrog | cpu_register_physical_memory(base, total_len, |
612 | 05ee37eb | balrog | off | pfl->fl_mem | IO_MEM_ROMD); |
613 | 05ee37eb | balrog | |
614 | 05ee37eb | balrog | pfl->bs = bs; |
615 | 05ee37eb | balrog | if (pfl->bs) {
|
616 | 05ee37eb | balrog | /* read the initial flash content */
|
617 | d0e7605e | Vijay Kumar | ret = bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9); |
618 | d0e7605e | Vijay Kumar | if (ret < 0) { |
619 | d0e7605e | Vijay Kumar | cpu_unregister_io_memory(pfl->fl_mem); |
620 | d0e7605e | Vijay Kumar | qemu_free(pfl); |
621 | d0e7605e | Vijay Kumar | return NULL; |
622 | d0e7605e | Vijay Kumar | } |
623 | 05ee37eb | balrog | } |
624 | 05ee37eb | balrog | #if 0 /* XXX: there should be a bit to set up read-only,
|
625 | 05ee37eb | balrog | * the same way the hardware does (with WP pin).
|
626 | 05ee37eb | balrog | */
|
627 | 05ee37eb | balrog | pfl->ro = 1;
|
628 | 05ee37eb | balrog | #else
|
629 | 05ee37eb | balrog | pfl->ro = 0;
|
630 | 05ee37eb | balrog | #endif
|
631 | 74475455 | Paolo Bonzini | pfl->timer = qemu_new_timer_ns(vm_clock, pflash_timer, pfl); |
632 | 05ee37eb | balrog | pfl->base = base; |
633 | 05ee37eb | balrog | pfl->sector_len = sector_len; |
634 | 05ee37eb | balrog | pfl->total_len = total_len; |
635 | 05ee37eb | balrog | pfl->width = width; |
636 | 05ee37eb | balrog | pfl->wcycle = 0;
|
637 | 05ee37eb | balrog | pfl->cmd = 0;
|
638 | 05ee37eb | balrog | pfl->status = 0;
|
639 | 05ee37eb | balrog | pfl->ident[0] = id0;
|
640 | 05ee37eb | balrog | pfl->ident[1] = id1;
|
641 | 05ee37eb | balrog | pfl->ident[2] = id2;
|
642 | 05ee37eb | balrog | pfl->ident[3] = id3;
|
643 | 05ee37eb | balrog | /* Hardcoded CFI table */
|
644 | 05ee37eb | balrog | pfl->cfi_len = 0x52;
|
645 | 05ee37eb | balrog | /* Standard "QRY" string */
|
646 | 05ee37eb | balrog | pfl->cfi_table[0x10] = 'Q'; |
647 | 05ee37eb | balrog | pfl->cfi_table[0x11] = 'R'; |
648 | 05ee37eb | balrog | pfl->cfi_table[0x12] = 'Y'; |
649 | 05ee37eb | balrog | /* Command set (Intel) */
|
650 | 05ee37eb | balrog | pfl->cfi_table[0x13] = 0x01; |
651 | 05ee37eb | balrog | pfl->cfi_table[0x14] = 0x00; |
652 | 05ee37eb | balrog | /* Primary extended table address (none) */
|
653 | 05ee37eb | balrog | pfl->cfi_table[0x15] = 0x31; |
654 | 05ee37eb | balrog | pfl->cfi_table[0x16] = 0x00; |
655 | 05ee37eb | balrog | /* Alternate command set (none) */
|
656 | 05ee37eb | balrog | pfl->cfi_table[0x17] = 0x00; |
657 | 05ee37eb | balrog | pfl->cfi_table[0x18] = 0x00; |
658 | 05ee37eb | balrog | /* Alternate extended table (none) */
|
659 | 05ee37eb | balrog | pfl->cfi_table[0x19] = 0x00; |
660 | 05ee37eb | balrog | pfl->cfi_table[0x1A] = 0x00; |
661 | 05ee37eb | balrog | /* Vcc min */
|
662 | 05ee37eb | balrog | pfl->cfi_table[0x1B] = 0x45; |
663 | 05ee37eb | balrog | /* Vcc max */
|
664 | 05ee37eb | balrog | pfl->cfi_table[0x1C] = 0x55; |
665 | 05ee37eb | balrog | /* Vpp min (no Vpp pin) */
|
666 | 05ee37eb | balrog | pfl->cfi_table[0x1D] = 0x00; |
667 | 05ee37eb | balrog | /* Vpp max (no Vpp pin) */
|
668 | 05ee37eb | balrog | pfl->cfi_table[0x1E] = 0x00; |
669 | 05ee37eb | balrog | /* Reserved */
|
670 | 05ee37eb | balrog | pfl->cfi_table[0x1F] = 0x07; |
671 | 05ee37eb | balrog | /* Timeout for min size buffer write */
|
672 | 05ee37eb | balrog | pfl->cfi_table[0x20] = 0x07; |
673 | 05ee37eb | balrog | /* Typical timeout for block erase */
|
674 | 05ee37eb | balrog | pfl->cfi_table[0x21] = 0x0a; |
675 | 05ee37eb | balrog | /* Typical timeout for full chip erase (4096 ms) */
|
676 | 05ee37eb | balrog | pfl->cfi_table[0x22] = 0x00; |
677 | 05ee37eb | balrog | /* Reserved */
|
678 | 05ee37eb | balrog | pfl->cfi_table[0x23] = 0x04; |
679 | 05ee37eb | balrog | /* Max timeout for buffer write */
|
680 | 05ee37eb | balrog | pfl->cfi_table[0x24] = 0x04; |
681 | 05ee37eb | balrog | /* Max timeout for block erase */
|
682 | 05ee37eb | balrog | pfl->cfi_table[0x25] = 0x04; |
683 | 05ee37eb | balrog | /* Max timeout for chip erase */
|
684 | 05ee37eb | balrog | pfl->cfi_table[0x26] = 0x00; |
685 | 05ee37eb | balrog | /* Device size */
|
686 | 05ee37eb | balrog | pfl->cfi_table[0x27] = ctz32(total_len); // + 1; |
687 | 05ee37eb | balrog | /* Flash device interface (8 & 16 bits) */
|
688 | 05ee37eb | balrog | pfl->cfi_table[0x28] = 0x02; |
689 | 05ee37eb | balrog | pfl->cfi_table[0x29] = 0x00; |
690 | 05ee37eb | balrog | /* Max number of bytes in multi-bytes write */
|
691 | 4737fa26 | Edgar E. Iglesias | if (width == 1) { |
692 | 4737fa26 | Edgar E. Iglesias | pfl->cfi_table[0x2A] = 0x08; |
693 | 4737fa26 | Edgar E. Iglesias | } else {
|
694 | 4737fa26 | Edgar E. Iglesias | pfl->cfi_table[0x2A] = 0x0B; |
695 | 4737fa26 | Edgar E. Iglesias | } |
696 | b4bf0a9a | Edgar E. Iglesias | pfl->writeblock_size = 1 << pfl->cfi_table[0x2A]; |
697 | b4bf0a9a | Edgar E. Iglesias | |
698 | 05ee37eb | balrog | pfl->cfi_table[0x2B] = 0x00; |
699 | 05ee37eb | balrog | /* Number of erase block regions (uniform) */
|
700 | 05ee37eb | balrog | pfl->cfi_table[0x2C] = 0x01; |
701 | 05ee37eb | balrog | /* Erase block region 1 */
|
702 | 05ee37eb | balrog | pfl->cfi_table[0x2D] = nb_blocs - 1; |
703 | 05ee37eb | balrog | pfl->cfi_table[0x2E] = (nb_blocs - 1) >> 8; |
704 | 05ee37eb | balrog | pfl->cfi_table[0x2F] = sector_len >> 8; |
705 | 05ee37eb | balrog | pfl->cfi_table[0x30] = sector_len >> 16; |
706 | 05ee37eb | balrog | |
707 | 05ee37eb | balrog | /* Extended */
|
708 | 05ee37eb | balrog | pfl->cfi_table[0x31] = 'P'; |
709 | 05ee37eb | balrog | pfl->cfi_table[0x32] = 'R'; |
710 | 05ee37eb | balrog | pfl->cfi_table[0x33] = 'I'; |
711 | 05ee37eb | balrog | |
712 | 05ee37eb | balrog | pfl->cfi_table[0x34] = '1'; |
713 | 05ee37eb | balrog | pfl->cfi_table[0x35] = '1'; |
714 | 05ee37eb | balrog | |
715 | 05ee37eb | balrog | pfl->cfi_table[0x36] = 0x00; |
716 | 05ee37eb | balrog | pfl->cfi_table[0x37] = 0x00; |
717 | 05ee37eb | balrog | pfl->cfi_table[0x38] = 0x00; |
718 | 05ee37eb | balrog | pfl->cfi_table[0x39] = 0x00; |
719 | 05ee37eb | balrog | |
720 | 05ee37eb | balrog | pfl->cfi_table[0x3a] = 0x00; |
721 | 05ee37eb | balrog | |
722 | 05ee37eb | balrog | pfl->cfi_table[0x3b] = 0x00; |
723 | 05ee37eb | balrog | pfl->cfi_table[0x3c] = 0x00; |
724 | 05ee37eb | balrog | |
725 | 05ee37eb | balrog | return pfl;
|
726 | 05ee37eb | balrog | } |