root / hw / r2d.c @ d47ede60
History | View | Annotate | Download (5.9 kB)
1 | 0d78f544 | ths | /*
|
---|---|---|---|
2 | 0d78f544 | ths | * Renesas SH7751R R2D-PLUS emulation
|
3 | 0d78f544 | ths | *
|
4 | 0d78f544 | ths | * Copyright (c) 2007 Magnus Damm
|
5 | b319feb7 | aurel32 | * Copyright (c) 2008 Paul Mundt
|
6 | 0d78f544 | ths | *
|
7 | 0d78f544 | ths | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
8 | 0d78f544 | ths | * of this software and associated documentation files (the "Software"), to deal
|
9 | 0d78f544 | ths | * in the Software without restriction, including without limitation the rights
|
10 | 0d78f544 | ths | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
11 | 0d78f544 | ths | * copies of the Software, and to permit persons to whom the Software is
|
12 | 0d78f544 | ths | * furnished to do so, subject to the following conditions:
|
13 | 0d78f544 | ths | *
|
14 | 0d78f544 | ths | * The above copyright notice and this permission notice shall be included in
|
15 | 0d78f544 | ths | * all copies or substantial portions of the Software.
|
16 | 0d78f544 | ths | *
|
17 | 0d78f544 | ths | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
18 | 0d78f544 | ths | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
19 | 0d78f544 | ths | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
20 | 0d78f544 | ths | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
21 | 0d78f544 | ths | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
22 | 0d78f544 | ths | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
23 | 0d78f544 | ths | * THE SOFTWARE.
|
24 | 0d78f544 | ths | */
|
25 | 0d78f544 | ths | |
26 | 87ecb68b | pbrook | #include "hw.h" |
27 | 87ecb68b | pbrook | #include "sh.h" |
28 | ffd39257 | blueswir1 | #include "devices.h" |
29 | 87ecb68b | pbrook | #include "sysemu.h" |
30 | 87ecb68b | pbrook | #include "boards.h" |
31 | 0d78f544 | ths | |
32 | 0d78f544 | ths | #define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */ |
33 | 0d78f544 | ths | #define SDRAM_SIZE 0x04000000 |
34 | 0d78f544 | ths | |
35 | ffd39257 | blueswir1 | #define SM501_VRAM_SIZE 0x800000 |
36 | ffd39257 | blueswir1 | |
37 | d47ede60 | balrog | #define PA_IRLMSK 0x00 |
38 | b319feb7 | aurel32 | #define PA_POWOFF 0x30 |
39 | b319feb7 | aurel32 | #define PA_VERREG 0x32 |
40 | b319feb7 | aurel32 | #define PA_OUTPORT 0x36 |
41 | b319feb7 | aurel32 | |
42 | b319feb7 | aurel32 | typedef struct { |
43 | b319feb7 | aurel32 | uint16_t bcr; |
44 | d47ede60 | balrog | uint16_t irlmsk; |
45 | b319feb7 | aurel32 | uint16_t irlmon; |
46 | b319feb7 | aurel32 | uint16_t cfctl; |
47 | b319feb7 | aurel32 | uint16_t cfpow; |
48 | b319feb7 | aurel32 | uint16_t dispctl; |
49 | b319feb7 | aurel32 | uint16_t sdmpow; |
50 | b319feb7 | aurel32 | uint16_t rtcce; |
51 | b319feb7 | aurel32 | uint16_t pcicd; |
52 | b319feb7 | aurel32 | uint16_t voyagerrts; |
53 | b319feb7 | aurel32 | uint16_t cfrst; |
54 | b319feb7 | aurel32 | uint16_t admrts; |
55 | b319feb7 | aurel32 | uint16_t extrst; |
56 | b319feb7 | aurel32 | uint16_t cfcdintclr; |
57 | b319feb7 | aurel32 | uint16_t keyctlclr; |
58 | b319feb7 | aurel32 | uint16_t pad0; |
59 | b319feb7 | aurel32 | uint16_t pad1; |
60 | b319feb7 | aurel32 | uint16_t powoff; |
61 | b319feb7 | aurel32 | uint16_t verreg; |
62 | b319feb7 | aurel32 | uint16_t inport; |
63 | b319feb7 | aurel32 | uint16_t outport; |
64 | b319feb7 | aurel32 | uint16_t bverreg; |
65 | d47ede60 | balrog | |
66 | d47ede60 | balrog | /* output pin */
|
67 | d47ede60 | balrog | qemu_irq irl; |
68 | b319feb7 | aurel32 | } r2d_fpga_t; |
69 | b319feb7 | aurel32 | |
70 | d47ede60 | balrog | enum r2d_fpga_irq {
|
71 | d47ede60 | balrog | PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T, |
72 | d47ede60 | balrog | SDCARD, PCI_INTA, PCI_INTB, EXT, TP, |
73 | d47ede60 | balrog | NR_IRQS |
74 | d47ede60 | balrog | }; |
75 | d47ede60 | balrog | |
76 | d47ede60 | balrog | static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = { |
77 | d47ede60 | balrog | [CF_IDE] = { 1, 1<<9 }, |
78 | d47ede60 | balrog | [CF_CD] = { 2, 1<<8 }, |
79 | d47ede60 | balrog | [PCI_INTA] = { 9, 1<<14 }, |
80 | d47ede60 | balrog | [PCI_INTB] = { 10, 1<<13 }, |
81 | d47ede60 | balrog | [PCI_INTC] = { 3, 1<<12 }, |
82 | d47ede60 | balrog | [PCI_INTD] = { 0, 1<<11 }, |
83 | d47ede60 | balrog | [SM501] = { 4, 1<<10 }, |
84 | d47ede60 | balrog | [KEY] = { 5, 1<<6 }, |
85 | d47ede60 | balrog | [RTC_A] = { 6, 1<<5 }, |
86 | d47ede60 | balrog | [RTC_T] = { 7, 1<<4 }, |
87 | d47ede60 | balrog | [SDCARD] = { 8, 1<<7 }, |
88 | d47ede60 | balrog | [EXT] = { 11, 1<<0 }, |
89 | d47ede60 | balrog | [TP] = { 12, 1<<15 }, |
90 | d47ede60 | balrog | }; |
91 | d47ede60 | balrog | |
92 | d47ede60 | balrog | static void update_irl(r2d_fpga_t *fpga) |
93 | d47ede60 | balrog | { |
94 | d47ede60 | balrog | int i, irl = 15; |
95 | d47ede60 | balrog | for (i = 0; i < NR_IRQS; i++) |
96 | d47ede60 | balrog | if (fpga->irlmon & fpga->irlmsk & irqtab[i].msk)
|
97 | d47ede60 | balrog | if (irqtab[i].irl < irl)
|
98 | d47ede60 | balrog | irl = irqtab[i].irl; |
99 | d47ede60 | balrog | qemu_set_irq(fpga->irl, irl ^ 15);
|
100 | d47ede60 | balrog | } |
101 | d47ede60 | balrog | |
102 | d47ede60 | balrog | static void r2d_fpga_irq_set(void *opaque, int n, int level) |
103 | d47ede60 | balrog | { |
104 | d47ede60 | balrog | r2d_fpga_t *fpga = opaque; |
105 | d47ede60 | balrog | if (level)
|
106 | d47ede60 | balrog | fpga->irlmon |= irqtab[n].msk; |
107 | d47ede60 | balrog | else
|
108 | d47ede60 | balrog | fpga->irlmon &= ~irqtab[n].msk; |
109 | d47ede60 | balrog | update_irl(fpga); |
110 | d47ede60 | balrog | } |
111 | d47ede60 | balrog | |
112 | b319feb7 | aurel32 | static uint32_t r2d_fpga_read(void *opaque, target_phys_addr_t addr) |
113 | b319feb7 | aurel32 | { |
114 | b319feb7 | aurel32 | r2d_fpga_t *s = opaque; |
115 | b319feb7 | aurel32 | |
116 | b319feb7 | aurel32 | switch (addr) {
|
117 | d47ede60 | balrog | case PA_IRLMSK:
|
118 | d47ede60 | balrog | return s->irlmsk;
|
119 | b319feb7 | aurel32 | case PA_OUTPORT:
|
120 | b319feb7 | aurel32 | return s->outport;
|
121 | b319feb7 | aurel32 | case PA_POWOFF:
|
122 | b319feb7 | aurel32 | return s->powoff;
|
123 | b319feb7 | aurel32 | case PA_VERREG:
|
124 | b319feb7 | aurel32 | return 0x10; |
125 | b319feb7 | aurel32 | } |
126 | b319feb7 | aurel32 | |
127 | b319feb7 | aurel32 | return 0; |
128 | b319feb7 | aurel32 | } |
129 | b319feb7 | aurel32 | |
130 | b319feb7 | aurel32 | static void |
131 | b319feb7 | aurel32 | r2d_fpga_write(void *opaque, target_phys_addr_t addr, uint32_t value)
|
132 | b319feb7 | aurel32 | { |
133 | b319feb7 | aurel32 | r2d_fpga_t *s = opaque; |
134 | b319feb7 | aurel32 | |
135 | b319feb7 | aurel32 | switch (addr) {
|
136 | d47ede60 | balrog | case PA_IRLMSK:
|
137 | d47ede60 | balrog | s->irlmsk = value; |
138 | d47ede60 | balrog | update_irl(s); |
139 | d47ede60 | balrog | break;
|
140 | b319feb7 | aurel32 | case PA_OUTPORT:
|
141 | b319feb7 | aurel32 | s->outport = value; |
142 | b319feb7 | aurel32 | break;
|
143 | b319feb7 | aurel32 | case PA_POWOFF:
|
144 | b319feb7 | aurel32 | s->powoff = value; |
145 | b319feb7 | aurel32 | break;
|
146 | b319feb7 | aurel32 | case PA_VERREG:
|
147 | b319feb7 | aurel32 | /* Discard writes */
|
148 | b319feb7 | aurel32 | break;
|
149 | b319feb7 | aurel32 | } |
150 | b319feb7 | aurel32 | } |
151 | b319feb7 | aurel32 | |
152 | b319feb7 | aurel32 | static CPUReadMemoryFunc *r2d_fpga_readfn[] = {
|
153 | b319feb7 | aurel32 | r2d_fpga_read, |
154 | b319feb7 | aurel32 | r2d_fpga_read, |
155 | b2463a64 | aurel32 | NULL,
|
156 | b319feb7 | aurel32 | }; |
157 | b319feb7 | aurel32 | |
158 | b319feb7 | aurel32 | static CPUWriteMemoryFunc *r2d_fpga_writefn[] = {
|
159 | b319feb7 | aurel32 | r2d_fpga_write, |
160 | b319feb7 | aurel32 | r2d_fpga_write, |
161 | b2463a64 | aurel32 | NULL,
|
162 | b319feb7 | aurel32 | }; |
163 | b319feb7 | aurel32 | |
164 | d47ede60 | balrog | static qemu_irq *r2d_fpga_init(target_phys_addr_t base, qemu_irq irl)
|
165 | b319feb7 | aurel32 | { |
166 | b319feb7 | aurel32 | int iomemtype;
|
167 | b319feb7 | aurel32 | r2d_fpga_t *s; |
168 | b319feb7 | aurel32 | |
169 | b319feb7 | aurel32 | s = qemu_mallocz(sizeof(r2d_fpga_t));
|
170 | b319feb7 | aurel32 | if (!s)
|
171 | d47ede60 | balrog | return NULL; |
172 | d47ede60 | balrog | |
173 | d47ede60 | balrog | s->irl = irl; |
174 | b319feb7 | aurel32 | |
175 | b319feb7 | aurel32 | iomemtype = cpu_register_io_memory(0, r2d_fpga_readfn,
|
176 | b319feb7 | aurel32 | r2d_fpga_writefn, s); |
177 | b319feb7 | aurel32 | cpu_register_physical_memory(base, 0x40, iomemtype);
|
178 | d47ede60 | balrog | return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
|
179 | b319feb7 | aurel32 | } |
180 | b319feb7 | aurel32 | |
181 | 00f82b8a | aurel32 | static void r2d_init(ram_addr_t ram_size, int vga_ram_size, |
182 | b881c2c6 | blueswir1 | const char *boot_device, DisplayState * ds, |
183 | 0d78f544 | ths | const char *kernel_filename, const char *kernel_cmdline, |
184 | 0d78f544 | ths | const char *initrd_filename, const char *cpu_model) |
185 | 0d78f544 | ths | { |
186 | 0d78f544 | ths | CPUState *env; |
187 | 0d78f544 | ths | struct SH7750State *s;
|
188 | ffd39257 | blueswir1 | ram_addr_t sdram_addr, sm501_vga_ram_addr; |
189 | d47ede60 | balrog | qemu_irq *irq; |
190 | 0d78f544 | ths | |
191 | aaed909a | bellard | if (!cpu_model)
|
192 | 0fd3ca30 | aurel32 | cpu_model = "SH7751R";
|
193 | aaed909a | bellard | |
194 | aaed909a | bellard | env = cpu_init(cpu_model); |
195 | aaed909a | bellard | if (!env) {
|
196 | aaed909a | bellard | fprintf(stderr, "Unable to find CPU definition\n");
|
197 | aaed909a | bellard | exit(1);
|
198 | aaed909a | bellard | } |
199 | 0d78f544 | ths | |
200 | 0d78f544 | ths | /* Allocate memory space */
|
201 | ffd39257 | blueswir1 | sdram_addr = qemu_ram_alloc(SDRAM_SIZE); |
202 | ffd39257 | blueswir1 | cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, sdram_addr); |
203 | 0d78f544 | ths | /* Register peripherals */
|
204 | 0d78f544 | ths | s = sh7750_init(env); |
205 | d47ede60 | balrog | irq = r2d_fpga_init(0x04000000, sh7750_irl(s));
|
206 | d47ede60 | balrog | |
207 | ffd39257 | blueswir1 | sm501_vga_ram_addr = qemu_ram_alloc(SM501_VRAM_SIZE); |
208 | ffd39257 | blueswir1 | sm501_init(ds, 0x10000000, sm501_vga_ram_addr, SM501_VRAM_SIZE,
|
209 | ffd39257 | blueswir1 | serial_hds[2]);
|
210 | a4a771c0 | balrog | |
211 | a4a771c0 | balrog | /* onboard CF (True IDE mode, Master only). */
|
212 | d47ede60 | balrog | mmio_ide_init(0x14001000, 0x1400080c, irq[CF_IDE], 1, |
213 | d47ede60 | balrog | drives_table[drive_get_index(IF_IDE, 0, 0)].bdrv, NULL); |
214 | a4a771c0 | balrog | |
215 | 0d78f544 | ths | /* Todo: register on board registers */
|
216 | 0d78f544 | ths | { |
217 | 0d78f544 | ths | int kernel_size;
|
218 | 0d78f544 | ths | |
219 | 0d78f544 | ths | kernel_size = load_image(kernel_filename, phys_ram_base); |
220 | 0d78f544 | ths | |
221 | 0d78f544 | ths | if (kernel_size < 0) { |
222 | 0d78f544 | ths | fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
|
223 | 0d78f544 | ths | exit(1);
|
224 | 0d78f544 | ths | } |
225 | 0d78f544 | ths | |
226 | 0d78f544 | ths | env->pc = SDRAM_BASE | 0xa0000000; /* Start from P2 area */ |
227 | 0d78f544 | ths | } |
228 | 0d78f544 | ths | } |
229 | 0d78f544 | ths | |
230 | 0d78f544 | ths | QEMUMachine r2d_machine = { |
231 | 4b32e168 | aliguori | .name = "r2d",
|
232 | 4b32e168 | aliguori | .desc = "r2d-plus board",
|
233 | 4b32e168 | aliguori | .init = r2d_init, |
234 | ffd39257 | blueswir1 | .ram_require = (SDRAM_SIZE + SM501_VRAM_SIZE) | RAMSIZE_FIXED, |
235 | 0d78f544 | ths | }; |