root / hw / r2d.c @ d47ede60
History | View | Annotate | Download (5.9 kB)
1 |
/*
|
---|---|
2 |
* Renesas SH7751R R2D-PLUS emulation
|
3 |
*
|
4 |
* Copyright (c) 2007 Magnus Damm
|
5 |
* Copyright (c) 2008 Paul Mundt
|
6 |
*
|
7 |
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
8 |
* of this software and associated documentation files (the "Software"), to deal
|
9 |
* in the Software without restriction, including without limitation the rights
|
10 |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
11 |
* copies of the Software, and to permit persons to whom the Software is
|
12 |
* furnished to do so, subject to the following conditions:
|
13 |
*
|
14 |
* The above copyright notice and this permission notice shall be included in
|
15 |
* all copies or substantial portions of the Software.
|
16 |
*
|
17 |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
18 |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
19 |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
20 |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
21 |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
22 |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
23 |
* THE SOFTWARE.
|
24 |
*/
|
25 |
|
26 |
#include "hw.h" |
27 |
#include "sh.h" |
28 |
#include "devices.h" |
29 |
#include "sysemu.h" |
30 |
#include "boards.h" |
31 |
|
32 |
#define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */ |
33 |
#define SDRAM_SIZE 0x04000000 |
34 |
|
35 |
#define SM501_VRAM_SIZE 0x800000 |
36 |
|
37 |
#define PA_IRLMSK 0x00 |
38 |
#define PA_POWOFF 0x30 |
39 |
#define PA_VERREG 0x32 |
40 |
#define PA_OUTPORT 0x36 |
41 |
|
42 |
typedef struct { |
43 |
uint16_t bcr; |
44 |
uint16_t irlmsk; |
45 |
uint16_t irlmon; |
46 |
uint16_t cfctl; |
47 |
uint16_t cfpow; |
48 |
uint16_t dispctl; |
49 |
uint16_t sdmpow; |
50 |
uint16_t rtcce; |
51 |
uint16_t pcicd; |
52 |
uint16_t voyagerrts; |
53 |
uint16_t cfrst; |
54 |
uint16_t admrts; |
55 |
uint16_t extrst; |
56 |
uint16_t cfcdintclr; |
57 |
uint16_t keyctlclr; |
58 |
uint16_t pad0; |
59 |
uint16_t pad1; |
60 |
uint16_t powoff; |
61 |
uint16_t verreg; |
62 |
uint16_t inport; |
63 |
uint16_t outport; |
64 |
uint16_t bverreg; |
65 |
|
66 |
/* output pin */
|
67 |
qemu_irq irl; |
68 |
} r2d_fpga_t; |
69 |
|
70 |
enum r2d_fpga_irq {
|
71 |
PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T, |
72 |
SDCARD, PCI_INTA, PCI_INTB, EXT, TP, |
73 |
NR_IRQS |
74 |
}; |
75 |
|
76 |
static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = { |
77 |
[CF_IDE] = { 1, 1<<9 }, |
78 |
[CF_CD] = { 2, 1<<8 }, |
79 |
[PCI_INTA] = { 9, 1<<14 }, |
80 |
[PCI_INTB] = { 10, 1<<13 }, |
81 |
[PCI_INTC] = { 3, 1<<12 }, |
82 |
[PCI_INTD] = { 0, 1<<11 }, |
83 |
[SM501] = { 4, 1<<10 }, |
84 |
[KEY] = { 5, 1<<6 }, |
85 |
[RTC_A] = { 6, 1<<5 }, |
86 |
[RTC_T] = { 7, 1<<4 }, |
87 |
[SDCARD] = { 8, 1<<7 }, |
88 |
[EXT] = { 11, 1<<0 }, |
89 |
[TP] = { 12, 1<<15 }, |
90 |
}; |
91 |
|
92 |
static void update_irl(r2d_fpga_t *fpga) |
93 |
{ |
94 |
int i, irl = 15; |
95 |
for (i = 0; i < NR_IRQS; i++) |
96 |
if (fpga->irlmon & fpga->irlmsk & irqtab[i].msk)
|
97 |
if (irqtab[i].irl < irl)
|
98 |
irl = irqtab[i].irl; |
99 |
qemu_set_irq(fpga->irl, irl ^ 15);
|
100 |
} |
101 |
|
102 |
static void r2d_fpga_irq_set(void *opaque, int n, int level) |
103 |
{ |
104 |
r2d_fpga_t *fpga = opaque; |
105 |
if (level)
|
106 |
fpga->irlmon |= irqtab[n].msk; |
107 |
else
|
108 |
fpga->irlmon &= ~irqtab[n].msk; |
109 |
update_irl(fpga); |
110 |
} |
111 |
|
112 |
static uint32_t r2d_fpga_read(void *opaque, target_phys_addr_t addr) |
113 |
{ |
114 |
r2d_fpga_t *s = opaque; |
115 |
|
116 |
switch (addr) {
|
117 |
case PA_IRLMSK:
|
118 |
return s->irlmsk;
|
119 |
case PA_OUTPORT:
|
120 |
return s->outport;
|
121 |
case PA_POWOFF:
|
122 |
return s->powoff;
|
123 |
case PA_VERREG:
|
124 |
return 0x10; |
125 |
} |
126 |
|
127 |
return 0; |
128 |
} |
129 |
|
130 |
static void |
131 |
r2d_fpga_write(void *opaque, target_phys_addr_t addr, uint32_t value)
|
132 |
{ |
133 |
r2d_fpga_t *s = opaque; |
134 |
|
135 |
switch (addr) {
|
136 |
case PA_IRLMSK:
|
137 |
s->irlmsk = value; |
138 |
update_irl(s); |
139 |
break;
|
140 |
case PA_OUTPORT:
|
141 |
s->outport = value; |
142 |
break;
|
143 |
case PA_POWOFF:
|
144 |
s->powoff = value; |
145 |
break;
|
146 |
case PA_VERREG:
|
147 |
/* Discard writes */
|
148 |
break;
|
149 |
} |
150 |
} |
151 |
|
152 |
static CPUReadMemoryFunc *r2d_fpga_readfn[] = {
|
153 |
r2d_fpga_read, |
154 |
r2d_fpga_read, |
155 |
NULL,
|
156 |
}; |
157 |
|
158 |
static CPUWriteMemoryFunc *r2d_fpga_writefn[] = {
|
159 |
r2d_fpga_write, |
160 |
r2d_fpga_write, |
161 |
NULL,
|
162 |
}; |
163 |
|
164 |
static qemu_irq *r2d_fpga_init(target_phys_addr_t base, qemu_irq irl)
|
165 |
{ |
166 |
int iomemtype;
|
167 |
r2d_fpga_t *s; |
168 |
|
169 |
s = qemu_mallocz(sizeof(r2d_fpga_t));
|
170 |
if (!s)
|
171 |
return NULL; |
172 |
|
173 |
s->irl = irl; |
174 |
|
175 |
iomemtype = cpu_register_io_memory(0, r2d_fpga_readfn,
|
176 |
r2d_fpga_writefn, s); |
177 |
cpu_register_physical_memory(base, 0x40, iomemtype);
|
178 |
return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
|
179 |
} |
180 |
|
181 |
static void r2d_init(ram_addr_t ram_size, int vga_ram_size, |
182 |
const char *boot_device, DisplayState * ds, |
183 |
const char *kernel_filename, const char *kernel_cmdline, |
184 |
const char *initrd_filename, const char *cpu_model) |
185 |
{ |
186 |
CPUState *env; |
187 |
struct SH7750State *s;
|
188 |
ram_addr_t sdram_addr, sm501_vga_ram_addr; |
189 |
qemu_irq *irq; |
190 |
|
191 |
if (!cpu_model)
|
192 |
cpu_model = "SH7751R";
|
193 |
|
194 |
env = cpu_init(cpu_model); |
195 |
if (!env) {
|
196 |
fprintf(stderr, "Unable to find CPU definition\n");
|
197 |
exit(1);
|
198 |
} |
199 |
|
200 |
/* Allocate memory space */
|
201 |
sdram_addr = qemu_ram_alloc(SDRAM_SIZE); |
202 |
cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, sdram_addr); |
203 |
/* Register peripherals */
|
204 |
s = sh7750_init(env); |
205 |
irq = r2d_fpga_init(0x04000000, sh7750_irl(s));
|
206 |
|
207 |
sm501_vga_ram_addr = qemu_ram_alloc(SM501_VRAM_SIZE); |
208 |
sm501_init(ds, 0x10000000, sm501_vga_ram_addr, SM501_VRAM_SIZE,
|
209 |
serial_hds[2]);
|
210 |
|
211 |
/* onboard CF (True IDE mode, Master only). */
|
212 |
mmio_ide_init(0x14001000, 0x1400080c, irq[CF_IDE], 1, |
213 |
drives_table[drive_get_index(IF_IDE, 0, 0)].bdrv, NULL); |
214 |
|
215 |
/* Todo: register on board registers */
|
216 |
{ |
217 |
int kernel_size;
|
218 |
|
219 |
kernel_size = load_image(kernel_filename, phys_ram_base); |
220 |
|
221 |
if (kernel_size < 0) { |
222 |
fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
|
223 |
exit(1);
|
224 |
} |
225 |
|
226 |
env->pc = SDRAM_BASE | 0xa0000000; /* Start from P2 area */ |
227 |
} |
228 |
} |
229 |
|
230 |
QEMUMachine r2d_machine = { |
231 |
.name = "r2d",
|
232 |
.desc = "r2d-plus board",
|
233 |
.init = r2d_init, |
234 |
.ram_require = (SDRAM_SIZE + SM501_VRAM_SIZE) | RAMSIZE_FIXED, |
235 |
}; |