target-arm: Allow special cpregs to have flags set
Relax the "is this a valid ARMCPRegInfo type value?" check to permit"special" cpregs to have flags other than ARM_CP_SPECIAL set. Atthe moment none of the other flags are relevant for special regs,but the migration related flag we're about to introduce can apply...
target-arm: Add raw_readfn and raw_writefn to ARMCPRegInfo
For reading and writing register values from the kernel for KVM,we need to provide accessor functions which are guaranteed to succeedand don't impose access checks, mask out unwritable bits, etc....
target-arm: mark up cpregs for no-migrate or raw access
Mark up coprocessor register definitions to add raw accessfunctions or mark the register as non-migratable where necessary.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Merge remote-tracking branch 'mjt/trivial-patches-next' into staging
Merge remote-tracking branch 'pmaydell/target-arm.next' into staging
Message-id: 1370268884-25945-1-git-send-email-peter.maydell@linaro.orgSigned-off-by: Anthony Liguori <aliguori@us.ibm.com>
KVM: ARM: Add dummy kvm_arch_init_irq_routing()
The common KVM code insists on calling kvm_arch_init_irq_routing()as soon as it sees kernel header support for it (regardless of whetherQEMU supports it). Provide a dummy function to satisfy this.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>...
Fix rfe instruction
The rfe instruction has been broken since patch5a839c0d54fac9db0516904db873a4fe01f50f4b because of a typo.
Signed-off-by: Peter Chubb <peter.chubb@nicta.com.au>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Remove unnecessary break statements
Fix these warnings from cppcheck:
hw/display/cirrus_vga.c:2603:hw/sd/sd.c:348:hw/timer/exynos4210_mct.c:1033:target-arm/translate.c:9886:target-s390x/mem_helper.c:518:target-unicore32/translate.c:1936: style: Consecutive return, break, continue, goto or throw statements are unnecessary....
target-arm: Remove gen_{ld,st}* definitions
All the uses of the gen_{ld,st}* functions are gone now, so removethe functions themselves.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-arm: Remove uses of gen_{ld,st}* from Neon code
target-arm: Remove use of gen_{ld,st}* from ldrex/strex
target-arm: Remove gen_{ld,st}* from basic ARM insns
target-arm: Remove gen_{ld,st}* from Thumb insns
target-arm: Remove gen_{ld,st}* from thumb2 decoder
target-arm: Remove uses of gen_{ld,st}* from iWMMXt code
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-arm: Remove gen_ld64() and gen_st64()
gen_ld64() and gen_st64() are used only in one place, so justexpand them out.
target-arm: Don't use TCGv when we mean TCGv_i32
TCGv changes size depending on the compile time value ofTARGET_LONG_BITS. This is useful for generating code for MIPS style"instructions are the same but the register width changes" CPUs, andalso for the generic bits of QEMU which operate on "width of a...
target-arm: Fix incorrect check of kvm_vcpu_ioctl return value
kvm_vcpu_ioctl() returns ETHING on error, not ETHING - correctan incorrect check in kvm_arch_init_vcpu(). This would not havehad any significant ill-effects -- we would just have propagated...
target-arm: port ARM CPU save/load to use VMState
Port the ARM CPU save/load code to use VMState. Some state issaved in a slightly different order to simplify things -- forexample arrays are saved one after the other rather than 'striped',and we always save all 32 VFP registers even if the CPU happens...
target-arm: Add some missing CPU state fields to VMState
A number of CPU state fields were accidentally omitted fromour migration state: some OMAP specific cp15 registers, andsome related to state for load/store exclusive insns. Add them.
target-arm: Correctly restore FPSCR
Use the helper functions to save and restore the FPSCR, so thatwe correctly propagate rounding mode and flushing behaviour intothe float_status fields. This also allows us to stop saving thevector length/stride fields separately....
target-arm: Reinsert missing return statement in ARM mode SRS decode
Since patch 81465888c5306cd94abb9847e560796fd13d3c2f target-arm: factor out handling of SRS instructionthe ARM mode SRS instruction has not worked in QEMU.
The problem is a missing return directive that was removed in the...
arm: fix location of some include files
The recent rearrangement of include files had some minor errors: devices.h is not ARM specific and should not be in arm/ arm.h should be in arm/
Move these two headers to correct this.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
hw: move headers to include/
Many of these should be cleaned up with proper qdev-/QOM-ification.Right now there are many catch-all headers in include/hw/ARCH dependingon cpu.h, and this makes it necessary to compile these files per-target.However, fixing this does not belong in these patches....
cpu: Move halted and interrupt_request fields to CPUState
Both fields are used in VMState, thus need to be moved together.Explicitly zero them on reset since they were located beforebreakpoints.
Pass PowerPCCPU to kvmppc_handle_halt().
Signed-off-by: Andreas Färber <afaerber@suse.de>
cpu: Pass CPUState to cpu_interrupt()
Move it to qom/cpu.h to avoid issues with include order.
Change pc_acpi_smi_interrupt() opaque to X86CPU.
cpu: Replace do_interrupt() by CPUClass::do_interrupt method
This removes a global per-target function and thus takes us one stepcloser to compiling multiple targets into one executable.
It will also allow to override the interrupt handling for certain CPU...
target-arm: Override do_interrupt for ARMv7-M profile
Enable ARMCPUInfo to specify a custom class_init functions.Introduce arm_v7m_class_init() and use it for "cortex-m3" model.
Instead of forwarding from arm_cpu_do_interrupt() to do_interrupt_v7m(),override CPUClass::do_interrupt with arm_v7m_cpu_do_interrupt()...
target-arm: Use MemoryListener to identify GIC base address for KVM
When using an in-kernel GIC with KVM, we need to tell the kernel wherethe GIC's memory mapped registers live. Do this by registering aMemoryListener which tracks where the board model maps the A15's...
ARM KVM: save and load VFP registers from kernel
Add support for saving and restoring VFP register state from thekernel. This includes a check that the KVM-created CPU has fullVFP support (as the TCG Cortex-A15 model always does), since forthe moment ARM QEMU doesn't have any way to tweak optional features...
ARM: KVM: Add support for KVM on ARM architecture
Add basic support for KVM on ARM architecture.
Signed-off-by: Christoffer Dall <cdall@cs.columbia.edu>[PMM: Minor tweaks and code cleanup, switch to ONE_REG]Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: Drop CPUARMState* argument from bank_number()
Drop the CPUARMState* argument from bank_number(), since we onlyuse it for passing to cpu_abort(). Use hw_error() instead.This avoids propagating further interfaces using env pointers.
In the long term this function's callers need auditing to fix...
target-arm: Factor out handling of SRS instruction
Factor out the handling of the SRS instruction rather thanduplicating it between the Thumb and ARM decoders. This inpassing fixes two bugs in the Thumb decoder's SRS handlingwhich didn't exist in the ARM decoder:...
target-arm: Don't decode RFE or SRS on M profile cores
M profile cores do not have the RFE or SRS instructions, socorrectly UNDEF these insn patterns on those cores.
gen-icount.h: Rename gen_icount_start/end to gen_tb_start/end
The gen_icount_start/end functions are now somewhat misnamed since theyare useful for generic "start/end of TB" code, used for more than justicount. Rename them to gen_tb_start/end.
cpu: Introduce ENV_OFFSET macros
Introduce ENV_OFFSET macros which can be used in non-target-specificcode that needs to generate TCG instructions which reference CPUStatefields given the cpu_env register that TCG targets set up with apointer to the CPUArchState struct....
arm/translate.c: Fix adc_CC/sbc_CC implementation
commits 49b4c31efcce45ab714f286f14fa5d5173f9069d and2de68a4900ef6eb67380b0c128abfe1976bc66e8 reworked the implementation of adc_CCand sub_CC. The new implementations (on the TCG_TARGET_HAS_add2_i32 code path)...
target-arm: Fix sbc_CC carry
While T0+~T1+CF = T0-T1+CF-1 is true for the low 32-bits,it does not produce the correct carry-out to bit 33. Doexactly what the manual says.
Using the ~T1 makes the add and subtract code paths nearlyidentical, so have sbc_CC use adc_CC....
target-arm: Use mul[us]2 in gen_mul[us]_i64_i32
Cc: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-arm: Use mul[us]2 and add2 in umlal et al
target-arm: Use add2 in gen_add_CC
target-arm: Implement adc_cc inline
Use add2 if available, otherwise use 64-bit arithmetic.
target-arm: Implement sbc_cc inline
Use sub2 if available, otherwise use 64-bit arithmetic.
cpu: Add CPUArchState pointer to CPUState
The target-specific ENV_GET_CPU() macros have allowed us to navigatefrom CPUArchState to CPUState. The reverse direction was not supported.Avoid introducing CPU_GET_ENV() macros by initializing an untypedpointer that is initialized in derived instance_init functions....
target-arm: Move TCG initialization to ARMCPU initfn
Ensures that a QOM-created ARMCPU is usable.
target-arm: Update ARMCPU to QOM realizefn
Turn arm_cpu_realize() into a QOM realize function, no longer calledvia cpu.h prototype. To maintain the semantics of cpu_init(), setrealized = true explicitly in cpu_arm_init().
Move GDB coprocessor registration, CPU reset and vCPU initialization...
target-arm: Rename CPU types
In the initial conversion of CPU models to QOM types, model names weremapped 1:1 to type names. As a side effect this gained us a type "any",which is now a device.
To avoid "-device any" silliness and to pave the way for compiling...
target-arm: Fix TCG temp leaks for WI and UNDEF VFP sysreg writes
Fix a leak of a TCG temporary in code paths for VFP system registerwrites for cases which UNDEF or are write-ignored.
target-arm: Catch attempt to instantiate abstract type in cpu_init()
This fixes -cpu arm-cpu asserting.
Cc: qemu-stable@nongnu.orgAcked-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Andreas Färber <afaerber@suse.de>
target-arm: Detect attempt to instantiate non-CPU type in cpu_init()
Consolidate model checking into a new arm_cpu_class_by_name().
If the name matches an existing type, also check whether that type isactually (a sub-type of) TYPE_ARM_CPU.
This fixes, e.g., -cpu tmp105 asserting....
cpu: Move cpu_index field to CPUState
Note that target-alpha accesses this field from TCG, now using anegative offset. Therefore the field is placed last in CPUState.
Pass PowerPCCPU to [kvm]ppc_fixup_cpu() to facilitate this change.
Move common parts of mips cpu_state_reset() to mips_cpu_reset()....
target-arm: use type_register() instead of type_register_static()
The type_register_static() interface is documented as:
type_register_static: @info: The #TypeInfo of the new type.
@info and all of the strings it points to should exist for the life...
target-arm: Fix SWI (SVC) instruction in M profile.
When do_interrupt_v7m is called with EXCP_SWI, the PC alreadypoints to the next instruction. Don't modify it here.
Signed-off-by: Alex Rozenman <Alex_Rozenman@mentor.com>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Merge branch 'master' of git://git.qemu.org/qemu into qom-cpu
Adapt header include paths.
cpu: Introduce CPUListState struct
This generalizes {ARM,M68k,Alpha}CPUListState to avoid declaring it foreach target. Place it in cpu-common.h to avoid circular dependencies.
Signed-off-by: Andreas Färber <afaerber@suse.de>Reviewed-by: Igor Mammedov <imammedo@redhat.com>...
fpu: move public header file to include/fpu
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
softmmu: move include files to include/sysemu/
misc: move include files to include/qemu/
qom: move include files to include/qom/
exec: move include files to include/exec/
build: kill libdis, move disassemblers to disas/
exec: refactor cpu_restore_state
Refactor common code around calls to cpu_restore_state().
tb_find_pc() has now no external users, make it static.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
TCG: Use gen_opc_instr_start from context instead of global variable.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
TCG: Use gen_opc_pc from context instead of global variable.
TCG: Use gen_opc_icount from context instead of global variable.
TCG: Use gen_opc_buf from context instead of global variable.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
TCG: Use gen_opc_ptr from context instead of global variable.
disas: avoid using cpu_single_env
Pass around CPUArchState instead of using global cpu_single_env.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Acked-by: Richard Henderson <rth@twiddle.net>Acked-by: Aurelien Jarno <aurelien@aurel32.net>Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
cpus: Pass CPUState to [qemu_]cpu_has_work()
For target-mips also change the return type to bool.
Make include paths for cpu-qom.h consistent for alpha and unicore32.
Signed-off-by: Andreas Färber <afaerber@suse.de>[AF: Updated new target-openrisc function accordingly]...
target-arm: rename helper flags
Rename helper flags to the new ones. This is purely a mechanical change,it's possible to use better flags by looking at the helpers.
Cc: Paul Brook <paul@codesourcery.com>Cc: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Richard Henderson <rth@twiddle.net>...
arm-semi.c: Handle get/put_user() failure accessing arguments
Rework the handling of arguments to ARM semihosting calls so that wehandle a possible failure return from get_user_ual() or put_user_ual().(This incidentally silences a lot of warnings from clang about...
target-arm: Use TCG operation for Neon 64 bit negation
Use the TCG operation to do Neon 64 bit negations rather than callinga helper routine for it.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Implement abs_i32 inline rather than as a helper
Implement abs_i32 inline (with movcond) rather than using a helperfunction.
target-arm: Remove out of date FIXME regarding saturating arithmetic
Remove an out of date FIXME regarding the saturating arithmetic helpers:we now do pass a pointer to CPUARMState to these helpers, and sincethe AREG0 changes went in there is no difference between helper.c...
Rename target_phys_addr_t to hwaddr
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes arereserved) and its purpose doesn't match the name (most target_phys_addr_taddresses are not target specific). Replace it with a finger-friendly,...
target-arm/neon_helper: Remove obsolete FIXME comment
Commit 33ebc29 fixed the bugs in the implementation of VQRSHL,but forgot to remove the FIXME comment...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
target-arm/translate: Fix RRX operands
Instructions that both use the RRX second operand and update CS wereincorrect, as the Carry flag was updated too early. An example of such aninstruction would be:
ands r12,r13,RRX
Ands, because of the "s" flag will update the carry flag. But the RRX second...
target-arm: mark a few integer helpers const and pure
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: use deposit instead of hardcoded version
Use the deposit op instead of and hardcoded bit field insertion. Itallows the host to emit the corresponding instruction if available.
target-arm: Drop unused DECODE_CPREG_CRN macro
This macro snuck through code review despite being unused; drop it.
target-arm: Reinstate display of VFP registers in cpu_dump_state
Reinstate the display of VFP registers in cpu_dump_state(), ifthe CPU has them (this code had been #if 0'd out a for a long time).We drop the attempt ot display the values as floating point, since...
target-arm: use globals for CC flags
Use globals for CC flags instead of loading/storing them each they areaccessed. This allows some optimizations to be performed by the TCGoptimization passes.
target-arm: convert add_cc and sub_cc helpers to TCG
Now that the setcond TCG op is available, it's possible to replaceadd_cc and sub_cc helpers by TCG code. The code generated by TCG isactually very close to the one generated by GCC for the helper, and...
target-arm: convert sar, shl and shr helpers to TCG
Now that the movcond TCG op is available, it's possible to replaceshl and shr helpers by TCG code. The code generated by TCG is slightlylonger than the code generated by GCC for the helper but is still worth...
Emit debug_insn for CPU_LOG_TB_OP_OPT as well.
For all targets that currently call tcg_gen_debug_insn_start,add CPU_LOG_TB_OP_OPT to the condition that gates it.
This is useful for comparing optimization dumps, when thepre-optimization dump is merely noise....
target-arm: convert void helpers
Add an explicit CPUState parameter instead of relying on AREG0.
For easier review, convert only op helpers which don't return any value.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: convert remaining helpers
Convert remaining helpers to AREG0 free mode: add an explicitCPUState parameter instead of relying on AREG0.
target-arm: final conversion to AREG0 free mode
Convert code load functions and switch to AREG0 free mode.
target-arm: Fix potential buffer overflow
Report from smatch:
target-arm/helper.c:651 arm946_prbs_read(6) error: buffer overflow 'env->cp15.c6_region' 8 <= 8target-arm/helper.c:661 arm946_prbs_write(6) error: buffer overflow 'env->cp15.c6_region' 8 <= 8...
arm-semi: don't leak 1KB user string lock buffer upon TARGET_SYS_OPEN
Always call unlock_user before returning.
Signed-off-by: Jim Meyering <meyering@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
target-arm: Fix typos in comments
Fix a variety of typos in comments in target-arm files.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Peter Crosthwaite <peter.crosthwaite@petalogix.com>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
arm: translate: comment typo - s/middel/middle/
Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>Reviewed-by: Andreas Färber <afaerber@suse.de>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
target-arm: Extend feature flags to 64 bits
Extend feature flags to 64 bits, as we've just run out of spacein the 32 bit integer we were using for them.
target-arm: Add AMAIR0, AMAIR1 LPAE cp15 registers
Add implementations of the AMAIR0 and AMAIR1 LPAEAuxiliary Memory Attribute Indirection Registers.These are implementation defined and we choose toimplement them as RAZ/WI, matching the Cortex-A7and Cortex-A15....
target-arm: Add 64 bit variants of DBGDRAR and DBGDSAR for LPAE
LPAE extends the DBGDRAR and DBGDSAR debug registers to 64 bits; weonly implement these as dummy RAZ versions; provide dummies forthe 64 bit accesses as well.
target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAE
Under LPAE, the cp15 registers PAR, TTBR0 and TTBR1 are extendedto 64 bits, with a 64 bit (MRRC/MCRR) access path to read thefull width of the register. Add the state fields for the tophalf and the 64 bit access path. Actual use of the top half of...
target-arm: Use target_phys_addr_t in get_phys_addr()
In the implementation of get_phys_addr(), consistently usetarget_phys_addr_t to hold the physical address rather thanuint32_t.
target-arm: Implement long-descriptor PAR format
Implement the different format of the PAR when long descriptortranslation tables are in use. Note that we assume thatget_phys_addr() returns a long-descriptor format DFSR value onfailure if long descriptors are in use; this added subtlety tips...
target-arm: Implement TTBCR changes for LPAE
Implement the changes to the TTBCR register required for LPAE: * many fewer bits should be RAZ/WI * since TTBCR changes can result in a change of ASID, we must flush the TLB on writes to it
target-arm: Add support for long format translation table walks
Implement the actual table walk code for LPAE's long formattranslation tables.