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target-sparc: Add compiler attribute to some functions which don't return
helper_raise_exception does not return, nor does do_unaligned_access.
Cc: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Stefan Weil <sw@weilnetz.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Sparc: avoid AREG0 for memory access helpers
Make memory access helpers take a parameter for CPUState insteadof relying on global env. Introduce wrappers for load and store ops.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Improve "ta 0" shutdown
This patch replace the previous implementation with this simplified andmore complete version (no shutdown when psret == 1).
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-sparc: Implement ALIGNADDR* inline.
While ALIGNADDR was implemented out-of-line, ALIGNADDRL was notimplemeneted at all. However, this is a very simple operationso we're better off doing this inline.
Signed-off-by: Richard Henderson <rth@twiddle.net>
target-sparc: Implement BMASK/BSHUFFLE.
target-sparc: Implement FALIGNDATA inline.
This is a relatively simple sequence of shifts.
target-sparc: Implement fpack{16,32,fix}.
target-sparc: Implement PDIST.
target-sparc: Do exceptions management fully inside the helpers.
This reduces the size of the individual translation blocks, sincewe only emit a single call for each FOP rather than three. Inaddition, clear_float_exceptions expands inline to a single byte store....
target-sparc: Pass float64 parameters instead of dt0/1 temporaries.
target-sparc: Make FPU/VIS helpers const when possible.
This also removes the unused ENV parameter from these helpers.
Sparc: avoid AREG0 for division op helpers
Make [su]div{,cc} helpers take a parameter for CPUState insteadof relying on global env. Move the functions to helper.c.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Sparc: avoid AREG0 for softint op helpers and Leon cache control
Make softint op helpers and Leon cache irq manager take a parameterfor CPUState instead of relying on global env. Move the functionsto int{32,64}_helper.c.
Reviewed-by: Richard Henderson <rth@twiddle.net>...
Sparc: avoid AREG0 for CWP and PSTATE helpers
Make CWP and PSTATE helpers take a parameter for CPUState insteadof relying on global env. Remove wrapper functions.
Sparc: avoid AREG0 for lazy condition code helpers
Make lazy condition code helpers take a parameter for CPUState insteadof relying on global env.
Sparc: avoid AREG0 for float and VIS ops
Make floating point and VIS ops take a parameter for CPUState insteadof relying on global env.
Sparc: avoid AREG0 for raise_exception and helper_debug
Make raise_exception() and helper_debug() take a parameter forCPUState instead of relying on global env. Move the functionsto helper.c.
SPARC64: fix VIS1 SIMD signed compare instructions
The destination registers of SIMD signed compare instructions(fcmp*<16|32>) are not FP registers but general purpose r registers.Comparisons should be freg_rs1 CMP freg_rs2, that were reversed.
Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>...
Delete unused tb_invalidate_page_range
tb_invalidate_page_range() was intended to be used to invalidate anarea of a TB which the guest explicitly flushes from i-cache. However,QEMU detects writes to code areas where TBs have been generated, sohis has never been useful....
SPARC: Emulation of Leon3
Leon3 is an open-source VHDL System-On-Chip, well known in space industry (moreinformation on http://www.gaisler.com).
Leon3 is made of multiple components available in the GrLib VHDL library.Three devices are implemented: uart, timers and IRQ manager....
target-sparc: fix udiv(cc) and sdiv(cc)
Since commit 5a4bb580cdb10b066f9fd67658b31cac4a4ea5e5, Xorg crashes ona Debian Etch image. The commit itself is fine, but it triggers a bugdue to wrong computation of flags for udiv(cc) and sdiv(cc).
This patch only compute cc_src2 for the cc version of udiv/sdiv. It...
target-sparc: Inline some generation of carry for ADDX/SUBX.
Computing carry is trivial for some inputs. By avoiding anexternal function call, we generate near-optimal code forthe common cases of add+addx (double-word arithmetic) andcmp+addx (a setcc pattern)....
target-sparc: Fix compilation with --enable-debug.
Return a target_ulong from compute_C_icc to match the width of the users.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
sparc64: use helper_wrpil to check pending irq on write
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Use dynamical computation for condition codes
TCG variable type checking.
Signed-off-by: Paul Brook <paul@codesourcery.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
Implement UA2005 hypervisor traps
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5327 c046a42c-6fe2-441c-8c8c-71466251a162
Add software and timer interrupt support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5299 c046a42c-6fe2-441c-8c8c-71466251a162
Use the new concat_i32_i64 op for std and stda
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5281 c046a42c-6fe2-441c-8c8c-71466251a162
Convert rest of ops using float32 to TCG, remove FT0 and FT1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5193 c046a42c-6fe2-441c-8c8c-71466251a162
Partially convert float128 conversion ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5192 c046a42c-6fe2-441c-8c8c-71466251a162
Convert basic 64 bit VIS ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5191 c046a42c-6fe2-441c-8c8c-71466251a162
Convert basic 32 bit VIS ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5190 c046a42c-6fe2-441c-8c8c-71466251a162
Convert basic float32 ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5189 c046a42c-6fe2-441c-8c8c-71466251a162
Implement ldxfsr/stxfsr, fix ld(x)fsr masks, convert to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5185 c046a42c-6fe2-441c-8c8c-71466251a162
Fix Sparc64 boot on i386 host: - move do_interrupt() back to op_helper.c - move non-helper prototypes from helper.h to exec.h - move some prototypes from cpu.h to exec.h - do not export either set_cwp() or cpu_set_cwp() from op_helper.c, but instead provide inline functions...
Implement nucleus quad ldda
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4902 c046a42c-6fe2-441c-8c8c-71466251a162
Move non-op functions from op_helper.c to helper.c and vice versa.Rearrange interrupt handling to match other targets.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4590 c046a42c-6fe2-441c-8c8c-71466251a162
Register op helpers
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4534 c046a42c-6fe2-441c-8c8c-71466251a162
Move prototype back to avoid a compiler warning
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4443 c046a42c-6fe2-441c-8c8c-71466251a162
Fix compiler warnings
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4404 c046a42c-6fe2-441c-8c8c-71466251a162
CPU feature selection support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4399 c046a42c-6fe2-441c-8c8c-71466251a162
Complete the TCG conversion
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4323 c046a42c-6fe2-441c-8c8c-71466251a162
Convert align checks to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4097 c046a42c-6fe2-441c-8c8c-71466251a162
Convert save, restore, saved, restored, and flushw to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4092 c046a42c-6fe2-441c-8c8c-71466251a162
Convert other float and VIS ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4091 c046a42c-6fe2-441c-8c8c-71466251a162
Convert udiv and sdiv ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4088 c046a42c-6fe2-441c-8c8c-71466251a162
Convert CCR and CWP ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4086 c046a42c-6fe2-441c-8c8c-71466251a162
Convert array8/16/32 and alignaddr to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4085 c046a42c-6fe2-441c-8c8c-71466251a162
Convert ldfsr and stfsr to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4067 c046a42c-6fe2-441c-8c8c-71466251a162
Convert exception ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4022 c046a42c-6fe2-441c-8c8c-71466251a162
Convert float helpers to TCG, fix fabsq in the process
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4014 c046a42c-6fe2-441c-8c8c-71466251a162
Convert tick operations to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4011 c046a42c-6fe2-441c-8c8c-71466251a162
Modify Sparc32/64 to use TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3989 c046a42c-6fe2-441c-8c8c-71466251a162