root / hw / sh7750.c @ d8c6d07f
History | View | Annotate | Download (23 kB)
1 | 27c7ca7e | bellard | /*
|
---|---|---|---|
2 | 27c7ca7e | bellard | * SH7750 device
|
3 | 5fafdf24 | ths | *
|
4 | 80f515e6 | balrog | * Copyright (c) 2007 Magnus Damm
|
5 | 27c7ca7e | bellard | * Copyright (c) 2005 Samuel Tardieu
|
6 | 5fafdf24 | ths | *
|
7 | 27c7ca7e | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
8 | 27c7ca7e | bellard | * of this software and associated documentation files (the "Software"), to deal
|
9 | 27c7ca7e | bellard | * in the Software without restriction, including without limitation the rights
|
10 | 27c7ca7e | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
11 | 27c7ca7e | bellard | * copies of the Software, and to permit persons to whom the Software is
|
12 | 27c7ca7e | bellard | * furnished to do so, subject to the following conditions:
|
13 | 27c7ca7e | bellard | *
|
14 | 27c7ca7e | bellard | * The above copyright notice and this permission notice shall be included in
|
15 | 27c7ca7e | bellard | * all copies or substantial portions of the Software.
|
16 | 27c7ca7e | bellard | *
|
17 | 27c7ca7e | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
18 | 27c7ca7e | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
19 | 27c7ca7e | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
20 | 27c7ca7e | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
21 | 27c7ca7e | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
22 | 27c7ca7e | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
23 | 27c7ca7e | bellard | * THE SOFTWARE.
|
24 | 27c7ca7e | bellard | */
|
25 | 27c7ca7e | bellard | #include <stdio.h> |
26 | 87ecb68b | pbrook | #include "hw.h" |
27 | 87ecb68b | pbrook | #include "sh.h" |
28 | 9c17d615 | Paolo Bonzini | #include "sysemu/sysemu.h" |
29 | 27c7ca7e | bellard | #include "sh7750_regs.h" |
30 | 27c7ca7e | bellard | #include "sh7750_regnames.h" |
31 | 80f515e6 | balrog | #include "sh_intc.h" |
32 | 29e179bc | aurel32 | #include "cpu.h" |
33 | 022c62cb | Paolo Bonzini | #include "exec/address-spaces.h" |
34 | 27c7ca7e | bellard | |
35 | 27c7ca7e | bellard | #define NB_DEVICES 4 |
36 | 27c7ca7e | bellard | |
37 | 27c7ca7e | bellard | typedef struct SH7750State { |
38 | 382863e2 | Benoît Canet | MemoryRegion iomem; |
39 | 382863e2 | Benoît Canet | MemoryRegion iomem_1f0; |
40 | 382863e2 | Benoît Canet | MemoryRegion iomem_ff0; |
41 | 382863e2 | Benoît Canet | MemoryRegion iomem_1f8; |
42 | 382863e2 | Benoît Canet | MemoryRegion iomem_ff8; |
43 | 382863e2 | Benoît Canet | MemoryRegion iomem_1fc; |
44 | 382863e2 | Benoît Canet | MemoryRegion iomem_ffc; |
45 | 1a4004c7 | Benoît Canet | MemoryRegion mmct_iomem; |
46 | 27c7ca7e | bellard | /* CPU */
|
47 | 27c7ca7e | bellard | CPUSH4State *cpu; |
48 | 27c7ca7e | bellard | /* Peripheral frequency in Hz */
|
49 | 27c7ca7e | bellard | uint32_t periph_freq; |
50 | 27c7ca7e | bellard | /* SDRAM controller */
|
51 | c2f01775 | balrog | uint32_t bcr1; |
52 | c2432a42 | aurel32 | uint16_t bcr2; |
53 | c2432a42 | aurel32 | uint16_t bcr3; |
54 | c2432a42 | aurel32 | uint32_t bcr4; |
55 | 27c7ca7e | bellard | uint16_t rfcr; |
56 | c2432a42 | aurel32 | /* PCMCIA controller */
|
57 | c2432a42 | aurel32 | uint16_t pcr; |
58 | 27c7ca7e | bellard | /* IO ports */
|
59 | 27c7ca7e | bellard | uint16_t gpioic; |
60 | 27c7ca7e | bellard | uint32_t pctra; |
61 | 27c7ca7e | bellard | uint32_t pctrb; |
62 | 27c7ca7e | bellard | uint16_t portdira; /* Cached */
|
63 | 27c7ca7e | bellard | uint16_t portpullupa; /* Cached */
|
64 | 27c7ca7e | bellard | uint16_t portdirb; /* Cached */
|
65 | 27c7ca7e | bellard | uint16_t portpullupb; /* Cached */
|
66 | 27c7ca7e | bellard | uint16_t pdtra; |
67 | 27c7ca7e | bellard | uint16_t pdtrb; |
68 | 27c7ca7e | bellard | uint16_t periph_pdtra; /* Imposed by the peripherals */
|
69 | 27c7ca7e | bellard | uint16_t periph_portdira; /* Direction seen from the peripherals */
|
70 | 27c7ca7e | bellard | uint16_t periph_pdtrb; /* Imposed by the peripherals */
|
71 | 27c7ca7e | bellard | uint16_t periph_portdirb; /* Direction seen from the peripherals */
|
72 | 27c7ca7e | bellard | sh7750_io_device *devices[NB_DEVICES]; /* External peripherals */
|
73 | 3464c589 | ths | |
74 | 27c7ca7e | bellard | /* Cache */
|
75 | 27c7ca7e | bellard | uint32_t ccr; |
76 | 27c7ca7e | bellard | |
77 | 80f515e6 | balrog | struct intc_desc intc;
|
78 | cd1a3f68 | ths | } SH7750State; |
79 | 27c7ca7e | bellard | |
80 | 86178a57 | Juan Quintela | static inline int has_bcr3_and_bcr4(SH7750State * s) |
81 | c2432a42 | aurel32 | { |
82 | c2432a42 | aurel32 | return (s->cpu->features & SH_FEATURE_BCR3_AND_BCR4);
|
83 | c2432a42 | aurel32 | } |
84 | 27c7ca7e | bellard | /**********************************************************************
|
85 | 27c7ca7e | bellard | I/O ports
|
86 | 27c7ca7e | bellard | **********************************************************************/
|
87 | 27c7ca7e | bellard | |
88 | 27c7ca7e | bellard | int sh7750_register_io_device(SH7750State * s, sh7750_io_device * device)
|
89 | 27c7ca7e | bellard | { |
90 | 27c7ca7e | bellard | int i;
|
91 | 27c7ca7e | bellard | |
92 | 27c7ca7e | bellard | for (i = 0; i < NB_DEVICES; i++) { |
93 | 27c7ca7e | bellard | if (s->devices[i] == NULL) { |
94 | 27c7ca7e | bellard | s->devices[i] = device; |
95 | 27c7ca7e | bellard | return 0; |
96 | 27c7ca7e | bellard | } |
97 | 27c7ca7e | bellard | } |
98 | 27c7ca7e | bellard | return -1; |
99 | 27c7ca7e | bellard | } |
100 | 27c7ca7e | bellard | |
101 | 27c7ca7e | bellard | static uint16_t portdir(uint32_t v)
|
102 | 27c7ca7e | bellard | { |
103 | 27c7ca7e | bellard | #define EVENPORTMASK(n) ((v & (1<<((n)<<1))) >> (n)) |
104 | 27c7ca7e | bellard | return
|
105 | 27c7ca7e | bellard | EVENPORTMASK(15) | EVENPORTMASK(14) | EVENPORTMASK(13) | |
106 | 27c7ca7e | bellard | EVENPORTMASK(12) | EVENPORTMASK(11) | EVENPORTMASK(10) | |
107 | 27c7ca7e | bellard | EVENPORTMASK(9) | EVENPORTMASK(8) | EVENPORTMASK(7) | |
108 | 27c7ca7e | bellard | EVENPORTMASK(6) | EVENPORTMASK(5) | EVENPORTMASK(4) | |
109 | 27c7ca7e | bellard | EVENPORTMASK(3) | EVENPORTMASK(2) | EVENPORTMASK(1) | |
110 | 27c7ca7e | bellard | EVENPORTMASK(0);
|
111 | 27c7ca7e | bellard | } |
112 | 27c7ca7e | bellard | |
113 | 27c7ca7e | bellard | static uint16_t portpullup(uint32_t v)
|
114 | 27c7ca7e | bellard | { |
115 | 27c7ca7e | bellard | #define ODDPORTMASK(n) ((v & (1<<(((n)<<1)+1))) >> (n)) |
116 | 27c7ca7e | bellard | return
|
117 | 27c7ca7e | bellard | ODDPORTMASK(15) | ODDPORTMASK(14) | ODDPORTMASK(13) | |
118 | 27c7ca7e | bellard | ODDPORTMASK(12) | ODDPORTMASK(11) | ODDPORTMASK(10) | |
119 | 27c7ca7e | bellard | ODDPORTMASK(9) | ODDPORTMASK(8) | ODDPORTMASK(7) | ODDPORTMASK(6) | |
120 | 27c7ca7e | bellard | ODDPORTMASK(5) | ODDPORTMASK(4) | ODDPORTMASK(3) | ODDPORTMASK(2) | |
121 | 27c7ca7e | bellard | ODDPORTMASK(1) | ODDPORTMASK(0); |
122 | 27c7ca7e | bellard | } |
123 | 27c7ca7e | bellard | |
124 | 27c7ca7e | bellard | static uint16_t porta_lines(SH7750State * s)
|
125 | 27c7ca7e | bellard | { |
126 | 27c7ca7e | bellard | return (s->portdira & s->pdtra) | /* CPU */ |
127 | 27c7ca7e | bellard | (s->periph_portdira & s->periph_pdtra) | /* Peripherals */
|
128 | 27c7ca7e | bellard | (~(s->portdira | s->periph_portdira) & s->portpullupa); /* Pullups */
|
129 | 27c7ca7e | bellard | } |
130 | 27c7ca7e | bellard | |
131 | 27c7ca7e | bellard | static uint16_t portb_lines(SH7750State * s)
|
132 | 27c7ca7e | bellard | { |
133 | 27c7ca7e | bellard | return (s->portdirb & s->pdtrb) | /* CPU */ |
134 | 27c7ca7e | bellard | (s->periph_portdirb & s->periph_pdtrb) | /* Peripherals */
|
135 | 27c7ca7e | bellard | (~(s->portdirb | s->periph_portdirb) & s->portpullupb); /* Pullups */
|
136 | 27c7ca7e | bellard | } |
137 | 27c7ca7e | bellard | |
138 | 27c7ca7e | bellard | static void gen_port_interrupts(SH7750State * s) |
139 | 27c7ca7e | bellard | { |
140 | 27c7ca7e | bellard | /* XXXXX interrupts not generated */
|
141 | 27c7ca7e | bellard | } |
142 | 27c7ca7e | bellard | |
143 | 27c7ca7e | bellard | static void porta_changed(SH7750State * s, uint16_t prev) |
144 | 27c7ca7e | bellard | { |
145 | 27c7ca7e | bellard | uint16_t currenta, changes; |
146 | 27c7ca7e | bellard | int i, r = 0; |
147 | 27c7ca7e | bellard | |
148 | 27c7ca7e | bellard | #if 0
|
149 | 27c7ca7e | bellard | fprintf(stderr, "porta changed from 0x%04x to 0x%04x\n",
|
150 | 27c7ca7e | bellard | prev, porta_lines(s));
|
151 | 27c7ca7e | bellard | fprintf(stderr, "pdtra=0x%04x, pctra=0x%08x\n", s->pdtra, s->pctra);
|
152 | 27c7ca7e | bellard | #endif
|
153 | 27c7ca7e | bellard | currenta = porta_lines(s); |
154 | 27c7ca7e | bellard | if (currenta == prev)
|
155 | 27c7ca7e | bellard | return;
|
156 | 27c7ca7e | bellard | changes = currenta ^ prev; |
157 | 27c7ca7e | bellard | |
158 | 27c7ca7e | bellard | for (i = 0; i < NB_DEVICES; i++) { |
159 | 27c7ca7e | bellard | if (s->devices[i] && (s->devices[i]->portamask_trigger & changes)) {
|
160 | 27c7ca7e | bellard | r |= s->devices[i]->port_change_cb(currenta, portb_lines(s), |
161 | 27c7ca7e | bellard | &s->periph_pdtra, |
162 | 27c7ca7e | bellard | &s->periph_portdira, |
163 | 27c7ca7e | bellard | &s->periph_pdtrb, |
164 | 27c7ca7e | bellard | &s->periph_portdirb); |
165 | 27c7ca7e | bellard | } |
166 | 27c7ca7e | bellard | } |
167 | 27c7ca7e | bellard | |
168 | 27c7ca7e | bellard | if (r)
|
169 | 27c7ca7e | bellard | gen_port_interrupts(s); |
170 | 27c7ca7e | bellard | } |
171 | 27c7ca7e | bellard | |
172 | 27c7ca7e | bellard | static void portb_changed(SH7750State * s, uint16_t prev) |
173 | 27c7ca7e | bellard | { |
174 | 27c7ca7e | bellard | uint16_t currentb, changes; |
175 | 27c7ca7e | bellard | int i, r = 0; |
176 | 27c7ca7e | bellard | |
177 | 27c7ca7e | bellard | currentb = portb_lines(s); |
178 | 27c7ca7e | bellard | if (currentb == prev)
|
179 | 27c7ca7e | bellard | return;
|
180 | 27c7ca7e | bellard | changes = currentb ^ prev; |
181 | 27c7ca7e | bellard | |
182 | 27c7ca7e | bellard | for (i = 0; i < NB_DEVICES; i++) { |
183 | 27c7ca7e | bellard | if (s->devices[i] && (s->devices[i]->portbmask_trigger & changes)) {
|
184 | 27c7ca7e | bellard | r |= s->devices[i]->port_change_cb(portb_lines(s), currentb, |
185 | 27c7ca7e | bellard | &s->periph_pdtra, |
186 | 27c7ca7e | bellard | &s->periph_portdira, |
187 | 27c7ca7e | bellard | &s->periph_pdtrb, |
188 | 27c7ca7e | bellard | &s->periph_portdirb); |
189 | 27c7ca7e | bellard | } |
190 | 27c7ca7e | bellard | } |
191 | 27c7ca7e | bellard | |
192 | 27c7ca7e | bellard | if (r)
|
193 | 27c7ca7e | bellard | gen_port_interrupts(s); |
194 | 27c7ca7e | bellard | } |
195 | 27c7ca7e | bellard | |
196 | 27c7ca7e | bellard | /**********************************************************************
|
197 | 27c7ca7e | bellard | Memory
|
198 | 27c7ca7e | bellard | **********************************************************************/
|
199 | 27c7ca7e | bellard | |
200 | a8170e5e | Avi Kivity | static void error_access(const char *kind, hwaddr addr) |
201 | 27c7ca7e | bellard | { |
202 | 526ccb7a | balrog | fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") not supported\n", |
203 | 27c7ca7e | bellard | kind, regname(addr), addr); |
204 | 27c7ca7e | bellard | } |
205 | 27c7ca7e | bellard | |
206 | a8170e5e | Avi Kivity | static void ignore_access(const char *kind, hwaddr addr) |
207 | 27c7ca7e | bellard | { |
208 | 526ccb7a | balrog | fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") ignored\n", |
209 | 27c7ca7e | bellard | kind, regname(addr), addr); |
210 | 27c7ca7e | bellard | } |
211 | 27c7ca7e | bellard | |
212 | a8170e5e | Avi Kivity | static uint32_t sh7750_mem_readb(void *opaque, hwaddr addr) |
213 | 27c7ca7e | bellard | { |
214 | 27c7ca7e | bellard | switch (addr) {
|
215 | 27c7ca7e | bellard | default:
|
216 | 27c7ca7e | bellard | error_access("byte read", addr);
|
217 | 43dc2a64 | Blue Swirl | abort(); |
218 | 27c7ca7e | bellard | } |
219 | 27c7ca7e | bellard | } |
220 | 27c7ca7e | bellard | |
221 | a8170e5e | Avi Kivity | static uint32_t sh7750_mem_readw(void *opaque, hwaddr addr) |
222 | 27c7ca7e | bellard | { |
223 | 27c7ca7e | bellard | SH7750State *s = opaque; |
224 | 27c7ca7e | bellard | |
225 | 27c7ca7e | bellard | switch (addr) {
|
226 | c2f01775 | balrog | case SH7750_BCR2_A7:
|
227 | c2f01775 | balrog | return s->bcr2;
|
228 | c2432a42 | aurel32 | case SH7750_BCR3_A7:
|
229 | c2432a42 | aurel32 | if(!has_bcr3_and_bcr4(s))
|
230 | c2432a42 | aurel32 | error_access("word read", addr);
|
231 | c2432a42 | aurel32 | return s->bcr3;
|
232 | ed8e0a4d | ths | case SH7750_FRQCR_A7:
|
233 | ed8e0a4d | ths | return 0; |
234 | c2432a42 | aurel32 | case SH7750_PCR_A7:
|
235 | c2432a42 | aurel32 | return s->pcr;
|
236 | 27c7ca7e | bellard | case SH7750_RFCR_A7:
|
237 | 27c7ca7e | bellard | fprintf(stderr, |
238 | 27c7ca7e | bellard | "Read access to refresh count register, incrementing\n");
|
239 | 27c7ca7e | bellard | return s->rfcr++;
|
240 | 27c7ca7e | bellard | case SH7750_PDTRA_A7:
|
241 | 27c7ca7e | bellard | return porta_lines(s);
|
242 | 27c7ca7e | bellard | case SH7750_PDTRB_A7:
|
243 | 27c7ca7e | bellard | return portb_lines(s);
|
244 | c2432a42 | aurel32 | case SH7750_RTCOR_A7:
|
245 | c2432a42 | aurel32 | case SH7750_RTCNT_A7:
|
246 | c2432a42 | aurel32 | case SH7750_RTCSR_A7:
|
247 | c2432a42 | aurel32 | ignore_access("word read", addr);
|
248 | c2432a42 | aurel32 | return 0; |
249 | 27c7ca7e | bellard | default:
|
250 | 27c7ca7e | bellard | error_access("word read", addr);
|
251 | 43dc2a64 | Blue Swirl | abort(); |
252 | 27c7ca7e | bellard | } |
253 | 27c7ca7e | bellard | } |
254 | 27c7ca7e | bellard | |
255 | a8170e5e | Avi Kivity | static uint32_t sh7750_mem_readl(void *opaque, hwaddr addr) |
256 | 27c7ca7e | bellard | { |
257 | 27c7ca7e | bellard | SH7750State *s = opaque; |
258 | 27c7ca7e | bellard | |
259 | 27c7ca7e | bellard | switch (addr) {
|
260 | c2f01775 | balrog | case SH7750_BCR1_A7:
|
261 | c2f01775 | balrog | return s->bcr1;
|
262 | c2f01775 | balrog | case SH7750_BCR4_A7:
|
263 | c2432a42 | aurel32 | if(!has_bcr3_and_bcr4(s))
|
264 | c2432a42 | aurel32 | error_access("long read", addr);
|
265 | c2432a42 | aurel32 | return s->bcr4;
|
266 | c2f01775 | balrog | case SH7750_WCR1_A7:
|
267 | c2f01775 | balrog | case SH7750_WCR2_A7:
|
268 | c2f01775 | balrog | case SH7750_WCR3_A7:
|
269 | c2f01775 | balrog | case SH7750_MCR_A7:
|
270 | c2f01775 | balrog | ignore_access("long read", addr);
|
271 | c2f01775 | balrog | return 0; |
272 | 27c7ca7e | bellard | case SH7750_MMUCR_A7:
|
273 | 27c7ca7e | bellard | return s->cpu->mmucr;
|
274 | 27c7ca7e | bellard | case SH7750_PTEH_A7:
|
275 | 27c7ca7e | bellard | return s->cpu->pteh;
|
276 | 27c7ca7e | bellard | case SH7750_PTEL_A7:
|
277 | 27c7ca7e | bellard | return s->cpu->ptel;
|
278 | 27c7ca7e | bellard | case SH7750_TTB_A7:
|
279 | 27c7ca7e | bellard | return s->cpu->ttb;
|
280 | 27c7ca7e | bellard | case SH7750_TEA_A7:
|
281 | 27c7ca7e | bellard | return s->cpu->tea;
|
282 | 27c7ca7e | bellard | case SH7750_TRA_A7:
|
283 | 27c7ca7e | bellard | return s->cpu->tra;
|
284 | 27c7ca7e | bellard | case SH7750_EXPEVT_A7:
|
285 | 27c7ca7e | bellard | return s->cpu->expevt;
|
286 | 27c7ca7e | bellard | case SH7750_INTEVT_A7:
|
287 | 27c7ca7e | bellard | return s->cpu->intevt;
|
288 | 27c7ca7e | bellard | case SH7750_CCR_A7:
|
289 | 27c7ca7e | bellard | return s->ccr;
|
290 | 0fd3ca30 | aurel32 | case 0x1f000030: /* Processor version */ |
291 | 0fd3ca30 | aurel32 | return s->cpu->pvr;
|
292 | 0fd3ca30 | aurel32 | case 0x1f000040: /* Cache version */ |
293 | 0fd3ca30 | aurel32 | return s->cpu->cvr;
|
294 | 0fd3ca30 | aurel32 | case 0x1f000044: /* Processor revision */ |
295 | 0fd3ca30 | aurel32 | return s->cpu->prr;
|
296 | 27c7ca7e | bellard | default:
|
297 | 27c7ca7e | bellard | error_access("long read", addr);
|
298 | 43dc2a64 | Blue Swirl | abort(); |
299 | 27c7ca7e | bellard | } |
300 | 27c7ca7e | bellard | } |
301 | 27c7ca7e | bellard | |
302 | c2432a42 | aurel32 | #define is_in_sdrmx(a, x) (a >= SH7750_SDMR ## x ## _A7 \ |
303 | c2432a42 | aurel32 | && a <= (SH7750_SDMR ## x ## _A7 + SH7750_SDMR ## x ## _REGNB)) |
304 | a8170e5e | Avi Kivity | static void sh7750_mem_writeb(void *opaque, hwaddr addr, |
305 | 27c7ca7e | bellard | uint32_t mem_value) |
306 | 27c7ca7e | bellard | { |
307 | c2432a42 | aurel32 | |
308 | c2432a42 | aurel32 | if (is_in_sdrmx(addr, 2) || is_in_sdrmx(addr, 3)) { |
309 | 27c7ca7e | bellard | ignore_access("byte write", addr);
|
310 | 27c7ca7e | bellard | return;
|
311 | 27c7ca7e | bellard | } |
312 | c2432a42 | aurel32 | |
313 | c2432a42 | aurel32 | error_access("byte write", addr);
|
314 | 43dc2a64 | Blue Swirl | abort(); |
315 | 27c7ca7e | bellard | } |
316 | 27c7ca7e | bellard | |
317 | a8170e5e | Avi Kivity | static void sh7750_mem_writew(void *opaque, hwaddr addr, |
318 | 27c7ca7e | bellard | uint32_t mem_value) |
319 | 27c7ca7e | bellard | { |
320 | 27c7ca7e | bellard | SH7750State *s = opaque; |
321 | 27c7ca7e | bellard | uint16_t temp; |
322 | 27c7ca7e | bellard | |
323 | 27c7ca7e | bellard | switch (addr) {
|
324 | 27c7ca7e | bellard | /* SDRAM controller */
|
325 | 27c7ca7e | bellard | case SH7750_BCR2_A7:
|
326 | c2f01775 | balrog | s->bcr2 = mem_value; |
327 | c2f01775 | balrog | return;
|
328 | 27c7ca7e | bellard | case SH7750_BCR3_A7:
|
329 | c2432a42 | aurel32 | if(!has_bcr3_and_bcr4(s))
|
330 | c2432a42 | aurel32 | error_access("word write", addr);
|
331 | c2432a42 | aurel32 | s->bcr3 = mem_value; |
332 | c2432a42 | aurel32 | return;
|
333 | c2432a42 | aurel32 | case SH7750_PCR_A7:
|
334 | c2432a42 | aurel32 | s->pcr = mem_value; |
335 | c2432a42 | aurel32 | return;
|
336 | 27c7ca7e | bellard | case SH7750_RTCNT_A7:
|
337 | c2432a42 | aurel32 | case SH7750_RTCOR_A7:
|
338 | 27c7ca7e | bellard | case SH7750_RTCSR_A7:
|
339 | 27c7ca7e | bellard | ignore_access("word write", addr);
|
340 | 27c7ca7e | bellard | return;
|
341 | 27c7ca7e | bellard | /* IO ports */
|
342 | 27c7ca7e | bellard | case SH7750_PDTRA_A7:
|
343 | 27c7ca7e | bellard | temp = porta_lines(s); |
344 | 27c7ca7e | bellard | s->pdtra = mem_value; |
345 | 27c7ca7e | bellard | porta_changed(s, temp); |
346 | 27c7ca7e | bellard | return;
|
347 | 27c7ca7e | bellard | case SH7750_PDTRB_A7:
|
348 | 27c7ca7e | bellard | temp = portb_lines(s); |
349 | 27c7ca7e | bellard | s->pdtrb = mem_value; |
350 | 27c7ca7e | bellard | portb_changed(s, temp); |
351 | 27c7ca7e | bellard | return;
|
352 | 27c7ca7e | bellard | case SH7750_RFCR_A7:
|
353 | 27c7ca7e | bellard | fprintf(stderr, "Write access to refresh count register\n");
|
354 | 27c7ca7e | bellard | s->rfcr = mem_value; |
355 | 27c7ca7e | bellard | return;
|
356 | 27c7ca7e | bellard | case SH7750_GPIOIC_A7:
|
357 | 27c7ca7e | bellard | s->gpioic = mem_value; |
358 | 27c7ca7e | bellard | if (mem_value != 0) { |
359 | 27c7ca7e | bellard | fprintf(stderr, "I/O interrupts not implemented\n");
|
360 | 43dc2a64 | Blue Swirl | abort(); |
361 | 27c7ca7e | bellard | } |
362 | 27c7ca7e | bellard | return;
|
363 | 27c7ca7e | bellard | default:
|
364 | 27c7ca7e | bellard | error_access("word write", addr);
|
365 | 43dc2a64 | Blue Swirl | abort(); |
366 | 27c7ca7e | bellard | } |
367 | 27c7ca7e | bellard | } |
368 | 27c7ca7e | bellard | |
369 | a8170e5e | Avi Kivity | static void sh7750_mem_writel(void *opaque, hwaddr addr, |
370 | 27c7ca7e | bellard | uint32_t mem_value) |
371 | 27c7ca7e | bellard | { |
372 | 27c7ca7e | bellard | SH7750State *s = opaque; |
373 | 27c7ca7e | bellard | uint16_t temp; |
374 | 27c7ca7e | bellard | |
375 | 27c7ca7e | bellard | switch (addr) {
|
376 | 27c7ca7e | bellard | /* SDRAM controller */
|
377 | 27c7ca7e | bellard | case SH7750_BCR1_A7:
|
378 | c2f01775 | balrog | s->bcr1 = mem_value; |
379 | c2f01775 | balrog | return;
|
380 | 27c7ca7e | bellard | case SH7750_BCR4_A7:
|
381 | c2432a42 | aurel32 | if(!has_bcr3_and_bcr4(s))
|
382 | c2432a42 | aurel32 | error_access("long write", addr);
|
383 | c2432a42 | aurel32 | s->bcr4 = mem_value; |
384 | c2432a42 | aurel32 | return;
|
385 | 27c7ca7e | bellard | case SH7750_WCR1_A7:
|
386 | 27c7ca7e | bellard | case SH7750_WCR2_A7:
|
387 | 27c7ca7e | bellard | case SH7750_WCR3_A7:
|
388 | 27c7ca7e | bellard | case SH7750_MCR_A7:
|
389 | 27c7ca7e | bellard | ignore_access("long write", addr);
|
390 | 27c7ca7e | bellard | return;
|
391 | 27c7ca7e | bellard | /* IO ports */
|
392 | 27c7ca7e | bellard | case SH7750_PCTRA_A7:
|
393 | 27c7ca7e | bellard | temp = porta_lines(s); |
394 | 27c7ca7e | bellard | s->pctra = mem_value; |
395 | 27c7ca7e | bellard | s->portdira = portdir(mem_value); |
396 | 27c7ca7e | bellard | s->portpullupa = portpullup(mem_value); |
397 | 27c7ca7e | bellard | porta_changed(s, temp); |
398 | 27c7ca7e | bellard | return;
|
399 | 27c7ca7e | bellard | case SH7750_PCTRB_A7:
|
400 | 27c7ca7e | bellard | temp = portb_lines(s); |
401 | 27c7ca7e | bellard | s->pctrb = mem_value; |
402 | 27c7ca7e | bellard | s->portdirb = portdir(mem_value); |
403 | 27c7ca7e | bellard | s->portpullupb = portpullup(mem_value); |
404 | 27c7ca7e | bellard | portb_changed(s, temp); |
405 | 27c7ca7e | bellard | return;
|
406 | 27c7ca7e | bellard | case SH7750_MMUCR_A7:
|
407 | e0bcb9ca | Aurelien Jarno | if (mem_value & MMUCR_TI) {
|
408 | e0bcb9ca | Aurelien Jarno | cpu_sh4_invalidate_tlb(s->cpu); |
409 | e0bcb9ca | Aurelien Jarno | } |
410 | e0bcb9ca | Aurelien Jarno | s->cpu->mmucr = mem_value & ~MMUCR_TI; |
411 | e0bcb9ca | Aurelien Jarno | return;
|
412 | 27c7ca7e | bellard | case SH7750_PTEH_A7:
|
413 | 06afe2c8 | aurel32 | /* If asid changes, clear all registered tlb entries. */
|
414 | 06afe2c8 | aurel32 | if ((s->cpu->pteh & 0xff) != (mem_value & 0xff)) |
415 | 06afe2c8 | aurel32 | tlb_flush(s->cpu, 1);
|
416 | 27c7ca7e | bellard | s->cpu->pteh = mem_value; |
417 | 27c7ca7e | bellard | return;
|
418 | 27c7ca7e | bellard | case SH7750_PTEL_A7:
|
419 | 27c7ca7e | bellard | s->cpu->ptel = mem_value; |
420 | 27c7ca7e | bellard | return;
|
421 | ea2b542a | aurel32 | case SH7750_PTEA_A7:
|
422 | ea2b542a | aurel32 | s->cpu->ptea = mem_value & 0x0000000f;
|
423 | ea2b542a | aurel32 | return;
|
424 | 27c7ca7e | bellard | case SH7750_TTB_A7:
|
425 | 27c7ca7e | bellard | s->cpu->ttb = mem_value; |
426 | 27c7ca7e | bellard | return;
|
427 | 27c7ca7e | bellard | case SH7750_TEA_A7:
|
428 | 27c7ca7e | bellard | s->cpu->tea = mem_value; |
429 | 27c7ca7e | bellard | return;
|
430 | 27c7ca7e | bellard | case SH7750_TRA_A7:
|
431 | 27c7ca7e | bellard | s->cpu->tra = mem_value & 0x000007ff;
|
432 | 27c7ca7e | bellard | return;
|
433 | 27c7ca7e | bellard | case SH7750_EXPEVT_A7:
|
434 | 27c7ca7e | bellard | s->cpu->expevt = mem_value & 0x000007ff;
|
435 | 27c7ca7e | bellard | return;
|
436 | 27c7ca7e | bellard | case SH7750_INTEVT_A7:
|
437 | 27c7ca7e | bellard | s->cpu->intevt = mem_value & 0x000007ff;
|
438 | 27c7ca7e | bellard | return;
|
439 | 27c7ca7e | bellard | case SH7750_CCR_A7:
|
440 | 27c7ca7e | bellard | s->ccr = mem_value; |
441 | 27c7ca7e | bellard | return;
|
442 | 27c7ca7e | bellard | default:
|
443 | 27c7ca7e | bellard | error_access("long write", addr);
|
444 | 43dc2a64 | Blue Swirl | abort(); |
445 | 27c7ca7e | bellard | } |
446 | 27c7ca7e | bellard | } |
447 | 27c7ca7e | bellard | |
448 | 382863e2 | Benoît Canet | static const MemoryRegionOps sh7750_mem_ops = { |
449 | 382863e2 | Benoît Canet | .old_mmio = { |
450 | 382863e2 | Benoît Canet | .read = {sh7750_mem_readb, |
451 | 382863e2 | Benoît Canet | sh7750_mem_readw, |
452 | 382863e2 | Benoît Canet | sh7750_mem_readl }, |
453 | 382863e2 | Benoît Canet | .write = {sh7750_mem_writeb, |
454 | 382863e2 | Benoît Canet | sh7750_mem_writew, |
455 | 382863e2 | Benoît Canet | sh7750_mem_writel }, |
456 | 382863e2 | Benoît Canet | }, |
457 | 382863e2 | Benoît Canet | .endianness = DEVICE_NATIVE_ENDIAN, |
458 | 27c7ca7e | bellard | }; |
459 | 27c7ca7e | bellard | |
460 | 80f515e6 | balrog | /* sh775x interrupt controller tables for sh_intc.c
|
461 | 80f515e6 | balrog | * stolen from linux/arch/sh/kernel/cpu/sh4/setup-sh7750.c
|
462 | 80f515e6 | balrog | */
|
463 | 80f515e6 | balrog | |
464 | 80f515e6 | balrog | enum {
|
465 | 80f515e6 | balrog | UNUSED = 0,
|
466 | 80f515e6 | balrog | |
467 | 80f515e6 | balrog | /* interrupt sources */
|
468 | c6d86a33 | balrog | IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6, IRL_7, |
469 | c6d86a33 | balrog | IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E, |
470 | c6d86a33 | balrog | IRL0, IRL1, IRL2, IRL3, |
471 | 80f515e6 | balrog | HUDI, GPIOI, |
472 | 80f515e6 | balrog | DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3, |
473 | 80f515e6 | balrog | DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7, |
474 | 80f515e6 | balrog | DMAC_DMAE, |
475 | 80f515e6 | balrog | PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, |
476 | 80f515e6 | balrog | PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3, |
477 | 80f515e6 | balrog | TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI, |
478 | 80f515e6 | balrog | RTC_ATI, RTC_PRI, RTC_CUI, |
479 | 80f515e6 | balrog | SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI, |
480 | 80f515e6 | balrog | SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI, |
481 | 80f515e6 | balrog | WDT, |
482 | 80f515e6 | balrog | REF_RCMI, REF_ROVI, |
483 | 80f515e6 | balrog | |
484 | 80f515e6 | balrog | /* interrupt groups */
|
485 | 80f515e6 | balrog | DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF, |
486 | c6d86a33 | balrog | /* irl bundle */
|
487 | c6d86a33 | balrog | IRL, |
488 | 80f515e6 | balrog | |
489 | 80f515e6 | balrog | NR_SOURCES, |
490 | 80f515e6 | balrog | }; |
491 | 80f515e6 | balrog | |
492 | 80f515e6 | balrog | static struct intc_vect vectors[] = { |
493 | 80f515e6 | balrog | INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), |
494 | 80f515e6 | balrog | INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), |
495 | 80f515e6 | balrog | INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460), |
496 | 80f515e6 | balrog | INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), |
497 | 80f515e6 | balrog | INTC_VECT(RTC_CUI, 0x4c0),
|
498 | 80f515e6 | balrog | INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500), |
499 | 80f515e6 | balrog | INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540), |
500 | 80f515e6 | balrog | INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720), |
501 | 80f515e6 | balrog | INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760), |
502 | 80f515e6 | balrog | INTC_VECT(WDT, 0x560),
|
503 | 80f515e6 | balrog | INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0), |
504 | 80f515e6 | balrog | }; |
505 | 80f515e6 | balrog | |
506 | 80f515e6 | balrog | static struct intc_group groups[] = { |
507 | 80f515e6 | balrog | INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI), |
508 | 80f515e6 | balrog | INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), |
509 | 80f515e6 | balrog | INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI), |
510 | 80f515e6 | balrog | INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI), |
511 | 80f515e6 | balrog | INTC_GROUP(REF, REF_RCMI, REF_ROVI), |
512 | 80f515e6 | balrog | }; |
513 | 80f515e6 | balrog | |
514 | 80f515e6 | balrog | static struct intc_prio_reg prio_registers[] = { |
515 | 80f515e6 | balrog | { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, |
516 | 80f515e6 | balrog | { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } }, |
517 | 80f515e6 | balrog | { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } }, |
518 | 80f515e6 | balrog | { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } }, |
519 | 80f515e6 | balrog | { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0, |
520 | 80f515e6 | balrog | TMU4, TMU3, |
521 | 80f515e6 | balrog | PCIC1, PCIC0_PCISERR } }, |
522 | 80f515e6 | balrog | }; |
523 | 80f515e6 | balrog | |
524 | 80f515e6 | balrog | /* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
|
525 | 80f515e6 | balrog | |
526 | 80f515e6 | balrog | static struct intc_vect vectors_dma4[] = { |
527 | 80f515e6 | balrog | INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), |
528 | 80f515e6 | balrog | INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), |
529 | 80f515e6 | balrog | INTC_VECT(DMAC_DMAE, 0x6c0),
|
530 | 80f515e6 | balrog | }; |
531 | 80f515e6 | balrog | |
532 | 80f515e6 | balrog | static struct intc_group groups_dma4[] = { |
533 | 80f515e6 | balrog | INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, |
534 | 80f515e6 | balrog | DMAC_DMTE3, DMAC_DMAE), |
535 | 80f515e6 | balrog | }; |
536 | 80f515e6 | balrog | |
537 | 80f515e6 | balrog | /* SH7750R and SH7751R both have 8-channel DMA controllers */
|
538 | 80f515e6 | balrog | |
539 | 80f515e6 | balrog | static struct intc_vect vectors_dma8[] = { |
540 | 80f515e6 | balrog | INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), |
541 | 80f515e6 | balrog | INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), |
542 | 80f515e6 | balrog | INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0), |
543 | 80f515e6 | balrog | INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0), |
544 | 80f515e6 | balrog | INTC_VECT(DMAC_DMAE, 0x6c0),
|
545 | 80f515e6 | balrog | }; |
546 | 80f515e6 | balrog | |
547 | 80f515e6 | balrog | static struct intc_group groups_dma8[] = { |
548 | 80f515e6 | balrog | INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, |
549 | 80f515e6 | balrog | DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5, |
550 | 80f515e6 | balrog | DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE), |
551 | 80f515e6 | balrog | }; |
552 | 80f515e6 | balrog | |
553 | 80f515e6 | balrog | /* SH7750R, SH7751 and SH7751R all have two extra timer channels */
|
554 | 80f515e6 | balrog | |
555 | 80f515e6 | balrog | static struct intc_vect vectors_tmu34[] = { |
556 | 80f515e6 | balrog | INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80), |
557 | 80f515e6 | balrog | }; |
558 | 80f515e6 | balrog | |
559 | 80f515e6 | balrog | static struct intc_mask_reg mask_registers[] = { |
560 | 80f515e6 | balrog | { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */ |
561 | 80f515e6 | balrog | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
562 | 80f515e6 | balrog | 0, 0, 0, 0, 0, 0, TMU4, TMU3, |
563 | 80f515e6 | balrog | PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, |
564 | 80f515e6 | balrog | PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, |
565 | 80f515e6 | balrog | PCIC1_PCIDMA3, PCIC0_PCISERR } }, |
566 | 80f515e6 | balrog | }; |
567 | 80f515e6 | balrog | |
568 | 80f515e6 | balrog | /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
|
569 | 80f515e6 | balrog | |
570 | 80f515e6 | balrog | static struct intc_vect vectors_irlm[] = { |
571 | 80f515e6 | balrog | INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0), |
572 | 80f515e6 | balrog | INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360), |
573 | 80f515e6 | balrog | }; |
574 | 80f515e6 | balrog | |
575 | 80f515e6 | balrog | /* SH7751 and SH7751R both have PCI */
|
576 | 80f515e6 | balrog | |
577 | 80f515e6 | balrog | static struct intc_vect vectors_pci[] = { |
578 | 80f515e6 | balrog | INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0), |
579 | 80f515e6 | balrog | INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0), |
580 | 80f515e6 | balrog | INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60), |
581 | 80f515e6 | balrog | INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20), |
582 | 80f515e6 | balrog | }; |
583 | 80f515e6 | balrog | |
584 | 80f515e6 | balrog | static struct intc_group groups_pci[] = { |
585 | 80f515e6 | balrog | INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, |
586 | 80f515e6 | balrog | PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3), |
587 | 80f515e6 | balrog | }; |
588 | 80f515e6 | balrog | |
589 | c6d86a33 | balrog | static struct intc_vect vectors_irl[] = { |
590 | c6d86a33 | balrog | INTC_VECT(IRL_0, 0x200),
|
591 | c6d86a33 | balrog | INTC_VECT(IRL_1, 0x220),
|
592 | c6d86a33 | balrog | INTC_VECT(IRL_2, 0x240),
|
593 | c6d86a33 | balrog | INTC_VECT(IRL_3, 0x260),
|
594 | c6d86a33 | balrog | INTC_VECT(IRL_4, 0x280),
|
595 | c6d86a33 | balrog | INTC_VECT(IRL_5, 0x2a0),
|
596 | c6d86a33 | balrog | INTC_VECT(IRL_6, 0x2c0),
|
597 | c6d86a33 | balrog | INTC_VECT(IRL_7, 0x2e0),
|
598 | c6d86a33 | balrog | INTC_VECT(IRL_8, 0x300),
|
599 | c6d86a33 | balrog | INTC_VECT(IRL_9, 0x320),
|
600 | c6d86a33 | balrog | INTC_VECT(IRL_A, 0x340),
|
601 | c6d86a33 | balrog | INTC_VECT(IRL_B, 0x360),
|
602 | c6d86a33 | balrog | INTC_VECT(IRL_C, 0x380),
|
603 | c6d86a33 | balrog | INTC_VECT(IRL_D, 0x3a0),
|
604 | c6d86a33 | balrog | INTC_VECT(IRL_E, 0x3c0),
|
605 | c6d86a33 | balrog | }; |
606 | c6d86a33 | balrog | |
607 | c6d86a33 | balrog | static struct intc_group groups_irl[] = { |
608 | c6d86a33 | balrog | INTC_GROUP(IRL, IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6, |
609 | c6d86a33 | balrog | IRL_7, IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E), |
610 | c6d86a33 | balrog | }; |
611 | c6d86a33 | balrog | |
612 | 29e179bc | aurel32 | /**********************************************************************
|
613 | 29e179bc | aurel32 | Memory mapped cache and TLB
|
614 | 29e179bc | aurel32 | **********************************************************************/
|
615 | 29e179bc | aurel32 | |
616 | 29e179bc | aurel32 | #define MM_REGION_MASK 0x07000000 |
617 | 29e179bc | aurel32 | #define MM_ICACHE_ADDR (0) |
618 | 29e179bc | aurel32 | #define MM_ICACHE_DATA (1) |
619 | 29e179bc | aurel32 | #define MM_ITLB_ADDR (2) |
620 | 29e179bc | aurel32 | #define MM_ITLB_DATA (3) |
621 | 29e179bc | aurel32 | #define MM_OCACHE_ADDR (4) |
622 | 29e179bc | aurel32 | #define MM_OCACHE_DATA (5) |
623 | 29e179bc | aurel32 | #define MM_UTLB_ADDR (6) |
624 | 29e179bc | aurel32 | #define MM_UTLB_DATA (7) |
625 | 29e179bc | aurel32 | #define MM_REGION_TYPE(addr) ((addr & MM_REGION_MASK) >> 24) |
626 | 29e179bc | aurel32 | |
627 | a8170e5e | Avi Kivity | static uint64_t invalid_read(void *opaque, hwaddr addr) |
628 | 29e179bc | aurel32 | { |
629 | 43dc2a64 | Blue Swirl | abort(); |
630 | 29e179bc | aurel32 | |
631 | 29e179bc | aurel32 | return 0; |
632 | 29e179bc | aurel32 | } |
633 | 29e179bc | aurel32 | |
634 | a8170e5e | Avi Kivity | static uint64_t sh7750_mmct_read(void *opaque, hwaddr addr, |
635 | 1a4004c7 | Benoît Canet | unsigned size)
|
636 | 29e179bc | aurel32 | { |
637 | bc656a29 | Aurelien Jarno | SH7750State *s = opaque; |
638 | 29e179bc | aurel32 | uint32_t ret = 0;
|
639 | 29e179bc | aurel32 | |
640 | 1a4004c7 | Benoît Canet | if (size != 4) { |
641 | 1a4004c7 | Benoît Canet | return invalid_read(opaque, addr);
|
642 | 1a4004c7 | Benoît Canet | } |
643 | 1a4004c7 | Benoît Canet | |
644 | 29e179bc | aurel32 | switch (MM_REGION_TYPE(addr)) {
|
645 | 29e179bc | aurel32 | case MM_ICACHE_ADDR:
|
646 | 29e179bc | aurel32 | case MM_ICACHE_DATA:
|
647 | 29e179bc | aurel32 | /* do nothing */
|
648 | 29e179bc | aurel32 | break;
|
649 | 29e179bc | aurel32 | case MM_ITLB_ADDR:
|
650 | bc656a29 | Aurelien Jarno | ret = cpu_sh4_read_mmaped_itlb_addr(s->cpu, addr); |
651 | bc656a29 | Aurelien Jarno | break;
|
652 | 29e179bc | aurel32 | case MM_ITLB_DATA:
|
653 | bc656a29 | Aurelien Jarno | ret = cpu_sh4_read_mmaped_itlb_data(s->cpu, addr); |
654 | bc656a29 | Aurelien Jarno | break;
|
655 | 29e179bc | aurel32 | case MM_OCACHE_ADDR:
|
656 | 29e179bc | aurel32 | case MM_OCACHE_DATA:
|
657 | 29e179bc | aurel32 | /* do nothing */
|
658 | 29e179bc | aurel32 | break;
|
659 | 29e179bc | aurel32 | case MM_UTLB_ADDR:
|
660 | bc656a29 | Aurelien Jarno | ret = cpu_sh4_read_mmaped_utlb_addr(s->cpu, addr); |
661 | bc656a29 | Aurelien Jarno | break;
|
662 | 29e179bc | aurel32 | case MM_UTLB_DATA:
|
663 | bc656a29 | Aurelien Jarno | ret = cpu_sh4_read_mmaped_utlb_data(s->cpu, addr); |
664 | bc656a29 | Aurelien Jarno | break;
|
665 | 29e179bc | aurel32 | default:
|
666 | 43dc2a64 | Blue Swirl | abort(); |
667 | 29e179bc | aurel32 | } |
668 | 29e179bc | aurel32 | |
669 | 29e179bc | aurel32 | return ret;
|
670 | 29e179bc | aurel32 | } |
671 | 29e179bc | aurel32 | |
672 | a8170e5e | Avi Kivity | static void invalid_write(void *opaque, hwaddr addr, |
673 | 1a4004c7 | Benoît Canet | uint64_t mem_value) |
674 | 29e179bc | aurel32 | { |
675 | 43dc2a64 | Blue Swirl | abort(); |
676 | 29e179bc | aurel32 | } |
677 | 29e179bc | aurel32 | |
678 | a8170e5e | Avi Kivity | static void sh7750_mmct_write(void *opaque, hwaddr addr, |
679 | 1a4004c7 | Benoît Canet | uint64_t mem_value, unsigned size)
|
680 | 29e179bc | aurel32 | { |
681 | 29e179bc | aurel32 | SH7750State *s = opaque; |
682 | 29e179bc | aurel32 | |
683 | 1a4004c7 | Benoît Canet | if (size != 4) { |
684 | 1a4004c7 | Benoît Canet | invalid_write(opaque, addr, mem_value); |
685 | 1a4004c7 | Benoît Canet | } |
686 | 1a4004c7 | Benoît Canet | |
687 | 29e179bc | aurel32 | switch (MM_REGION_TYPE(addr)) {
|
688 | 29e179bc | aurel32 | case MM_ICACHE_ADDR:
|
689 | 29e179bc | aurel32 | case MM_ICACHE_DATA:
|
690 | 29e179bc | aurel32 | /* do nothing */
|
691 | 29e179bc | aurel32 | break;
|
692 | 29e179bc | aurel32 | case MM_ITLB_ADDR:
|
693 | c0f809c4 | Aurelien Jarno | cpu_sh4_write_mmaped_itlb_addr(s->cpu, addr, mem_value); |
694 | c0f809c4 | Aurelien Jarno | break;
|
695 | 29e179bc | aurel32 | case MM_ITLB_DATA:
|
696 | 9f97309a | Aurelien Jarno | cpu_sh4_write_mmaped_itlb_data(s->cpu, addr, mem_value); |
697 | 43dc2a64 | Blue Swirl | abort(); |
698 | 29e179bc | aurel32 | break;
|
699 | 29e179bc | aurel32 | case MM_OCACHE_ADDR:
|
700 | 29e179bc | aurel32 | case MM_OCACHE_DATA:
|
701 | 29e179bc | aurel32 | /* do nothing */
|
702 | 29e179bc | aurel32 | break;
|
703 | 29e179bc | aurel32 | case MM_UTLB_ADDR:
|
704 | 29e179bc | aurel32 | cpu_sh4_write_mmaped_utlb_addr(s->cpu, addr, mem_value); |
705 | 29e179bc | aurel32 | break;
|
706 | 29e179bc | aurel32 | case MM_UTLB_DATA:
|
707 | 9f97309a | Aurelien Jarno | cpu_sh4_write_mmaped_utlb_data(s->cpu, addr, mem_value); |
708 | 29e179bc | aurel32 | break;
|
709 | 29e179bc | aurel32 | default:
|
710 | 43dc2a64 | Blue Swirl | abort(); |
711 | 29e179bc | aurel32 | break;
|
712 | 29e179bc | aurel32 | } |
713 | 29e179bc | aurel32 | } |
714 | 29e179bc | aurel32 | |
715 | 12f30833 | Stefan Weil | static const MemoryRegionOps sh7750_mmct_ops = { |
716 | 1a4004c7 | Benoît Canet | .read = sh7750_mmct_read, |
717 | 1a4004c7 | Benoît Canet | .write = sh7750_mmct_write, |
718 | 1a4004c7 | Benoît Canet | .endianness = DEVICE_NATIVE_ENDIAN, |
719 | 29e179bc | aurel32 | }; |
720 | 29e179bc | aurel32 | |
721 | 382863e2 | Benoît Canet | SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem) |
722 | 27c7ca7e | bellard | { |
723 | 27c7ca7e | bellard | SH7750State *s; |
724 | 27c7ca7e | bellard | |
725 | 7267c094 | Anthony Liguori | s = g_malloc0(sizeof(SH7750State));
|
726 | 27c7ca7e | bellard | s->cpu = cpu; |
727 | 27c7ca7e | bellard | s->periph_freq = 60000000; /* 60MHz */ |
728 | 382863e2 | Benoît Canet | memory_region_init_io(&s->iomem, &sh7750_mem_ops, s, |
729 | 382863e2 | Benoît Canet | "memory", 0x1fc01000); |
730 | 382863e2 | Benoît Canet | |
731 | 382863e2 | Benoît Canet | memory_region_init_alias(&s->iomem_1f0, "memory-1f0",
|
732 | 382863e2 | Benoît Canet | &s->iomem, 0x1f000000, 0x1000); |
733 | 382863e2 | Benoît Canet | memory_region_add_subregion(sysmem, 0x1f000000, &s->iomem_1f0);
|
734 | 382863e2 | Benoît Canet | |
735 | 382863e2 | Benoît Canet | memory_region_init_alias(&s->iomem_ff0, "memory-ff0",
|
736 | 382863e2 | Benoît Canet | &s->iomem, 0x1f000000, 0x1000); |
737 | 382863e2 | Benoît Canet | memory_region_add_subregion(sysmem, 0xff000000, &s->iomem_ff0);
|
738 | 382863e2 | Benoît Canet | |
739 | 382863e2 | Benoît Canet | memory_region_init_alias(&s->iomem_1f8, "memory-1f8",
|
740 | 382863e2 | Benoît Canet | &s->iomem, 0x1f800000, 0x1000); |
741 | 382863e2 | Benoît Canet | memory_region_add_subregion(sysmem, 0x1f800000, &s->iomem_1f8);
|
742 | 382863e2 | Benoît Canet | |
743 | 382863e2 | Benoît Canet | memory_region_init_alias(&s->iomem_ff8, "memory-ff8",
|
744 | 382863e2 | Benoît Canet | &s->iomem, 0x1f800000, 0x1000); |
745 | 382863e2 | Benoît Canet | memory_region_add_subregion(sysmem, 0xff800000, &s->iomem_ff8);
|
746 | 382863e2 | Benoît Canet | |
747 | 382863e2 | Benoît Canet | memory_region_init_alias(&s->iomem_1fc, "memory-1fc",
|
748 | 382863e2 | Benoît Canet | &s->iomem, 0x1fc00000, 0x1000); |
749 | 382863e2 | Benoît Canet | memory_region_add_subregion(sysmem, 0x1fc00000, &s->iomem_1fc);
|
750 | 382863e2 | Benoît Canet | |
751 | 382863e2 | Benoît Canet | memory_region_init_alias(&s->iomem_ffc, "memory-ffc",
|
752 | 382863e2 | Benoît Canet | &s->iomem, 0x1fc00000, 0x1000); |
753 | 382863e2 | Benoît Canet | memory_region_add_subregion(sysmem, 0xffc00000, &s->iomem_ffc);
|
754 | 2f062c72 | ths | |
755 | 1a4004c7 | Benoît Canet | memory_region_init_io(&s->mmct_iomem, &sh7750_mmct_ops, s, |
756 | 1a4004c7 | Benoît Canet | "cache-and-tlb", 0x08000000); |
757 | 1a4004c7 | Benoît Canet | memory_region_add_subregion(sysmem, 0xf0000000, &s->mmct_iomem);
|
758 | 29e179bc | aurel32 | |
759 | b279e5ef | Benoît Canet | sh_intc_init(sysmem, &s->intc, NR_SOURCES, |
760 | 80f515e6 | balrog | _INTC_ARRAY(mask_registers), |
761 | 80f515e6 | balrog | _INTC_ARRAY(prio_registers)); |
762 | 80f515e6 | balrog | |
763 | 0fd3ca30 | aurel32 | sh_intc_register_sources(&s->intc, |
764 | 80f515e6 | balrog | _INTC_ARRAY(vectors), |
765 | 80f515e6 | balrog | _INTC_ARRAY(groups)); |
766 | 80f515e6 | balrog | |
767 | e96e2044 | ths | cpu->intc_handle = &s->intc; |
768 | e96e2044 | ths | |
769 | 9a9d0b81 | Benoît Canet | sh_serial_init(sysmem, 0x1fe00000,
|
770 | 9a9d0b81 | Benoît Canet | 0, s->periph_freq, serial_hds[0], |
771 | 9a9d0b81 | Benoît Canet | s->intc.irqs[SCI1_ERI], |
772 | 9a9d0b81 | Benoît Canet | s->intc.irqs[SCI1_RXI], |
773 | 9a9d0b81 | Benoît Canet | s->intc.irqs[SCI1_TXI], |
774 | 9a9d0b81 | Benoît Canet | s->intc.irqs[SCI1_TEI], |
775 | 9a9d0b81 | Benoît Canet | NULL);
|
776 | 9a9d0b81 | Benoît Canet | sh_serial_init(sysmem, 0x1fe80000,
|
777 | 9a9d0b81 | Benoît Canet | SH_SERIAL_FEAT_SCIF, |
778 | 9a9d0b81 | Benoît Canet | s->periph_freq, serial_hds[1],
|
779 | 9a9d0b81 | Benoît Canet | s->intc.irqs[SCIF_ERI], |
780 | 9a9d0b81 | Benoît Canet | s->intc.irqs[SCIF_RXI], |
781 | 9a9d0b81 | Benoît Canet | s->intc.irqs[SCIF_TXI], |
782 | 9a9d0b81 | Benoît Canet | NULL,
|
783 | 9a9d0b81 | Benoît Canet | s->intc.irqs[SCIF_BRI]); |
784 | cd1a3f68 | ths | |
785 | 89e29451 | Benoît Canet | tmu012_init(sysmem, 0x1fd80000,
|
786 | cd1a3f68 | ths | TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK, |
787 | 703243a0 | balrog | s->periph_freq, |
788 | 96e2fc41 | aurel32 | s->intc.irqs[TMU0], |
789 | 96e2fc41 | aurel32 | s->intc.irqs[TMU1], |
790 | 96e2fc41 | aurel32 | s->intc.irqs[TMU2_TUNI], |
791 | 96e2fc41 | aurel32 | s->intc.irqs[TMU2_TICPI]); |
792 | 80f515e6 | balrog | |
793 | 0fd3ca30 | aurel32 | if (cpu->id & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) {
|
794 | 0fd3ca30 | aurel32 | sh_intc_register_sources(&s->intc, |
795 | 80f515e6 | balrog | _INTC_ARRAY(vectors_dma4), |
796 | 80f515e6 | balrog | _INTC_ARRAY(groups_dma4)); |
797 | 80f515e6 | balrog | } |
798 | 80f515e6 | balrog | |
799 | 0fd3ca30 | aurel32 | if (cpu->id & (SH_CPU_SH7750R | SH_CPU_SH7751R)) {
|
800 | 0fd3ca30 | aurel32 | sh_intc_register_sources(&s->intc, |
801 | 80f515e6 | balrog | _INTC_ARRAY(vectors_dma8), |
802 | 80f515e6 | balrog | _INTC_ARRAY(groups_dma8)); |
803 | 80f515e6 | balrog | } |
804 | 80f515e6 | balrog | |
805 | 0fd3ca30 | aurel32 | if (cpu->id & (SH_CPU_SH7750R | SH_CPU_SH7751 | SH_CPU_SH7751R)) {
|
806 | 0fd3ca30 | aurel32 | sh_intc_register_sources(&s->intc, |
807 | 80f515e6 | balrog | _INTC_ARRAY(vectors_tmu34), |
808 | f26ae302 | bellard | NULL, 0); |
809 | 89e29451 | Benoît Canet | tmu012_init(sysmem, 0x1e100000, 0, s->periph_freq, |
810 | 96e2fc41 | aurel32 | s->intc.irqs[TMU3], |
811 | 96e2fc41 | aurel32 | s->intc.irqs[TMU4], |
812 | 703243a0 | balrog | NULL, NULL); |
813 | 80f515e6 | balrog | } |
814 | 80f515e6 | balrog | |
815 | 0fd3ca30 | aurel32 | if (cpu->id & (SH_CPU_SH7751_ALL)) {
|
816 | 0fd3ca30 | aurel32 | sh_intc_register_sources(&s->intc, |
817 | 80f515e6 | balrog | _INTC_ARRAY(vectors_pci), |
818 | 80f515e6 | balrog | _INTC_ARRAY(groups_pci)); |
819 | 80f515e6 | balrog | } |
820 | 80f515e6 | balrog | |
821 | 0fd3ca30 | aurel32 | if (cpu->id & (SH_CPU_SH7750S | SH_CPU_SH7750R | SH_CPU_SH7751_ALL)) {
|
822 | 0fd3ca30 | aurel32 | sh_intc_register_sources(&s->intc, |
823 | 80f515e6 | balrog | _INTC_ARRAY(vectors_irlm), |
824 | f26ae302 | bellard | NULL, 0); |
825 | 80f515e6 | balrog | } |
826 | 80f515e6 | balrog | |
827 | c6d86a33 | balrog | sh_intc_register_sources(&s->intc, |
828 | c6d86a33 | balrog | _INTC_ARRAY(vectors_irl), |
829 | c6d86a33 | balrog | _INTC_ARRAY(groups_irl)); |
830 | 27c7ca7e | bellard | return s;
|
831 | 27c7ca7e | bellard | } |
832 | c6d86a33 | balrog | |
833 | c6d86a33 | balrog | qemu_irq sh7750_irl(SH7750State *s) |
834 | c6d86a33 | balrog | { |
835 | c6d86a33 | balrog | sh_intc_toggle_source(sh_intc_source(&s->intc, IRL), 1, 0); /* enable */ |
836 | c6d86a33 | balrog | return qemu_allocate_irqs(sh_intc_set_irl, sh_intc_source(&s->intc, IRL),
|
837 | c6d86a33 | balrog | 1)[0]; |
838 | c6d86a33 | balrog | } |