History | View | Annotate | Download (52.8 kB)
target-ppc: emulate cmpb instruction
Needed for Power ISA version 2.05 compliance.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Use mul*2 in mulh* insns
Cc: Alexander Graf <agraf@suse.de>Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-ppc: Split out SO, OV, CA fields from XER
In preparation for more efficient setting of these fields.
misc: move include files to include/qemu/
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
target-ppc: use the softfloat float32_muladd function
Use the new softfloat float32_muladd() function to implement the vmaddfpand vnmsubfp instructions. As a bonus we can get rid of the call to theHANDLE_NAN3 macro, as the NaN handling is directly done at the softfloat...
target-ppc: get rid of the HANDLE_NAN{1, 2, 3} macros
We can finally get rid of the ugly HANDLE_NAN{1,2,3} macros.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: simplify NaN propagation for vector functions
Commit e024e881bb1a8b5085026589360d26ed97acdd64 provided a pickNaN()function for PowerPC, implementing the correct NaN propagation rules.Therefore there is no need to test the operands manually, we can rely...
target-ppc: use the softfloat min/max functions
Use the new softfloat float32_min() and float32_max() to implement thevminfp and vmaxfp instructions. As a bonus we can get rid of the call tothe HANDLE_NAN2 macro, as the NaN handling is directly done at the...
ppc: Make hbrev table const
Lookup table 'hbrev' is never written to, so add a 'const' qualifier.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Alexander Graf <agraf@suse.de>Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Alexander Graf <agraf@suse.de>
ppc: Split integer and vector ops
Move integer and vector ops to int_helper.c.
ppc: Avoid AREG0 for integer and vector helpers
Add an explicit CPUPPCState parameter instead of relying on AREG0.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Alexander Graf <agraf@suse.de>Signed-off-by: Andreas Färber <afaerber@suse.de>...