root / hw / char / imx_serial.c @ db1b58e9
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1 | 40b6f911 | Peter Chubb | /*
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2 | 40b6f911 | Peter Chubb | * IMX31 UARTS
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3 | 40b6f911 | Peter Chubb | *
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4 | 40b6f911 | Peter Chubb | * Copyright (c) 2008 OKL
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5 | 40b6f911 | Peter Chubb | * Originally Written by Hans Jiang
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6 | 40b6f911 | Peter Chubb | * Copyright (c) 2011 NICTA Pty Ltd.
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7 | 40b6f911 | Peter Chubb | *
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8 | 40b6f911 | Peter Chubb | * This work is licensed under the terms of the GNU GPL, version 2 or later.
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9 | 40b6f911 | Peter Chubb | * See the COPYING file in the top-level directory.
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10 | 40b6f911 | Peter Chubb | *
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11 | 40b6f911 | Peter Chubb | * This is a `bare-bones' implementation of the IMX series serial ports.
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12 | 40b6f911 | Peter Chubb | * TODO:
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13 | 40b6f911 | Peter Chubb | * -- implement FIFOs. The real hardware has 32 word transmit
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14 | 40b6f911 | Peter Chubb | * and receive FIFOs; we currently use a 1-char buffer
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15 | 40b6f911 | Peter Chubb | * -- implement DMA
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16 | 40b6f911 | Peter Chubb | * -- implement BAUD-rate and modem lines, for when the backend
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17 | 40b6f911 | Peter Chubb | * is a real serial device.
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18 | 40b6f911 | Peter Chubb | */
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19 | 40b6f911 | Peter Chubb | |
20 | 83c9f4ca | Paolo Bonzini | #include "hw/hw.h" |
21 | 83c9f4ca | Paolo Bonzini | #include "hw/sysbus.h" |
22 | 9c17d615 | Paolo Bonzini | #include "sysemu/sysemu.h" |
23 | dccfcd0e | Paolo Bonzini | #include "sysemu/char.h" |
24 | 0d09e41a | Paolo Bonzini | #include "hw/arm/imx.h" |
25 | 40b6f911 | Peter Chubb | |
26 | 40b6f911 | Peter Chubb | //#define DEBUG_SERIAL 1
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27 | 40b6f911 | Peter Chubb | #ifdef DEBUG_SERIAL
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28 | 40b6f911 | Peter Chubb | #define DPRINTF(fmt, args...) \
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29 | 40b6f911 | Peter Chubb | do { printf("imx_serial: " fmt , ##args); } while (0) |
30 | 40b6f911 | Peter Chubb | #else
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31 | 40b6f911 | Peter Chubb | #define DPRINTF(fmt, args...) do {} while (0) |
32 | 40b6f911 | Peter Chubb | #endif
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33 | 40b6f911 | Peter Chubb | |
34 | 40b6f911 | Peter Chubb | /*
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35 | 40b6f911 | Peter Chubb | * Define to 1 for messages about attempts to
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36 | 40b6f911 | Peter Chubb | * access unimplemented registers or similar.
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37 | 40b6f911 | Peter Chubb | */
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38 | 40b6f911 | Peter Chubb | //#define DEBUG_IMPLEMENTATION 1
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39 | 40b6f911 | Peter Chubb | #ifdef DEBUG_IMPLEMENTATION
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40 | 40b6f911 | Peter Chubb | # define IPRINTF(fmt, args...) \
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41 | 40b6f911 | Peter Chubb | do { fprintf(stderr, "imx_serial: " fmt, ##args); } while (0) |
42 | 40b6f911 | Peter Chubb | #else
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43 | 40b6f911 | Peter Chubb | # define IPRINTF(fmt, args...) do {} while (0) |
44 | 40b6f911 | Peter Chubb | #endif
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45 | 40b6f911 | Peter Chubb | |
46 | 40b6f911 | Peter Chubb | typedef struct { |
47 | 40b6f911 | Peter Chubb | SysBusDevice busdev; |
48 | 40b6f911 | Peter Chubb | MemoryRegion iomem; |
49 | 40b6f911 | Peter Chubb | int32_t readbuff; |
50 | 40b6f911 | Peter Chubb | |
51 | 40b6f911 | Peter Chubb | uint32_t usr1; |
52 | 40b6f911 | Peter Chubb | uint32_t usr2; |
53 | 40b6f911 | Peter Chubb | uint32_t ucr1; |
54 | 40b6f911 | Peter Chubb | uint32_t ucr2; |
55 | 40b6f911 | Peter Chubb | uint32_t uts1; |
56 | 40b6f911 | Peter Chubb | |
57 | 40b6f911 | Peter Chubb | /*
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58 | 40b6f911 | Peter Chubb | * The registers below are implemented just so that the
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59 | 40b6f911 | Peter Chubb | * guest OS sees what it has written
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60 | 40b6f911 | Peter Chubb | */
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61 | 40b6f911 | Peter Chubb | uint32_t onems; |
62 | 40b6f911 | Peter Chubb | uint32_t ufcr; |
63 | 40b6f911 | Peter Chubb | uint32_t ubmr; |
64 | 40b6f911 | Peter Chubb | uint32_t ubrc; |
65 | 40b6f911 | Peter Chubb | uint32_t ucr3; |
66 | 40b6f911 | Peter Chubb | |
67 | 40b6f911 | Peter Chubb | qemu_irq irq; |
68 | 40b6f911 | Peter Chubb | CharDriverState *chr; |
69 | 40b6f911 | Peter Chubb | } IMXSerialState; |
70 | 40b6f911 | Peter Chubb | |
71 | 40b6f911 | Peter Chubb | static const VMStateDescription vmstate_imx_serial = { |
72 | 40b6f911 | Peter Chubb | .name = "imx-serial",
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73 | 40b6f911 | Peter Chubb | .version_id = 1,
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74 | 40b6f911 | Peter Chubb | .minimum_version_id = 1,
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75 | 40b6f911 | Peter Chubb | .minimum_version_id_old = 1,
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76 | 40b6f911 | Peter Chubb | .fields = (VMStateField[]) { |
77 | 40b6f911 | Peter Chubb | VMSTATE_INT32(readbuff, IMXSerialState), |
78 | 40b6f911 | Peter Chubb | VMSTATE_UINT32(usr1, IMXSerialState), |
79 | 40b6f911 | Peter Chubb | VMSTATE_UINT32(usr2, IMXSerialState), |
80 | 40b6f911 | Peter Chubb | VMSTATE_UINT32(ucr1, IMXSerialState), |
81 | 40b6f911 | Peter Chubb | VMSTATE_UINT32(uts1, IMXSerialState), |
82 | 40b6f911 | Peter Chubb | VMSTATE_UINT32(onems, IMXSerialState), |
83 | 40b6f911 | Peter Chubb | VMSTATE_UINT32(ufcr, IMXSerialState), |
84 | 40b6f911 | Peter Chubb | VMSTATE_UINT32(ubmr, IMXSerialState), |
85 | 40b6f911 | Peter Chubb | VMSTATE_UINT32(ubrc, IMXSerialState), |
86 | 40b6f911 | Peter Chubb | VMSTATE_UINT32(ucr3, IMXSerialState), |
87 | 40b6f911 | Peter Chubb | VMSTATE_END_OF_LIST() |
88 | 40b6f911 | Peter Chubb | }, |
89 | 40b6f911 | Peter Chubb | }; |
90 | 40b6f911 | Peter Chubb | |
91 | 40b6f911 | Peter Chubb | |
92 | 40b6f911 | Peter Chubb | #define URXD_CHARRDY (1<<15) /* character read is valid */ |
93 | 40b6f911 | Peter Chubb | #define URXD_ERR (1<<14) /* Character has error */ |
94 | 40b6f911 | Peter Chubb | #define URXD_BRK (1<<11) /* Break received */ |
95 | 40b6f911 | Peter Chubb | |
96 | 40b6f911 | Peter Chubb | #define USR1_PARTYER (1<<15) /* Parity Error */ |
97 | 40b6f911 | Peter Chubb | #define USR1_RTSS (1<<14) /* RTS pin status */ |
98 | 40b6f911 | Peter Chubb | #define USR1_TRDY (1<<13) /* Tx ready */ |
99 | 40b6f911 | Peter Chubb | #define USR1_RTSD (1<<12) /* RTS delta: pin changed state */ |
100 | 40b6f911 | Peter Chubb | #define USR1_ESCF (1<<11) /* Escape sequence interrupt */ |
101 | 40b6f911 | Peter Chubb | #define USR1_FRAMERR (1<<10) /* Framing error */ |
102 | 40b6f911 | Peter Chubb | #define USR1_RRDY (1<<9) /* receiver ready */ |
103 | 40b6f911 | Peter Chubb | #define USR1_AGTIM (1<<8) /* Aging timer interrupt */ |
104 | 40b6f911 | Peter Chubb | #define USR1_DTRD (1<<7) /* DTR changed */ |
105 | 40b6f911 | Peter Chubb | #define USR1_RXDS (1<<6) /* Receiver is idle */ |
106 | 40b6f911 | Peter Chubb | #define USR1_AIRINT (1<<5) /* Aysnch IR interrupt */ |
107 | 40b6f911 | Peter Chubb | #define USR1_AWAKE (1<<4) /* Falling edge detected on RXd pin */ |
108 | 40b6f911 | Peter Chubb | |
109 | 40b6f911 | Peter Chubb | #define USR2_ADET (1<<15) /* Autobaud complete */ |
110 | 40b6f911 | Peter Chubb | #define USR2_TXFE (1<<14) /* Transmit FIFO empty */ |
111 | 40b6f911 | Peter Chubb | #define USR2_DTRF (1<<13) /* DTR/DSR transition */ |
112 | 40b6f911 | Peter Chubb | #define USR2_IDLE (1<<12) /* UART has been idle for too long */ |
113 | 40b6f911 | Peter Chubb | #define USR2_ACST (1<<11) /* Autobaud counter stopped */ |
114 | 40b6f911 | Peter Chubb | #define USR2_RIDELT (1<<10) /* Ring Indicator delta */ |
115 | 40b6f911 | Peter Chubb | #define USR2_RIIN (1<<9) /* Ring Indicator Input */ |
116 | 40b6f911 | Peter Chubb | #define USR2_IRINT (1<<8) /* Serial Infrared Interrupt */ |
117 | 40b6f911 | Peter Chubb | #define USR2_WAKE (1<<7) /* Start bit detected */ |
118 | 40b6f911 | Peter Chubb | #define USR2_DCDDELT (1<<6) /* Data Carrier Detect delta */ |
119 | 40b6f911 | Peter Chubb | #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */ |
120 | 40b6f911 | Peter Chubb | #define USR2_RTSF (1<<4) /* RTS transition */ |
121 | 40b6f911 | Peter Chubb | #define USR2_TXDC (1<<3) /* Transmission complete */ |
122 | 40b6f911 | Peter Chubb | #define USR2_BRCD (1<<2) /* Break condition detected */ |
123 | 40b6f911 | Peter Chubb | #define USR2_ORE (1<<1) /* Overrun error */ |
124 | 40b6f911 | Peter Chubb | #define USR2_RDR (1<<0) /* Receive data ready */ |
125 | 40b6f911 | Peter Chubb | |
126 | 40b6f911 | Peter Chubb | #define UCR1_TRDYEN (1<<13) /* Tx Ready Interrupt Enable */ |
127 | 40b6f911 | Peter Chubb | #define UCR1_RRDYEN (1<<9) /* Rx Ready Interrupt Enable */ |
128 | 40b6f911 | Peter Chubb | #define UCR1_TXMPTYEN (1<<6) /* Tx Empty Interrupt Enable */ |
129 | 40b6f911 | Peter Chubb | #define UCR1_UARTEN (1<<0) /* UART Enable */ |
130 | 40b6f911 | Peter Chubb | |
131 | 40b6f911 | Peter Chubb | #define UCR2_TXEN (1<<2) /* Transmitter enable */ |
132 | 40b6f911 | Peter Chubb | #define UCR2_RXEN (1<<1) /* Receiver enable */ |
133 | 40b6f911 | Peter Chubb | #define UCR2_SRST (1<<0) /* Reset complete */ |
134 | 40b6f911 | Peter Chubb | |
135 | 40b6f911 | Peter Chubb | #define UTS1_TXEMPTY (1<<6) |
136 | 40b6f911 | Peter Chubb | #define UTS1_RXEMPTY (1<<5) |
137 | 40b6f911 | Peter Chubb | #define UTS1_TXFULL (1<<4) |
138 | 40b6f911 | Peter Chubb | #define UTS1_RXFULL (1<<3) |
139 | 40b6f911 | Peter Chubb | |
140 | 40b6f911 | Peter Chubb | static void imx_update(IMXSerialState *s) |
141 | 40b6f911 | Peter Chubb | { |
142 | 40b6f911 | Peter Chubb | uint32_t flags; |
143 | 40b6f911 | Peter Chubb | |
144 | 40b6f911 | Peter Chubb | flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY); |
145 | 40b6f911 | Peter Chubb | if (!(s->ucr1 & UCR1_TXMPTYEN)) {
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146 | 40b6f911 | Peter Chubb | flags &= ~USR1_TRDY; |
147 | 40b6f911 | Peter Chubb | } |
148 | 40b6f911 | Peter Chubb | |
149 | 40b6f911 | Peter Chubb | qemu_set_irq(s->irq, !!flags); |
150 | 40b6f911 | Peter Chubb | } |
151 | 40b6f911 | Peter Chubb | |
152 | 40b6f911 | Peter Chubb | static void imx_serial_reset(IMXSerialState *s) |
153 | 40b6f911 | Peter Chubb | { |
154 | 40b6f911 | Peter Chubb | |
155 | 40b6f911 | Peter Chubb | s->usr1 = USR1_TRDY | USR1_RXDS; |
156 | 40b6f911 | Peter Chubb | /*
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157 | 40b6f911 | Peter Chubb | * Fake attachment of a terminal: assert RTS.
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158 | 40b6f911 | Peter Chubb | */
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159 | 40b6f911 | Peter Chubb | s->usr1 |= USR1_RTSS; |
160 | 40b6f911 | Peter Chubb | s->usr2 = USR2_TXFE | USR2_TXDC | USR2_DCDIN; |
161 | 40b6f911 | Peter Chubb | s->uts1 = UTS1_RXEMPTY | UTS1_TXEMPTY; |
162 | 40b6f911 | Peter Chubb | s->ucr1 = 0;
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163 | 40b6f911 | Peter Chubb | s->ucr2 = UCR2_SRST; |
164 | 40b6f911 | Peter Chubb | s->ucr3 = 0x700;
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165 | 40b6f911 | Peter Chubb | s->ubmr = 0;
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166 | 40b6f911 | Peter Chubb | s->ubrc = 4;
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167 | 40b6f911 | Peter Chubb | s->readbuff = URXD_ERR; |
168 | 40b6f911 | Peter Chubb | } |
169 | 40b6f911 | Peter Chubb | |
170 | 40b6f911 | Peter Chubb | static void imx_serial_reset_at_boot(DeviceState *dev) |
171 | 40b6f911 | Peter Chubb | { |
172 | 40b6f911 | Peter Chubb | IMXSerialState *s = container_of(dev, IMXSerialState, busdev.qdev); |
173 | 40b6f911 | Peter Chubb | |
174 | 40b6f911 | Peter Chubb | imx_serial_reset(s); |
175 | 40b6f911 | Peter Chubb | |
176 | 40b6f911 | Peter Chubb | /*
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177 | 40b6f911 | Peter Chubb | * enable the uart on boot, so messages from the linux decompresser
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178 | 40b6f911 | Peter Chubb | * are visible. On real hardware this is done by the boot rom
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179 | 40b6f911 | Peter Chubb | * before anything else is loaded.
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180 | 40b6f911 | Peter Chubb | */
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181 | 40b6f911 | Peter Chubb | s->ucr1 = UCR1_UARTEN; |
182 | 40b6f911 | Peter Chubb | s->ucr2 = UCR2_TXEN; |
183 | 40b6f911 | Peter Chubb | |
184 | 40b6f911 | Peter Chubb | } |
185 | 40b6f911 | Peter Chubb | |
186 | a8170e5e | Avi Kivity | static uint64_t imx_serial_read(void *opaque, hwaddr offset, |
187 | 40b6f911 | Peter Chubb | unsigned size)
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188 | 40b6f911 | Peter Chubb | { |
189 | 40b6f911 | Peter Chubb | IMXSerialState *s = (IMXSerialState *)opaque; |
190 | 40b6f911 | Peter Chubb | uint32_t c; |
191 | 40b6f911 | Peter Chubb | |
192 | 40b6f911 | Peter Chubb | DPRINTF("read(offset=%x)\n", offset >> 2); |
193 | 40b6f911 | Peter Chubb | switch (offset >> 2) { |
194 | 40b6f911 | Peter Chubb | case 0x0: /* URXD */ |
195 | 40b6f911 | Peter Chubb | c = s->readbuff; |
196 | 40b6f911 | Peter Chubb | if (!(s->uts1 & UTS1_RXEMPTY)) {
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197 | 40b6f911 | Peter Chubb | /* Character is valid */
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198 | 40b6f911 | Peter Chubb | c |= URXD_CHARRDY; |
199 | 40b6f911 | Peter Chubb | s->usr1 &= ~USR1_RRDY; |
200 | 40b6f911 | Peter Chubb | s->usr2 &= ~USR2_RDR; |
201 | 40b6f911 | Peter Chubb | s->uts1 |= UTS1_RXEMPTY; |
202 | 40b6f911 | Peter Chubb | imx_update(s); |
203 | 40b6f911 | Peter Chubb | qemu_chr_accept_input(s->chr); |
204 | 40b6f911 | Peter Chubb | } |
205 | 40b6f911 | Peter Chubb | return c;
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206 | 40b6f911 | Peter Chubb | |
207 | 40b6f911 | Peter Chubb | case 0x20: /* UCR1 */ |
208 | 40b6f911 | Peter Chubb | return s->ucr1;
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209 | 40b6f911 | Peter Chubb | |
210 | 40b6f911 | Peter Chubb | case 0x21: /* UCR2 */ |
211 | 40b6f911 | Peter Chubb | return s->ucr2;
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212 | 40b6f911 | Peter Chubb | |
213 | 40b6f911 | Peter Chubb | case 0x25: /* USR1 */ |
214 | 40b6f911 | Peter Chubb | return s->usr1;
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215 | 40b6f911 | Peter Chubb | |
216 | 40b6f911 | Peter Chubb | case 0x26: /* USR2 */ |
217 | 40b6f911 | Peter Chubb | return s->usr2;
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218 | 40b6f911 | Peter Chubb | |
219 | 40b6f911 | Peter Chubb | case 0x2A: /* BRM Modulator */ |
220 | 40b6f911 | Peter Chubb | return s->ubmr;
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221 | 40b6f911 | Peter Chubb | |
222 | 40b6f911 | Peter Chubb | case 0x2B: /* Baud Rate Count */ |
223 | 40b6f911 | Peter Chubb | return s->ubrc;
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224 | 40b6f911 | Peter Chubb | |
225 | 40b6f911 | Peter Chubb | case 0x2d: /* Test register */ |
226 | 40b6f911 | Peter Chubb | return s->uts1;
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227 | 40b6f911 | Peter Chubb | |
228 | 40b6f911 | Peter Chubb | case 0x24: /* UFCR */ |
229 | 40b6f911 | Peter Chubb | return s->ufcr;
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230 | 40b6f911 | Peter Chubb | |
231 | 40b6f911 | Peter Chubb | case 0x2c: |
232 | 40b6f911 | Peter Chubb | return s->onems;
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233 | 40b6f911 | Peter Chubb | |
234 | 40b6f911 | Peter Chubb | case 0x22: /* UCR3 */ |
235 | 40b6f911 | Peter Chubb | return s->ucr3;
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236 | 40b6f911 | Peter Chubb | |
237 | 40b6f911 | Peter Chubb | case 0x23: /* UCR4 */ |
238 | 40b6f911 | Peter Chubb | case 0x29: /* BRM Incremental */ |
239 | 40b6f911 | Peter Chubb | return 0x0; /* TODO */ |
240 | 40b6f911 | Peter Chubb | |
241 | 40b6f911 | Peter Chubb | default:
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242 | 40b6f911 | Peter Chubb | IPRINTF("imx_serial_read: bad offset: 0x%x\n", (int)offset); |
243 | 40b6f911 | Peter Chubb | return 0; |
244 | 40b6f911 | Peter Chubb | } |
245 | 40b6f911 | Peter Chubb | } |
246 | 40b6f911 | Peter Chubb | |
247 | a8170e5e | Avi Kivity | static void imx_serial_write(void *opaque, hwaddr offset, |
248 | 40b6f911 | Peter Chubb | uint64_t value, unsigned size)
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249 | 40b6f911 | Peter Chubb | { |
250 | 40b6f911 | Peter Chubb | IMXSerialState *s = (IMXSerialState *)opaque; |
251 | 40b6f911 | Peter Chubb | unsigned char ch; |
252 | 40b6f911 | Peter Chubb | |
253 | 40b6f911 | Peter Chubb | DPRINTF("write(offset=%x, value = %x) to %s\n",
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254 | 40b6f911 | Peter Chubb | offset >> 2,
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255 | 40b6f911 | Peter Chubb | (unsigned int)value, s->chr ? s->chr->label : "NODEV"); |
256 | 40b6f911 | Peter Chubb | |
257 | 40b6f911 | Peter Chubb | switch (offset >> 2) { |
258 | 40b6f911 | Peter Chubb | case 0x10: /* UTXD */ |
259 | 40b6f911 | Peter Chubb | ch = value; |
260 | 40b6f911 | Peter Chubb | if (s->ucr2 & UCR2_TXEN) {
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261 | 40b6f911 | Peter Chubb | if (s->chr) {
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262 | 40b6f911 | Peter Chubb | qemu_chr_fe_write(s->chr, &ch, 1);
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263 | 40b6f911 | Peter Chubb | } |
264 | 40b6f911 | Peter Chubb | s->usr1 &= ~USR1_TRDY; |
265 | 40b6f911 | Peter Chubb | imx_update(s); |
266 | 40b6f911 | Peter Chubb | s->usr1 |= USR1_TRDY; |
267 | 40b6f911 | Peter Chubb | imx_update(s); |
268 | 40b6f911 | Peter Chubb | } |
269 | 40b6f911 | Peter Chubb | break;
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270 | 40b6f911 | Peter Chubb | |
271 | 40b6f911 | Peter Chubb | case 0x20: /* UCR1 */ |
272 | 40b6f911 | Peter Chubb | s->ucr1 = value & 0xffff;
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273 | 40b6f911 | Peter Chubb | DPRINTF("write(ucr1=%x)\n", (unsigned int)value); |
274 | 40b6f911 | Peter Chubb | imx_update(s); |
275 | 40b6f911 | Peter Chubb | break;
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276 | 40b6f911 | Peter Chubb | |
277 | 40b6f911 | Peter Chubb | case 0x21: /* UCR2 */ |
278 | 40b6f911 | Peter Chubb | /*
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279 | 40b6f911 | Peter Chubb | * Only a few bits in control register 2 are implemented as yet.
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280 | 40b6f911 | Peter Chubb | * If it's intended to use a real serial device as a back-end, this
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281 | 40b6f911 | Peter Chubb | * register will have to be implemented more fully.
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282 | 40b6f911 | Peter Chubb | */
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283 | 40b6f911 | Peter Chubb | if (!(value & UCR2_SRST)) {
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284 | 40b6f911 | Peter Chubb | imx_serial_reset(s); |
285 | 40b6f911 | Peter Chubb | imx_update(s); |
286 | 40b6f911 | Peter Chubb | value |= UCR2_SRST; |
287 | 40b6f911 | Peter Chubb | } |
288 | 40b6f911 | Peter Chubb | if (value & UCR2_RXEN) {
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289 | 40b6f911 | Peter Chubb | if (!(s->ucr2 & UCR2_RXEN)) {
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290 | 40b6f911 | Peter Chubb | qemu_chr_accept_input(s->chr); |
291 | 40b6f911 | Peter Chubb | } |
292 | 40b6f911 | Peter Chubb | } |
293 | 40b6f911 | Peter Chubb | s->ucr2 = value & 0xffff;
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294 | 40b6f911 | Peter Chubb | break;
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295 | 40b6f911 | Peter Chubb | |
296 | 40b6f911 | Peter Chubb | case 0x25: /* USR1 */ |
297 | 40b6f911 | Peter Chubb | value &= USR1_AWAKE | USR1_AIRINT | USR1_DTRD | USR1_AGTIM | |
298 | 40b6f911 | Peter Chubb | USR1_FRAMERR | USR1_ESCF | USR1_RTSD | USR1_PARTYER; |
299 | 40b6f911 | Peter Chubb | s->usr1 &= ~value; |
300 | 40b6f911 | Peter Chubb | break;
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301 | 40b6f911 | Peter Chubb | |
302 | 40b6f911 | Peter Chubb | case 0x26: /* USR2 */ |
303 | 40b6f911 | Peter Chubb | /*
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304 | 40b6f911 | Peter Chubb | * Writing 1 to some bits clears them; all other
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305 | 40b6f911 | Peter Chubb | * values are ignored
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306 | 40b6f911 | Peter Chubb | */
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307 | 40b6f911 | Peter Chubb | value &= USR2_ADET | USR2_DTRF | USR2_IDLE | USR2_ACST | |
308 | 40b6f911 | Peter Chubb | USR2_RIDELT | USR2_IRINT | USR2_WAKE | |
309 | 40b6f911 | Peter Chubb | USR2_DCDDELT | USR2_RTSF | USR2_BRCD | USR2_ORE; |
310 | 40b6f911 | Peter Chubb | s->usr2 &= ~value; |
311 | 40b6f911 | Peter Chubb | break;
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312 | 40b6f911 | Peter Chubb | |
313 | 40b6f911 | Peter Chubb | /*
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314 | 40b6f911 | Peter Chubb | * Linux expects to see what it writes to these registers
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315 | 40b6f911 | Peter Chubb | * We don't currently alter the baud rate
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316 | 40b6f911 | Peter Chubb | */
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317 | 40b6f911 | Peter Chubb | case 0x29: /* UBIR */ |
318 | 40b6f911 | Peter Chubb | s->ubrc = value & 0xffff;
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319 | 40b6f911 | Peter Chubb | break;
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320 | 40b6f911 | Peter Chubb | |
321 | 40b6f911 | Peter Chubb | case 0x2a: /* UBMR */ |
322 | 40b6f911 | Peter Chubb | s->ubmr = value & 0xffff;
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323 | 40b6f911 | Peter Chubb | break;
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324 | 40b6f911 | Peter Chubb | |
325 | 40b6f911 | Peter Chubb | case 0x2c: /* One ms reg */ |
326 | 40b6f911 | Peter Chubb | s->onems = value & 0xffff;
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327 | 40b6f911 | Peter Chubb | break;
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328 | 40b6f911 | Peter Chubb | |
329 | 40b6f911 | Peter Chubb | case 0x24: /* FIFO control register */ |
330 | 40b6f911 | Peter Chubb | s->ufcr = value & 0xffff;
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331 | 40b6f911 | Peter Chubb | break;
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332 | 40b6f911 | Peter Chubb | |
333 | 40b6f911 | Peter Chubb | case 0x22: /* UCR3 */ |
334 | 40b6f911 | Peter Chubb | s->ucr3 = value & 0xffff;
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335 | 40b6f911 | Peter Chubb | break;
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336 | 40b6f911 | Peter Chubb | |
337 | 40b6f911 | Peter Chubb | case 0x2d: /* UTS1 */ |
338 | 40b6f911 | Peter Chubb | case 0x23: /* UCR4 */ |
339 | 40b6f911 | Peter Chubb | IPRINTF("Unimplemented Register %x written to\n", offset >> 2); |
340 | 40b6f911 | Peter Chubb | /* TODO */
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341 | 40b6f911 | Peter Chubb | break;
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342 | 40b6f911 | Peter Chubb | |
343 | 40b6f911 | Peter Chubb | default:
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344 | 40b6f911 | Peter Chubb | IPRINTF("imx_serial_write: Bad offset 0x%x\n", (int)offset); |
345 | 40b6f911 | Peter Chubb | } |
346 | 40b6f911 | Peter Chubb | } |
347 | 40b6f911 | Peter Chubb | |
348 | 40b6f911 | Peter Chubb | static int imx_can_receive(void *opaque) |
349 | 40b6f911 | Peter Chubb | { |
350 | 40b6f911 | Peter Chubb | IMXSerialState *s = (IMXSerialState *)opaque; |
351 | 40b6f911 | Peter Chubb | return !(s->usr1 & USR1_RRDY);
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352 | 40b6f911 | Peter Chubb | } |
353 | 40b6f911 | Peter Chubb | |
354 | 40b6f911 | Peter Chubb | static void imx_put_data(void *opaque, uint32_t value) |
355 | 40b6f911 | Peter Chubb | { |
356 | 40b6f911 | Peter Chubb | IMXSerialState *s = (IMXSerialState *)opaque; |
357 | 40b6f911 | Peter Chubb | DPRINTF("received char\n");
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358 | 40b6f911 | Peter Chubb | s->usr1 |= USR1_RRDY; |
359 | 40b6f911 | Peter Chubb | s->usr2 |= USR2_RDR; |
360 | 40b6f911 | Peter Chubb | s->uts1 &= ~UTS1_RXEMPTY; |
361 | 40b6f911 | Peter Chubb | s->readbuff = value; |
362 | 40b6f911 | Peter Chubb | imx_update(s); |
363 | 40b6f911 | Peter Chubb | } |
364 | 40b6f911 | Peter Chubb | |
365 | 40b6f911 | Peter Chubb | static void imx_receive(void *opaque, const uint8_t *buf, int size) |
366 | 40b6f911 | Peter Chubb | { |
367 | 40b6f911 | Peter Chubb | imx_put_data(opaque, *buf); |
368 | 40b6f911 | Peter Chubb | } |
369 | 40b6f911 | Peter Chubb | |
370 | 40b6f911 | Peter Chubb | static void imx_event(void *opaque, int event) |
371 | 40b6f911 | Peter Chubb | { |
372 | 40b6f911 | Peter Chubb | if (event == CHR_EVENT_BREAK) {
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373 | 40b6f911 | Peter Chubb | imx_put_data(opaque, URXD_BRK); |
374 | 40b6f911 | Peter Chubb | } |
375 | 40b6f911 | Peter Chubb | } |
376 | 40b6f911 | Peter Chubb | |
377 | 40b6f911 | Peter Chubb | |
378 | 40b6f911 | Peter Chubb | static const struct MemoryRegionOps imx_serial_ops = { |
379 | 40b6f911 | Peter Chubb | .read = imx_serial_read, |
380 | 40b6f911 | Peter Chubb | .write = imx_serial_write, |
381 | 40b6f911 | Peter Chubb | .endianness = DEVICE_NATIVE_ENDIAN, |
382 | 40b6f911 | Peter Chubb | }; |
383 | 40b6f911 | Peter Chubb | |
384 | 40b6f911 | Peter Chubb | static int imx_serial_init(SysBusDevice *dev) |
385 | 40b6f911 | Peter Chubb | { |
386 | 40b6f911 | Peter Chubb | IMXSerialState *s = FROM_SYSBUS(IMXSerialState, dev); |
387 | 40b6f911 | Peter Chubb | |
388 | 40b6f911 | Peter Chubb | |
389 | 300b1fc6 | Paolo Bonzini | memory_region_init_io(&s->iomem, OBJECT(s), &imx_serial_ops, s, |
390 | 300b1fc6 | Paolo Bonzini | "imx-serial", 0x1000); |
391 | 40b6f911 | Peter Chubb | sysbus_init_mmio(dev, &s->iomem); |
392 | 40b6f911 | Peter Chubb | sysbus_init_irq(dev, &s->irq); |
393 | 40b6f911 | Peter Chubb | |
394 | 40b6f911 | Peter Chubb | if (s->chr) {
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395 | 40b6f911 | Peter Chubb | qemu_chr_add_handlers(s->chr, imx_can_receive, imx_receive, |
396 | 40b6f911 | Peter Chubb | imx_event, s); |
397 | 40b6f911 | Peter Chubb | } else {
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398 | 40b6f911 | Peter Chubb | DPRINTF("No char dev for uart at 0x%lx\n",
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399 | 40b6f911 | Peter Chubb | (unsigned long)s->iomem.ram_addr); |
400 | 40b6f911 | Peter Chubb | } |
401 | 40b6f911 | Peter Chubb | |
402 | 40b6f911 | Peter Chubb | return 0; |
403 | 40b6f911 | Peter Chubb | } |
404 | 40b6f911 | Peter Chubb | |
405 | a8170e5e | Avi Kivity | void imx_serial_create(int uart, const hwaddr addr, qemu_irq irq) |
406 | 40b6f911 | Peter Chubb | { |
407 | 40b6f911 | Peter Chubb | DeviceState *dev; |
408 | 40b6f911 | Peter Chubb | SysBusDevice *bus; |
409 | 40b6f911 | Peter Chubb | CharDriverState *chr; |
410 | 40b6f911 | Peter Chubb | const char chr_name[] = "serial"; |
411 | 40b6f911 | Peter Chubb | char label[ARRAY_SIZE(chr_name) + 1]; |
412 | 40b6f911 | Peter Chubb | |
413 | 40b6f911 | Peter Chubb | dev = qdev_create(NULL, "imx-serial"); |
414 | 40b6f911 | Peter Chubb | |
415 | 40b6f911 | Peter Chubb | if (uart >= MAX_SERIAL_PORTS) {
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416 | 40b6f911 | Peter Chubb | hw_error("Cannot assign uart %d: QEMU supports only %d ports\n",
|
417 | 40b6f911 | Peter Chubb | uart, MAX_SERIAL_PORTS); |
418 | 40b6f911 | Peter Chubb | } |
419 | 40b6f911 | Peter Chubb | chr = serial_hds[uart]; |
420 | 40b6f911 | Peter Chubb | if (!chr) {
|
421 | 40b6f911 | Peter Chubb | snprintf(label, ARRAY_SIZE(label), "%s%d", chr_name, uart);
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422 | 40b6f911 | Peter Chubb | chr = qemu_chr_new(label, "null", NULL); |
423 | 40b6f911 | Peter Chubb | if (!(chr)) {
|
424 | 40b6f911 | Peter Chubb | hw_error("Can't assign serial port to imx-uart%d.\n", uart);
|
425 | 40b6f911 | Peter Chubb | } |
426 | 40b6f911 | Peter Chubb | } |
427 | 40b6f911 | Peter Chubb | |
428 | 40b6f911 | Peter Chubb | qdev_prop_set_chr(dev, "chardev", chr);
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429 | 1356b98d | Andreas Färber | bus = SYS_BUS_DEVICE(dev); |
430 | 40b6f911 | Peter Chubb | qdev_init_nofail(dev); |
431 | a8170e5e | Avi Kivity | if (addr != (hwaddr)-1) { |
432 | 40b6f911 | Peter Chubb | sysbus_mmio_map(bus, 0, addr);
|
433 | 40b6f911 | Peter Chubb | } |
434 | 40b6f911 | Peter Chubb | sysbus_connect_irq(bus, 0, irq);
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435 | 40b6f911 | Peter Chubb | |
436 | 40b6f911 | Peter Chubb | } |
437 | 40b6f911 | Peter Chubb | |
438 | 40b6f911 | Peter Chubb | |
439 | 40b6f911 | Peter Chubb | static Property imx32_serial_properties[] = {
|
440 | 40b6f911 | Peter Chubb | DEFINE_PROP_CHR("chardev", IMXSerialState, chr),
|
441 | 40b6f911 | Peter Chubb | DEFINE_PROP_END_OF_LIST(), |
442 | 40b6f911 | Peter Chubb | }; |
443 | 40b6f911 | Peter Chubb | |
444 | 40b6f911 | Peter Chubb | static void imx_serial_class_init(ObjectClass *klass, void *data) |
445 | 40b6f911 | Peter Chubb | { |
446 | 40b6f911 | Peter Chubb | DeviceClass *dc = DEVICE_CLASS(klass); |
447 | 40b6f911 | Peter Chubb | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
448 | 40b6f911 | Peter Chubb | |
449 | 40b6f911 | Peter Chubb | k->init = imx_serial_init; |
450 | 40b6f911 | Peter Chubb | dc->vmsd = &vmstate_imx_serial; |
451 | 40b6f911 | Peter Chubb | dc->reset = imx_serial_reset_at_boot; |
452 | 40b6f911 | Peter Chubb | dc->desc = "i.MX series UART";
|
453 | 40b6f911 | Peter Chubb | dc->props = imx32_serial_properties; |
454 | 40b6f911 | Peter Chubb | } |
455 | 40b6f911 | Peter Chubb | |
456 | 8c43a6f0 | Andreas Färber | static const TypeInfo imx_serial_info = { |
457 | 40b6f911 | Peter Chubb | .name = "imx-serial",
|
458 | 40b6f911 | Peter Chubb | .parent = TYPE_SYS_BUS_DEVICE, |
459 | 40b6f911 | Peter Chubb | .instance_size = sizeof(IMXSerialState),
|
460 | 40b6f911 | Peter Chubb | .class_init = imx_serial_class_init, |
461 | 40b6f911 | Peter Chubb | }; |
462 | 40b6f911 | Peter Chubb | |
463 | 40b6f911 | Peter Chubb | static void imx_serial_register_types(void) |
464 | 40b6f911 | Peter Chubb | { |
465 | 40b6f911 | Peter Chubb | type_register_static(&imx_serial_info); |
466 | 40b6f911 | Peter Chubb | } |
467 | 40b6f911 | Peter Chubb | |
468 | 40b6f911 | Peter Chubb | type_init(imx_serial_register_types) |