root / hw / char / imx_serial.c @ db1b58e9
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/*
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* IMX31 UARTS
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*
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* Copyright (c) 2008 OKL
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* Originally Written by Hans Jiang
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* Copyright (c) 2011 NICTA Pty Ltd.
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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* This is a `bare-bones' implementation of the IMX series serial ports.
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* TODO:
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* -- implement FIFOs. The real hardware has 32 word transmit
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* and receive FIFOs; we currently use a 1-char buffer
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* -- implement DMA
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* -- implement BAUD-rate and modem lines, for when the backend
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* is a real serial device.
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*/
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#include "hw/hw.h" |
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#include "hw/sysbus.h" |
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#include "sysemu/sysemu.h" |
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#include "sysemu/char.h" |
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#include "hw/arm/imx.h" |
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//#define DEBUG_SERIAL 1
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#ifdef DEBUG_SERIAL
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#define DPRINTF(fmt, args...) \
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do { printf("imx_serial: " fmt , ##args); } while (0) |
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#else
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#define DPRINTF(fmt, args...) do {} while (0) |
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#endif
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/*
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* Define to 1 for messages about attempts to
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* access unimplemented registers or similar.
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*/
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//#define DEBUG_IMPLEMENTATION 1
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#ifdef DEBUG_IMPLEMENTATION
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# define IPRINTF(fmt, args...) \
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do { fprintf(stderr, "imx_serial: " fmt, ##args); } while (0) |
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#else
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# define IPRINTF(fmt, args...) do {} while (0) |
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#endif
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typedef struct { |
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SysBusDevice busdev; |
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MemoryRegion iomem; |
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int32_t readbuff; |
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uint32_t usr1; |
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uint32_t usr2; |
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uint32_t ucr1; |
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uint32_t ucr2; |
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uint32_t uts1; |
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/*
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* The registers below are implemented just so that the
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* guest OS sees what it has written
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*/
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uint32_t onems; |
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uint32_t ufcr; |
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uint32_t ubmr; |
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uint32_t ubrc; |
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uint32_t ucr3; |
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qemu_irq irq; |
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CharDriverState *chr; |
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} IMXSerialState; |
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static const VMStateDescription vmstate_imx_serial = { |
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.name = "imx-serial",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) { |
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VMSTATE_INT32(readbuff, IMXSerialState), |
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VMSTATE_UINT32(usr1, IMXSerialState), |
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VMSTATE_UINT32(usr2, IMXSerialState), |
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VMSTATE_UINT32(ucr1, IMXSerialState), |
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VMSTATE_UINT32(uts1, IMXSerialState), |
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VMSTATE_UINT32(onems, IMXSerialState), |
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VMSTATE_UINT32(ufcr, IMXSerialState), |
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VMSTATE_UINT32(ubmr, IMXSerialState), |
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VMSTATE_UINT32(ubrc, IMXSerialState), |
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VMSTATE_UINT32(ucr3, IMXSerialState), |
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VMSTATE_END_OF_LIST() |
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}, |
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}; |
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#define URXD_CHARRDY (1<<15) /* character read is valid */ |
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#define URXD_ERR (1<<14) /* Character has error */ |
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#define URXD_BRK (1<<11) /* Break received */ |
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#define USR1_PARTYER (1<<15) /* Parity Error */ |
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#define USR1_RTSS (1<<14) /* RTS pin status */ |
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#define USR1_TRDY (1<<13) /* Tx ready */ |
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#define USR1_RTSD (1<<12) /* RTS delta: pin changed state */ |
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#define USR1_ESCF (1<<11) /* Escape sequence interrupt */ |
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#define USR1_FRAMERR (1<<10) /* Framing error */ |
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#define USR1_RRDY (1<<9) /* receiver ready */ |
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#define USR1_AGTIM (1<<8) /* Aging timer interrupt */ |
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#define USR1_DTRD (1<<7) /* DTR changed */ |
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#define USR1_RXDS (1<<6) /* Receiver is idle */ |
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#define USR1_AIRINT (1<<5) /* Aysnch IR interrupt */ |
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#define USR1_AWAKE (1<<4) /* Falling edge detected on RXd pin */ |
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#define USR2_ADET (1<<15) /* Autobaud complete */ |
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#define USR2_TXFE (1<<14) /* Transmit FIFO empty */ |
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#define USR2_DTRF (1<<13) /* DTR/DSR transition */ |
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#define USR2_IDLE (1<<12) /* UART has been idle for too long */ |
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#define USR2_ACST (1<<11) /* Autobaud counter stopped */ |
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#define USR2_RIDELT (1<<10) /* Ring Indicator delta */ |
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#define USR2_RIIN (1<<9) /* Ring Indicator Input */ |
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#define USR2_IRINT (1<<8) /* Serial Infrared Interrupt */ |
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#define USR2_WAKE (1<<7) /* Start bit detected */ |
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#define USR2_DCDDELT (1<<6) /* Data Carrier Detect delta */ |
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#define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */ |
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#define USR2_RTSF (1<<4) /* RTS transition */ |
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#define USR2_TXDC (1<<3) /* Transmission complete */ |
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#define USR2_BRCD (1<<2) /* Break condition detected */ |
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#define USR2_ORE (1<<1) /* Overrun error */ |
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#define USR2_RDR (1<<0) /* Receive data ready */ |
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|
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#define UCR1_TRDYEN (1<<13) /* Tx Ready Interrupt Enable */ |
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#define UCR1_RRDYEN (1<<9) /* Rx Ready Interrupt Enable */ |
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#define UCR1_TXMPTYEN (1<<6) /* Tx Empty Interrupt Enable */ |
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#define UCR1_UARTEN (1<<0) /* UART Enable */ |
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#define UCR2_TXEN (1<<2) /* Transmitter enable */ |
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#define UCR2_RXEN (1<<1) /* Receiver enable */ |
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#define UCR2_SRST (1<<0) /* Reset complete */ |
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#define UTS1_TXEMPTY (1<<6) |
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#define UTS1_RXEMPTY (1<<5) |
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#define UTS1_TXFULL (1<<4) |
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#define UTS1_RXFULL (1<<3) |
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static void imx_update(IMXSerialState *s) |
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{ |
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uint32_t flags; |
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flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY); |
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if (!(s->ucr1 & UCR1_TXMPTYEN)) {
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flags &= ~USR1_TRDY; |
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} |
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qemu_set_irq(s->irq, !!flags); |
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} |
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static void imx_serial_reset(IMXSerialState *s) |
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{ |
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s->usr1 = USR1_TRDY | USR1_RXDS; |
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/*
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* Fake attachment of a terminal: assert RTS.
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*/
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s->usr1 |= USR1_RTSS; |
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s->usr2 = USR2_TXFE | USR2_TXDC | USR2_DCDIN; |
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s->uts1 = UTS1_RXEMPTY | UTS1_TXEMPTY; |
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s->ucr1 = 0;
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s->ucr2 = UCR2_SRST; |
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s->ucr3 = 0x700;
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s->ubmr = 0;
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s->ubrc = 4;
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s->readbuff = URXD_ERR; |
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} |
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static void imx_serial_reset_at_boot(DeviceState *dev) |
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{ |
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IMXSerialState *s = container_of(dev, IMXSerialState, busdev.qdev); |
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imx_serial_reset(s); |
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/*
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* enable the uart on boot, so messages from the linux decompresser
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* are visible. On real hardware this is done by the boot rom
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* before anything else is loaded.
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*/
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s->ucr1 = UCR1_UARTEN; |
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s->ucr2 = UCR2_TXEN; |
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} |
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static uint64_t imx_serial_read(void *opaque, hwaddr offset, |
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unsigned size)
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{ |
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IMXSerialState *s = (IMXSerialState *)opaque; |
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uint32_t c; |
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DPRINTF("read(offset=%x)\n", offset >> 2); |
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switch (offset >> 2) { |
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case 0x0: /* URXD */ |
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c = s->readbuff; |
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if (!(s->uts1 & UTS1_RXEMPTY)) {
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/* Character is valid */
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c |= URXD_CHARRDY; |
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s->usr1 &= ~USR1_RRDY; |
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s->usr2 &= ~USR2_RDR; |
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s->uts1 |= UTS1_RXEMPTY; |
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imx_update(s); |
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qemu_chr_accept_input(s->chr); |
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} |
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return c;
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case 0x20: /* UCR1 */ |
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return s->ucr1;
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case 0x21: /* UCR2 */ |
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return s->ucr2;
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case 0x25: /* USR1 */ |
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return s->usr1;
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case 0x26: /* USR2 */ |
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return s->usr2;
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case 0x2A: /* BRM Modulator */ |
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return s->ubmr;
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case 0x2B: /* Baud Rate Count */ |
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return s->ubrc;
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case 0x2d: /* Test register */ |
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return s->uts1;
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case 0x24: /* UFCR */ |
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return s->ufcr;
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case 0x2c: |
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return s->onems;
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case 0x22: /* UCR3 */ |
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return s->ucr3;
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case 0x23: /* UCR4 */ |
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case 0x29: /* BRM Incremental */ |
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return 0x0; /* TODO */ |
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default:
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IPRINTF("imx_serial_read: bad offset: 0x%x\n", (int)offset); |
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return 0; |
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} |
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} |
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static void imx_serial_write(void *opaque, hwaddr offset, |
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uint64_t value, unsigned size)
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{ |
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IMXSerialState *s = (IMXSerialState *)opaque; |
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unsigned char ch; |
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DPRINTF("write(offset=%x, value = %x) to %s\n",
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offset >> 2,
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(unsigned int)value, s->chr ? s->chr->label : "NODEV"); |
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switch (offset >> 2) { |
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case 0x10: /* UTXD */ |
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ch = value; |
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if (s->ucr2 & UCR2_TXEN) {
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if (s->chr) {
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qemu_chr_fe_write(s->chr, &ch, 1);
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} |
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s->usr1 &= ~USR1_TRDY; |
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imx_update(s); |
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s->usr1 |= USR1_TRDY; |
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imx_update(s); |
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} |
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break;
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case 0x20: /* UCR1 */ |
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s->ucr1 = value & 0xffff;
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DPRINTF("write(ucr1=%x)\n", (unsigned int)value); |
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imx_update(s); |
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break;
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case 0x21: /* UCR2 */ |
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/*
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* Only a few bits in control register 2 are implemented as yet.
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* If it's intended to use a real serial device as a back-end, this
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* register will have to be implemented more fully.
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*/
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if (!(value & UCR2_SRST)) {
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imx_serial_reset(s); |
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imx_update(s); |
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value |= UCR2_SRST; |
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} |
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if (value & UCR2_RXEN) {
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if (!(s->ucr2 & UCR2_RXEN)) {
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qemu_chr_accept_input(s->chr); |
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} |
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} |
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s->ucr2 = value & 0xffff;
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break;
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case 0x25: /* USR1 */ |
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value &= USR1_AWAKE | USR1_AIRINT | USR1_DTRD | USR1_AGTIM | |
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USR1_FRAMERR | USR1_ESCF | USR1_RTSD | USR1_PARTYER; |
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s->usr1 &= ~value; |
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break;
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case 0x26: /* USR2 */ |
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/*
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* Writing 1 to some bits clears them; all other
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* values are ignored
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*/
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value &= USR2_ADET | USR2_DTRF | USR2_IDLE | USR2_ACST | |
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USR2_RIDELT | USR2_IRINT | USR2_WAKE | |
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USR2_DCDDELT | USR2_RTSF | USR2_BRCD | USR2_ORE; |
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s->usr2 &= ~value; |
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break;
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/*
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* Linux expects to see what it writes to these registers
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* We don't currently alter the baud rate
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*/
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case 0x29: /* UBIR */ |
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s->ubrc = value & 0xffff;
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break;
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case 0x2a: /* UBMR */ |
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s->ubmr = value & 0xffff;
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break;
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case 0x2c: /* One ms reg */ |
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s->onems = value & 0xffff;
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break;
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case 0x24: /* FIFO control register */ |
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s->ufcr = value & 0xffff;
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break;
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case 0x22: /* UCR3 */ |
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s->ucr3 = value & 0xffff;
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break;
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case 0x2d: /* UTS1 */ |
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case 0x23: /* UCR4 */ |
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IPRINTF("Unimplemented Register %x written to\n", offset >> 2); |
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/* TODO */
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break;
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default:
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IPRINTF("imx_serial_write: Bad offset 0x%x\n", (int)offset); |
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} |
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} |
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static int imx_can_receive(void *opaque) |
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{ |
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IMXSerialState *s = (IMXSerialState *)opaque; |
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return !(s->usr1 & USR1_RRDY);
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} |
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static void imx_put_data(void *opaque, uint32_t value) |
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{ |
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IMXSerialState *s = (IMXSerialState *)opaque; |
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DPRINTF("received char\n");
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s->usr1 |= USR1_RRDY; |
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s->usr2 |= USR2_RDR; |
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s->uts1 &= ~UTS1_RXEMPTY; |
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s->readbuff = value; |
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imx_update(s); |
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} |
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|
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static void imx_receive(void *opaque, const uint8_t *buf, int size) |
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{ |
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imx_put_data(opaque, *buf); |
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} |
369 |
|
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static void imx_event(void *opaque, int event) |
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{ |
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if (event == CHR_EVENT_BREAK) {
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imx_put_data(opaque, URXD_BRK); |
374 |
} |
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} |
376 |
|
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static const struct MemoryRegionOps imx_serial_ops = { |
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.read = imx_serial_read, |
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.write = imx_serial_write, |
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.endianness = DEVICE_NATIVE_ENDIAN, |
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}; |
383 |
|
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static int imx_serial_init(SysBusDevice *dev) |
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{ |
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IMXSerialState *s = FROM_SYSBUS(IMXSerialState, dev); |
387 |
|
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|
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memory_region_init_io(&s->iomem, OBJECT(s), &imx_serial_ops, s, |
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"imx-serial", 0x1000); |
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sysbus_init_mmio(dev, &s->iomem); |
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sysbus_init_irq(dev, &s->irq); |
393 |
|
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if (s->chr) {
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qemu_chr_add_handlers(s->chr, imx_can_receive, imx_receive, |
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imx_event, s); |
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} else {
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DPRINTF("No char dev for uart at 0x%lx\n",
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(unsigned long)s->iomem.ram_addr); |
400 |
} |
401 |
|
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return 0; |
403 |
} |
404 |
|
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void imx_serial_create(int uart, const hwaddr addr, qemu_irq irq) |
406 |
{ |
407 |
DeviceState *dev; |
408 |
SysBusDevice *bus; |
409 |
CharDriverState *chr; |
410 |
const char chr_name[] = "serial"; |
411 |
char label[ARRAY_SIZE(chr_name) + 1]; |
412 |
|
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dev = qdev_create(NULL, "imx-serial"); |
414 |
|
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if (uart >= MAX_SERIAL_PORTS) {
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hw_error("Cannot assign uart %d: QEMU supports only %d ports\n",
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uart, MAX_SERIAL_PORTS); |
418 |
} |
419 |
chr = serial_hds[uart]; |
420 |
if (!chr) {
|
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snprintf(label, ARRAY_SIZE(label), "%s%d", chr_name, uart);
|
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chr = qemu_chr_new(label, "null", NULL); |
423 |
if (!(chr)) {
|
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hw_error("Can't assign serial port to imx-uart%d.\n", uart);
|
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} |
426 |
} |
427 |
|
428 |
qdev_prop_set_chr(dev, "chardev", chr);
|
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bus = SYS_BUS_DEVICE(dev); |
430 |
qdev_init_nofail(dev); |
431 |
if (addr != (hwaddr)-1) { |
432 |
sysbus_mmio_map(bus, 0, addr);
|
433 |
} |
434 |
sysbus_connect_irq(bus, 0, irq);
|
435 |
|
436 |
} |
437 |
|
438 |
|
439 |
static Property imx32_serial_properties[] = {
|
440 |
DEFINE_PROP_CHR("chardev", IMXSerialState, chr),
|
441 |
DEFINE_PROP_END_OF_LIST(), |
442 |
}; |
443 |
|
444 |
static void imx_serial_class_init(ObjectClass *klass, void *data) |
445 |
{ |
446 |
DeviceClass *dc = DEVICE_CLASS(klass); |
447 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
448 |
|
449 |
k->init = imx_serial_init; |
450 |
dc->vmsd = &vmstate_imx_serial; |
451 |
dc->reset = imx_serial_reset_at_boot; |
452 |
dc->desc = "i.MX series UART";
|
453 |
dc->props = imx32_serial_properties; |
454 |
} |
455 |
|
456 |
static const TypeInfo imx_serial_info = { |
457 |
.name = "imx-serial",
|
458 |
.parent = TYPE_SYS_BUS_DEVICE, |
459 |
.instance_size = sizeof(IMXSerialState),
|
460 |
.class_init = imx_serial_class_init, |
461 |
}; |
462 |
|
463 |
static void imx_serial_register_types(void) |
464 |
{ |
465 |
type_register_static(&imx_serial_info); |
466 |
} |
467 |
|
468 |
type_init(imx_serial_register_types) |