block: remove keep_read_only flag from BlockDriverState struct
The keep_read_only flag is no longer used, in favor of the bdrvflag BDRV_O_ALLOW_RDWR.
Signed-off-by: Jeff Cody <jcody@redhat.com>Signed-off-by: Kevin Wolf <kwolf@redhat.com>
block: purge s->aligned_buf and s->aligned_buf_size from raw-posix.c
The aligned_buf pointer and aligned_buf size are no longer used inraw_posix.c, so remove all references to them.
block: raw-posix image file reopen
This is derived from the Supriya Kannery's reopen patches.
This contains the raw-posix driver changes for the bdrv_reopen_*functions. All changes are staged into a temporary scratch bufferduring the prepare() stage, and copied over to the live structure...
block: raw image file reopen
These are the stubs for the file reopen drivers for the raw format.
There is currently nothing that needs to be done by the raw driverin reopen.
block: qed image file reopen
These are the stubs for the file reopen drivers for the qed format.
There is currently nothing that needs to be done by the qed driverin reopen.
block: qcow2 image file reopen
These are the stubs for the file reopen drivers for the qcow2 format.
There is currently nothing that needs to be done by the qcow2 driverin reopen.
block: qcow image file reopen
These are the stubs for the file reopen drivers for the qcow format.
There is currently nothing that needs to be done by the qcow driverin reopen.
block: vmdk image file reopen
This patch supports reopen for VMDK image files. VMDK extents are addedto the existing reopen queue, so that the transactional model of reopenis maintained with multiple image files.
Signed-off-by: Jeff Cody <jcody@redhat.com>...
block: vdi image file reopen
There is currently nothing that needs to be done for VDI reopen.
block: vpc image file reopen
There is currently nothing that needs to be done for VPC imagefile reopen.
block: convert bdrv_commit() to use bdrv_reopen()
Currently, bdrv_commit() reopens images r/w itself, via risky_delete() and _open() calls. Use the new safe method for drive reopen.
blockdev: preserve readonly and snapshot states across media changes
If readonly=on is given at device creation time, the ->readonly flagneeds to be set in the block driver state for this device so thatreadonly-ness is preserved across media changes (qmp change command)....
block: correctly set the keep_read_only flag
I believe the bs->keep_read_only flag is supposed to reflectthe initial open state of the device. If the device is initiallyopened R/O, then commit operations, or reopen operations changingto R/W, are prohibited....
block: make bdrv_set_enable_write_cache() modify open_flags
bdrv_set_enable_write_cache() sets the bs->enable_write_cache flag,but without the flag recorded in bs->open_flags, then next timea reopen() is performed the enable_write_cache setting may beinadvertently lost....
block: Framework for reopening files safely
This is based on Supriya Kannery's bdrv_reopen() patch series.
This provides a transactional method to reopen multipleimages files safely.
Image files are queue for reopen via bdrv_reopen_queue(), and thereopen occurs when bdrv_reopen_multiple() is called. Changes are...
block: move aio initialization into a helper function
Move AIO initialization for raw-posix block driver into a helper function.
In addition to just code motion, the aio_ctx pointer is checked for NULL,prior to calling laio_init(), to make sure laio_init() is only run once....
block: move open flag parsing in raw block drivers to helper functions
Code motion, to move parsing of open flags into a helper function.
block: do not parse BDRV_O_CACHE_WB in block drivers
Block drivers should ignore BDRV_O_CACHE_WB in .bdrv_open flags,and in the bs->open_flags.
This patch removes the code, leaving the behaviour behind as ifBDRV_O_CACHE_WB was set.
block: use BDRV_O_NOCACHE instead of s->aligned_buf in raw-posix.c
Rather than check for a non-NULL aligned_buf to determine ifraw_aio_submit needs to check for alignment, check for the presenceof BDRV_O_NOCACHE in the bs->open_flags.
w32: Add implementation of gmtime_r, localtime_r
Those functions are missing in MinGW.
Some versions of MinGW-w64 include defines for gmtime_r and localtime_r.Older versions of these macros are buggy (they return a pointer to astatic variable), therefore we don't want them. Newer versions are...
audio: Fix warning from static code analysis
smatch report:audio/audio_template.h:416 AUD_open_out(18) warn: variable dereferenced before check 'as' (see line 414)
Moving the ldebug statement after the statement which checks 'as'fixes that warning.
Signed-off-by: Stefan Weil <sw@weilnetz.de>...
Merge branch 'tcg-sparc' of git://repo.or.cz/qemu/rth
target-xtensa: implement FP1 group
These are comparison and conditional move opcodes.See ISA, 4.3.10 for more details.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-xtensa: implement coprocessor context option
In case Coprocessor Context option is enabled CPENABLE SR bits controlwhether access to coprocessors is allowed or would rise one ofCoprocessorXDisabled exceptions.
See ISA, 4.4.5 for more details.
FP is coprocessor 0....
softfloat: make float_muladd_negate_* flags independent
Flags passed into float{32,64}_muladd are treated as bits; assignindependent bits to float_muladd_negate_* to allow precise control overwhat gets negated in float{32,64}_muladd.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>...
softfloat: add NO_SIGNALING_NANS
Architectures that don't have signaling NaNs can defineNO_SIGNALING_NANS, it will make float*_is_quiet_nan return 1 for any NaNand float*_is_signaling_nan always return 0.
target-xtensa: handle boolean option in overlays
target-xtensa: specialize softfloat NaN rules
NaN propagation rule: leftmost NaN in the expression gets propagated tothe result.
target-xtensa: add FP registers
There are 16 32-bit FP registers (f0 - f15), control and status userregisters (fcr, fsr).
See ISA, 4.3.10 for more details.
target-xtensa: implement LSCX and LSCI groups
These are load/store instructions for FP registers with immediate orregister index and optional base post-update.See ISA, 4.3.10 for more details.
target-xtensa: implement FP0 arithmetic
These are FP arithmetic opcodes.See ISA, 4.3.10 for more details.
target-xtensa: implement FP0 conversions
These are FP to integer and integer to FP conversion opcodes.See ISA, 4.3.10 for more details.
Note that ISA description for utrunc.s is currently incorrect and willbe fixed in future revisions.
Revert "tcg/mips"
This reverts commit ad49d1f75115663731bfe06dec61eed6775526ad.
This commit was not supposed to be pushed.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg/ppc32: Implement movcond32
Thanks to Richard Henderson
Signed-off-by: malc <av1474@comtv.ru>
tcg/mips
tcg/i386: Add shortcuts for registers used in L constraint
While 64 bit hosts use the first three registers which are also usedas function input parameters, 32 bit hosts use TCG_REG_EAX andTCG_REG_EDX which are not used in parameter passing.
After defining new register macros for the registers used in L...
tcg/i386: Remove unused registers from tcg_target_call_iarg_regs
32 bit x86 hosts don't need registers for helper function argumentsbecause they use the default stack based calling convention.
Removing the registers allows simpler code for functiontcg_target_get_call_iarg_regs_count....
tcg: Remove tcg_target_get_call_iarg_regs_count
The TCG targets no longer need individual implementations.
Since commit 6a18ae2d2947532d5c26439548afa0481c4529f9,'flags' is no longer used in tcg_target_get_call_iarg_regs_count.
The remaining tcg_target_get_call_iarg_regs_count is trivial and only...
tcg-hppa: Implement movcond
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg/README: document tcg_gen_goto_tb restrictions
Seehttp://lists.nongnu.org/archive/html/qemu-devel/2012-09/msg03196.htmlfor the whole story.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
w64: Fix TCG helper functions with 5 arguments
TCG uses 6 registers for function arguments on 64 bit Linux hosts,but only 4 registers on W64 hosts.
Commit 2999a0b20074a7e4a58f56572bb1436749368f59 increased the numberof arguments for some important helper functions from 4 to 5...
tcg/optimize: rework copy progagation
The copy propagation pass tries to keep track what is a copy of whatand what has copy of what, and in addition it keep a circular list ofof all the copies. Unfortunately this doesn't fully work: a mov froma temp which has a state "COPY" changed it into a state "HAS_COPY"....
tcg/optimize: do copy propagation for all operations
It is possible to due copy propagation for all operations, even the onethat have side effects or clobber arguments (it only concerns inputarguments). That said, the call operation should be handled differently...
tcg/optimize: optimize "op r, a, a => mov r, a"
Now that we can easily detect all copies, we can optimize the"op r, a, a => mov r, a" case a bit more.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg/optimize: optimize "op r, a, a => movi r, 0"
Now that it's possible to detect copies, we can optimize the casethe "op r, a, a => movi r, 0". This helps in the computation ofoverflow flags when one of the two args is 0.
Reviewed-by: Richard Henderson <rth@twiddle.net>...
tcg/optimize: further optimize brcond/movcond/setcond
When both argument of brcond/movcond/setcond are the same or when oneof the two values is a constant equal to zero, it's possible to dofurther optimizations.
tcg/optimize: prefer the "op a, a, b" form for commutative ops
The "op a, a, b" form is better handled on non-RISC host than the "opa, b, a" form, so swap the arguments to this form when possible, andwhen b is not a constant.
This reduces the number of generated instructions by a tiny bit....
tcg: remove #ifdef #endif around TCGOpcode tests
Commit 25c4d9cc changed all TCGOpcode enums to be available, so we don'tneed to #ifdef #endif the one that are available only on some targets.This makes the code easier to read.
tcg/optimize: add constant folding for deposit
tcg/mips: optimize brcond arg, 0
MIPS has some conditional branch instructions when comparing with zero.Use them.
tcg/mips: optimize bswap{16,16s,32} on MIPS32R2
bswap operations can be optimized on MIPS32 Release 2 using the ROTR,WSBH and SEH instructions. We can't use the non-R2 code to implement theops due to registers constraints, so don't define the corresponding...
tcg/mips: implement rotl/rotr ops on MIPS32R2
rotr operations can be optimized on MIPS32 Release 2 using the ROTR andROTRV instructions. Also implemented rotl operations by subtracting theshift from 32.
tcg/mips: implement deposit op on MIPS32R2
deposit operations can be optimized on MIPS32 Release 2 using the INSinstruction.
tcg/mips: implement movcond op on MIPS32R2
movcond operation can be implemented on MIPS32 Release 2 using the MOVN,MOVZ, SLT and SLTU instructions.
tcg/optimize: remove TCG_TEMP_ANY
TCG_TEMP_ANY has no different meaning than TCG_TEMP_UNDEF, so usethe later instead.
tcg/optimize: check types in copy propagation
The copy propagation doesn't check the types of the temps during copypropagation. However TCG is using the mov_i32 for the i64 to i32conversion and thus the two are not equivalent.
With this patch tcg_opt_gen_mov() doesn't consider two temps of...
tcg-mips: fix wrong usage of 'Z' constraint
The 'Z' constraint has been introduced to map the zero register. Howeverwhen the op also accept a constant, there is no point to accept the zeroregister in addition.
tcg/mips: kill warnings in user mode
Recent versions of GCC emit warnings when compiling user mode targets.Kill them by reordering a bit the #ifdef.
tcg/mips: use TCGArg or TCGReg instead of int
Instead of int, use the correct TCGArg and TCGReg type: TCGReg whenrepresenting a TCG target register, TCGArg when representing the latteror a constant.
tcg/mips: don't use global pointer
Don't use the global pointer in TCG, in case helpers try access globalvariables.
tcg/mips: use stack for TCG temps
Use stack instead of temp_buf array in CPUState for TCGtemps.
tcg-sparc: Preserve branch destinations during retranslation
Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-sparc: Add %g/%o registers to alloc_order
tcg-sparc: Fix and enable direct TB chaining.
tcg-sparc: Clean up cruft stemming from attempts to use global registers.
Don't use -ffixed-gN. Don't link statically. Don't save/restoreAREG0 around calls. Don't allocate space on the stack for AREG0 save.
tcg-sparc: Mask shift immediates to avoid illegal insns.
The xtensa-test image generates a sra_i32 with count 0x40.Whether this is accident of tcg constant propagation ororiginating directly from the instruction stream is immaterial.
tcg-sparc: Use defines for temporaries.
And change from %i4/%i5 to %g1/%o7 to remove a v8plus fixme.
tcg-sparc: Support GUEST_BASE.
tcg-sparc: Change AREG0 in generated code to %i0.
We can now move the TCG variable from %g56 to a call-preservedwindowed register.
tcg-sparc: Fix qemu_ld/st to handle 32-bit host.
At the same time, split out the tlb load logic to a new function.Fixes the cases of two data registers and two address registers.Fixes the signature of, and adds missing, qemu_ld/st opcodes.
tcg-sparc: Don't MAP_FIXED on top of the program
The address we pick in sparc64.ld is also 0x60000000, so doing a fixed mapon top of that is guaranteed to blow up. Choosing 0x40000000 is exactlyright for the max of code_gen_buffer_size set below.
No need to ever use MAP_FIXED. While getting our desired address helps...
tcg-sparc: Assume v9 cpu always, i.e. force v8plus in 32-bit mode.
Current code doesn't actually work in 32-bit mode at all. Sinceno one really noticed, drop the complication of v7 and v8 cpus.Eliminate the --sparc_cpu configure option and standardize macro...
linux-user: Use memcpy in get_user/put_user.
When host and target have differing alignment rules, using a castand direct memory operation can result in SIGBUS. Use memcpy instead,which the compiler will happily optimize when alignment is satisfied.
Signed-off-by: Richard Henderson <rth@twiddle.net>...
tcg-sparc: Hack in qemu_ld/st64 for 32-bit.
Not actually implemented, but at least we avoid the tcg assert at startup.
tcg-sparc: Fix ADDX opcode.
Merge branch 'usb.65' of git://git.kraxel.org/qemu
tcg-hppa: Fix broken load/store helpers
The CONFIG_TCG_PASS_AREG0 code for calling ld/st helperswas not respecting the ABI requirement for 64-bit valuesbeing aligned in registers.
Mirror the ARM port in use of helper functions to marshalarguments into the correct registers....
target-alpha: Use movcond
For proper cmov insns, as well as the non-goto-tb caseof conditional branch.
tcg-i386: Implement movcond
Signed-off-by: Richard Henderson <rth@twiddle.net>Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg: Optimize movcond for constant comparisons
tcg: Optimize two-address commutative operations
While swapping constants to the second operand, swapsources matching destinations to the first operand.
gdbstub/sh4: fix build with USE_SOFTFLOAT_STRUCT_TYPES
We have to use different type to access float values whenUSE_SOFTFLOAT_STRUCT_TYPES is defined.
Rework SH4 version of cpu_gdb_{read,write}_register() usinga single case, and fixing the coding style. Use ldll_p() and...
tcg: Fix !USE_DIRECT_JUMP
Commit 6375e09e changed the type of TranslationBlock.tb_next,but failed to change the type of TCGContext.tb_next.
Signed-off-by: Richard Henderson <rth@twiddle.net>Reviewed-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg-hppa: Fix brcond2 and setcond2
Neither of these functions were performing double-wordcompares properly.
target-sh4: implement addv and subv using TCG
addv and subv helpers implementation is directly copied from the SH4manual and looks quite complex. It is however possible to explain itwithout branches, and is therefore possible to implement it with TCG....
target-sh4: optimize xtrct
The register being 32 bit long, after a shift to the right by 16 bits,the upper 16 bit are already cleared. There is no need to call ext16uto clear them.
target-sh4: optimize swap.w
It's possible swap the two 16-bit words of a 32-bit register using arotation. If the TCG target doesn't implement rotation, the replacementcode is similar to the previously implemented code.
target-sh4: remove gen_clr_t() and gen_set_t()
gen_clr_t() and gen_set_t() have very few callers and can be remplacedby a single line. Remove them.
target-sh4: rework exceptions handling
Since commit fd4bab102 PC is restored in case of exception through coderetranslation. While it is clearly the thing to do in case it is notnot known if an helper is going to trigger an exception or not(e.g. for load/store, FPU, etc.), it just make things slower when the...
target-sh4: cleanup DisasContext
We should avoid accessing env at translation stage, except of course forstatic values like the supported features.
Remove variables copied from env in DisasContext and use the TB flagsinstead.
target-sh4: remove useless code
Almost dead code.
tcg: Introduce movcond
Implemented with setcond if the target does not providethe optional opcode.
target-sh4: mark a few helpers const and pure
target-sh4: use float32_muladd() to implement fmac
There is no need to add a SH4 specific pickNaNMulAdd() to softfloat asSH4 is always returning a default NaN.
target-sh4: implement addc and subc using TCG
Now that setcond is available, the addc and subc can easily beimplemented using TCG.
target-xtensa: fix extui shift amount
extui opcode only uses lowermost op1 bit for sa4.
Reported-by: malc <av1474@comtv.ru>Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>Cc: qemu-stable <qemu-stable@nongnu.org>Signed-off-by: malc <av1474@comtv.ru>
target-xtensa: don't emit extra tcg_gen_goto_tb
Unconditional gen_check_loop_end at the end of disas_xtensa_insncan emit tcg_gen_goto_tb with slot id already used in the TB (e.g. whenTB ends at LEND with a branch).
tcg/optimize: fix end of basic block detection
Commit e31b0a7c050711884ad570fe73df806520953618 fixed copy propagation on32-bit host by restricting the copy between different types. This was thewrong fix.
The real problem is that the all temps states should be reset at the end...
target-mips: Implement Loongson Multimedia Instructions
Implements all of the COP2 instructions except for the S<cond>family of comparisons. The documentation is unclear for those.
target-mips: Always evaluate debugging macro arguments
this will prevent some of the compilation errors with debuggingenabled from creeping back in.