Archipelago » qemu

/*

 * Xtensa ISA:

 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm

 *

 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.

 * All rights reserved.

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions are met:

 *     * Redistributions of source code must retain the above copyright

 *       notice, this list of conditions and the following disclaimer.

 *     * Redistributions in binary form must reproduce the above copyright

 *       notice, this list of conditions and the following disclaimer in the

 *       documentation and/or other materials provided with the distribution.

 *     * Neither the name of the Open Source and Linux Lab nor the

 *       names of its contributors may be used to endorse or promote products

 *       derived from this software without specific prior written permission.

 *

 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY

 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;

 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND

 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS

 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */

#include <stdio.h>

#include "cpu.h"

#include "exec-all.h"

#include "disas.h"

#include "tcg-op.h"

#include "qemu-log.h"

#include "sysemu.h"

#include "helper.h"

#define GEN_HELPER 1

#include "helper.h"

typedef struct DisasContext {

    const XtensaConfig *config;

    TranslationBlock *tb;

    uint32_t pc;

    uint32_t next_pc;

    int cring;

    int ring;

    uint32_t lbeg;

    uint32_t lend;

    TCGv_i32 litbase;

    int is_jmp;

    int singlestep_enabled;

    bool sar_5bit;

    bool sar_m32_5bit;

    bool sar_m32_allocated;

    TCGv_i32 sar_m32;

    uint32_t ccount_delta;

    unsigned used_window;

    bool debug;

    bool icount;

    TCGv_i32 next_icount;

} DisasContext;

static TCGv_ptr cpu_env;

static TCGv_i32 cpu_pc;

static TCGv_i32 cpu_R[16];

static TCGv_i32 cpu_FR[16];

static TCGv_i32 cpu_SR[256];

static TCGv_i32 cpu_UR[256];

#include "gen-icount.h"

static const char * const sregnames[256] = {

    [LBEG] = "LBEG",

    [LEND] = "LEND",

    [LCOUNT] = "LCOUNT",

    [SAR] = "SAR",

    [BR] = "BR",

    [LITBASE] = "LITBASE",

    [SCOMPARE1] = "SCOMPARE1",

    [ACCLO] = "ACCLO",

    [ACCHI] = "ACCHI",

    [MR] = "MR0",

    [MR + 1] = "MR1",

    [MR + 2] = "MR2",

    [MR + 3] = "MR3",

    [WINDOW_BASE] = "WINDOW_BASE",

    [WINDOW_START] = "WINDOW_START",

    [PTEVADDR] = "PTEVADDR",

    [RASID] = "RASID",

    [ITLBCFG] = "ITLBCFG",

    [DTLBCFG] = "DTLBCFG",

    [IBREAKENABLE] = "IBREAKENABLE",

    [IBREAKA] = "IBREAKA0",

    [IBREAKA + 1] = "IBREAKA1",

    [DBREAKA] = "DBREAKA0",

    [DBREAKA + 1] = "DBREAKA1",

    [DBREAKC] = "DBREAKC0",

    [DBREAKC + 1] = "DBREAKC1",

    [EPC1] = "EPC1",

    [EPC1 + 1] = "EPC2",

    [EPC1 + 2] = "EPC3",

    [EPC1 + 3] = "EPC4",

    [EPC1 + 4] = "EPC5",

    [EPC1 + 5] = "EPC6",

    [EPC1 + 6] = "EPC7",

    [DEPC] = "DEPC",

    [EPS2] = "EPS2",

    [EPS2 + 1] = "EPS3",

    [EPS2 + 2] = "EPS4",

    [EPS2 + 3] = "EPS5",

    [EPS2 + 4] = "EPS6",

    [EPS2 + 5] = "EPS7",

    [EXCSAVE1] = "EXCSAVE1",

    [EXCSAVE1 + 1] = "EXCSAVE2",

    [EXCSAVE1 + 2] = "EXCSAVE3",

    [EXCSAVE1 + 3] = "EXCSAVE4",

    [EXCSAVE1 + 4] = "EXCSAVE5",

    [EXCSAVE1 + 5] = "EXCSAVE6",

    [EXCSAVE1 + 6] = "EXCSAVE7",

    [CPENABLE] = "CPENABLE",

    [INTSET] = "INTSET",

    [INTCLEAR] = "INTCLEAR",

    [INTENABLE] = "INTENABLE",

    [PS] = "PS",

    [VECBASE] = "VECBASE",

    [EXCCAUSE] = "EXCCAUSE",

    [DEBUGCAUSE] = "DEBUGCAUSE",

    [CCOUNT] = "CCOUNT",

    [PRID] = "PRID",

    [ICOUNT] = "ICOUNT",

    [ICOUNTLEVEL] = "ICOUNTLEVEL",

    [EXCVADDR] = "EXCVADDR",

    [CCOMPARE] = "CCOMPARE0",

    [CCOMPARE + 1] = "CCOMPARE1",

    [CCOMPARE + 2] = "CCOMPARE2",

};

static const char * const uregnames[256] = {

    [THREADPTR] = "THREADPTR",

    [FCR] = "FCR",

    [FSR] = "FSR",

};

void xtensa_translate_init(void)

{

    static const char * const regnames[] = {

        "ar0", "ar1", "ar2", "ar3",

        "ar4", "ar5", "ar6", "ar7",

        "ar8", "ar9", "ar10", "ar11",

        "ar12", "ar13", "ar14", "ar15",

    };

    static const char * const fregnames[] = {

        "f0", "f1", "f2", "f3",

        "f4", "f5", "f6", "f7",

        "f8", "f9", "f10", "f11",

        "f12", "f13", "f14", "f15",

    };

    int i;

    cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");

    cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,

            offsetof(CPUXtensaState, pc), "pc");

    for (i = 0; i < 16; i++) {

        cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,

                offsetof(CPUXtensaState, regs[i]),

                regnames[i]);

    }

    for (i = 0; i < 16; i++) {

        cpu_FR[i] = tcg_global_mem_new_i32(TCG_AREG0,

                offsetof(CPUXtensaState, fregs[i]),

                fregnames[i]);

    }

    for (i = 0; i < 256; ++i) {

        if (sregnames[i]) {

            cpu_SR[i] = tcg_global_mem_new_i32(TCG_AREG0,

                    offsetof(CPUXtensaState, sregs[i]),

                    sregnames[i]);

        }

    }

    for (i = 0; i < 256; ++i) {

        if (uregnames[i]) {

            cpu_UR[i] = tcg_global_mem_new_i32(TCG_AREG0,

                    offsetof(CPUXtensaState, uregs[i]),

                    uregnames[i]);

        }

    }

#define GEN_HELPER 2

#include "helper.h"

}

static inline bool option_bits_enabled(DisasContext *dc, uint64_t opt)

{

    return xtensa_option_bits_enabled(dc->config, opt);

}

static inline bool option_enabled(DisasContext *dc, int opt)

{

    return xtensa_option_enabled(dc->config, opt);

}

static void init_litbase(DisasContext *dc)

{

    if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {

        dc->litbase = tcg_temp_local_new_i32();

        tcg_gen_andi_i32(dc->litbase, cpu_SR[LITBASE], 0xfffff000);

    }

}

static void reset_litbase(DisasContext *dc)

{

    if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {

        tcg_temp_free(dc->litbase);

    }

}

static void init_sar_tracker(DisasContext *dc)

{

    dc->sar_5bit = false;

    dc->sar_m32_5bit = false;

    dc->sar_m32_allocated = false;

}

static void reset_sar_tracker(DisasContext *dc)

{

    if (dc->sar_m32_allocated) {

        tcg_temp_free(dc->sar_m32);

    }

}

static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)

{

    tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f);

    if (dc->sar_m32_5bit) {

        tcg_gen_discard_i32(dc->sar_m32);

    }

    dc->sar_5bit = true;

    dc->sar_m32_5bit = false;

}

static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)

{

    TCGv_i32 tmp = tcg_const_i32(32);

    if (!dc->sar_m32_allocated) {

        dc->sar_m32 = tcg_temp_local_new_i32();

        dc->sar_m32_allocated = true;

    }

    tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);

    tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32);

    dc->sar_5bit = false;

    dc->sar_m32_5bit = true;

    tcg_temp_free(tmp);

}

static void gen_advance_ccount(DisasContext *dc)

{

    if (dc->ccount_delta > 0) {

        TCGv_i32 tmp = tcg_const_i32(dc->ccount_delta);

        dc->ccount_delta = 0;

        gen_helper_advance_ccount(cpu_env, tmp);

        tcg_temp_free(tmp);

    }

}

static void reset_used_window(DisasContext *dc)

{

    dc->used_window = 0;

}

static void gen_exception(DisasContext *dc, int excp)

{

    TCGv_i32 tmp = tcg_const_i32(excp);

    gen_advance_ccount(dc);

    gen_helper_exception(cpu_env, tmp);

    tcg_temp_free(tmp);

}

static void gen_exception_cause(DisasContext *dc, uint32_t cause)

{

    TCGv_i32 tpc = tcg_const_i32(dc->pc);

    TCGv_i32 tcause = tcg_const_i32(cause);

    gen_advance_ccount(dc);

    gen_helper_exception_cause(cpu_env, tpc, tcause);

    tcg_temp_free(tpc);

    tcg_temp_free(tcause);

    if (cause == ILLEGAL_INSTRUCTION_CAUSE ||

            cause == SYSCALL_CAUSE) {

        dc->is_jmp = DISAS_UPDATE;

    }

}

static void gen_exception_cause_vaddr(DisasContext *dc, uint32_t cause,

        TCGv_i32 vaddr)

{

    TCGv_i32 tpc = tcg_const_i32(dc->pc);

    TCGv_i32 tcause = tcg_const_i32(cause);

    gen_advance_ccount(dc);

    gen_helper_exception_cause_vaddr(cpu_env, tpc, tcause, vaddr);

    tcg_temp_free(tpc);

    tcg_temp_free(tcause);

}

static void gen_debug_exception(DisasContext *dc, uint32_t cause)

{

    TCGv_i32 tpc = tcg_const_i32(dc->pc);

    TCGv_i32 tcause = tcg_const_i32(cause);

    gen_advance_ccount(dc);

    gen_helper_debug_exception(cpu_env, tpc, tcause);

    tcg_temp_free(tpc);

    tcg_temp_free(tcause);

    if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) {

        dc->is_jmp = DISAS_UPDATE;

    }

}

static void gen_check_privilege(DisasContext *dc)

{

    if (dc->cring) {

        gen_exception_cause(dc, PRIVILEGED_CAUSE);

        dc->is_jmp = DISAS_UPDATE;

    }

}

static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)

{

    tcg_gen_mov_i32(cpu_pc, dest);

    gen_advance_ccount(dc);

    if (dc->icount) {

        tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);

    }

    if (dc->singlestep_enabled) {

        gen_exception(dc, EXCP_DEBUG);

    } else {

        if (slot >= 0) {

            tcg_gen_goto_tb(slot);

            tcg_gen_exit_tb((tcg_target_long)dc->tb + slot);

        } else {

            tcg_gen_exit_tb(0);

        }

    }

    dc->is_jmp = DISAS_UPDATE;

}

static void gen_jump(DisasContext *dc, TCGv dest)

{

    gen_jump_slot(dc, dest, -1);

}

static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)

{

    TCGv_i32 tmp = tcg_const_i32(dest);

    if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {

        slot = -1;

    }

    gen_jump_slot(dc, tmp, slot);

    tcg_temp_free(tmp);

}

static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,

        int slot)

{

    TCGv_i32 tcallinc = tcg_const_i32(callinc);

    tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],

            tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);

    tcg_temp_free(tcallinc);

    tcg_gen_movi_i32(cpu_R[callinc << 2],

            (callinc << 30) | (dc->next_pc & 0x3fffffff));

    gen_jump_slot(dc, dest, slot);

}

static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest)

{

    gen_callw_slot(dc, callinc, dest, -1);

}

static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot)

{

    TCGv_i32 tmp = tcg_const_i32(dest);

    if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {

        slot = -1;

    }

    gen_callw_slot(dc, callinc, tmp, slot);

    tcg_temp_free(tmp);

}

static bool gen_check_loop_end(DisasContext *dc, int slot)

{

    if (option_enabled(dc, XTENSA_OPTION_LOOP) &&

            !(dc->tb->flags & XTENSA_TBFLAG_EXCM) &&

            dc->next_pc == dc->lend) {

        int label = gen_new_label();

        gen_advance_ccount(dc);

        tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label);

        tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1);

        gen_jumpi(dc, dc->lbeg, slot);

        gen_set_label(label);

        gen_jumpi(dc, dc->next_pc, -1);

        return true;

    }

    return false;

}

static void gen_jumpi_check_loop_end(DisasContext *dc, int slot)

{

    if (!gen_check_loop_end(dc, slot)) {

        gen_jumpi(dc, dc->next_pc, slot);

    }

}

static void gen_brcond(DisasContext *dc, TCGCond cond,

        TCGv_i32 t0, TCGv_i32 t1, uint32_t offset)

{

    int label = gen_new_label();

    gen_advance_ccount(dc);

    tcg_gen_brcond_i32(cond, t0, t1, label);

    gen_jumpi_check_loop_end(dc, 0);

    gen_set_label(label);

    gen_jumpi(dc, dc->pc + offset, 1);

}

static void gen_brcondi(DisasContext *dc, TCGCond cond,

        TCGv_i32 t0, uint32_t t1, uint32_t offset)

{

    TCGv_i32 tmp = tcg_const_i32(t1);

    gen_brcond(dc, cond, t0, tmp, offset);

    tcg_temp_free(tmp);

}

static void gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr)

{

    gen_advance_ccount(dc);

    tcg_gen_mov_i32(d, cpu_SR[sr]);

}

static void gen_rsr_ptevaddr(DisasContext *dc, TCGv_i32 d, uint32_t sr)

{

    tcg_gen_shri_i32(d, cpu_SR[EXCVADDR], 10);

    tcg_gen_or_i32(d, d, cpu_SR[sr]);

    tcg_gen_andi_i32(d, d, 0xfffffffc);

}

static void gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr)

{

    static void (* const rsr_handler[256])(DisasContext *dc,

            TCGv_i32 d, uint32_t sr) = {

        [CCOUNT] = gen_rsr_ccount,

        [PTEVADDR] = gen_rsr_ptevaddr,

    };

    if (sregnames[sr]) {

        if (rsr_handler[sr]) {

            rsr_handler[sr](dc, d, sr);

        } else {

            tcg_gen_mov_i32(d, cpu_SR[sr]);

        }

    } else {

        qemu_log("RSR %d not implemented, ", sr);

    }

}

static void gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s)

{

    gen_helper_wsr_lbeg(cpu_env, s);

    gen_jumpi_check_loop_end(dc, 0);

}

static void gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s)

{

    gen_helper_wsr_lend(cpu_env, s);

    gen_jumpi_check_loop_end(dc, 0);

}

static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s)

{

    tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f);

    if (dc->sar_m32_5bit) {

        tcg_gen_discard_i32(dc->sar_m32);

    }

    dc->sar_5bit = false;

    dc->sar_m32_5bit = false;

}

static void gen_wsr_br(DisasContext *dc, uint32_t sr, TCGv_i32 s)

{

    tcg_gen_andi_i32(cpu_SR[sr], s, 0xffff);

}

static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s)

{

    tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001);

    /* This can change tb->flags, so exit tb */

    gen_jumpi_check_loop_end(dc, -1);

}

static void gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s)

{

    tcg_gen_ext8s_i32(cpu_SR[sr], s);

}

static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v)

{

    gen_helper_wsr_windowbase(cpu_env, v);

    reset_used_window(dc);

}

static void gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v)

{

    tcg_gen_andi_i32(cpu_SR[sr], v, (1 << dc->config->nareg / 4) - 1);

    reset_used_window(dc);

}

static void gen_wsr_ptevaddr(DisasContext *dc, uint32_t sr, TCGv_i32 v)

{

    tcg_gen_andi_i32(cpu_SR[sr], v, 0xffc00000);

}

static void gen_wsr_rasid(DisasContext *dc, uint32_t sr, TCGv_i32 v)

{

    gen_helper_wsr_rasid(cpu_env, v);

    /* This can change tb->flags, so exit tb */

    gen_jumpi_check_loop_end(dc, -1);

}

static void gen_wsr_tlbcfg(DisasContext *dc, uint32_t sr, TCGv_i32 v)

{

    tcg_gen_andi_i32(cpu_SR[sr], v, 0x01130000);

}

static void gen_wsr_ibreakenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)

{

    gen_helper_wsr_ibreakenable(cpu_env, v);

    gen_jumpi_check_loop_end(dc, 0);

}

static void gen_wsr_ibreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)

{

    unsigned id = sr - IBREAKA;

    if (id < dc->config->nibreak) {

        TCGv_i32 tmp = tcg_const_i32(id);

        gen_helper_wsr_ibreaka(cpu_env, tmp, v);

        tcg_temp_free(tmp);

        gen_jumpi_check_loop_end(dc, 0);

    }

}

static void gen_wsr_dbreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)

{

    unsigned id = sr - DBREAKA;

    if (id < dc->config->ndbreak) {

        TCGv_i32 tmp = tcg_const_i32(id);

        gen_helper_wsr_dbreaka(cpu_env, tmp, v);

        tcg_temp_free(tmp);

    }

}

static void gen_wsr_dbreakc(DisasContext *dc, uint32_t sr, TCGv_i32 v)

{

    unsigned id = sr - DBREAKC;

    if (id < dc->config->ndbreak) {

        TCGv_i32 tmp = tcg_const_i32(id);

        gen_helper_wsr_dbreakc(cpu_env, tmp, v);

        tcg_temp_free(tmp);

    }

}

static void gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v)

{

    tcg_gen_andi_i32(cpu_SR[sr], v,

            dc->config->inttype_mask[INTTYPE_SOFTWARE]);

    gen_helper_check_interrupts(cpu_env);

    gen_jumpi_check_loop_end(dc, 0);

}

static void gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v)

{

    TCGv_i32 tmp = tcg_temp_new_i32();

    tcg_gen_andi_i32(tmp, v,

            dc->config->inttype_mask[INTTYPE_EDGE] |

            dc->config->inttype_mask[INTTYPE_NMI] |

            dc->config->inttype_mask[INTTYPE_SOFTWARE]);

    tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp);

    tcg_temp_free(tmp);

    gen_helper_check_interrupts(cpu_env);

}

static void gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)

{

    tcg_gen_mov_i32(cpu_SR[sr], v);

    gen_helper_check_interrupts(cpu_env);

    gen_jumpi_check_loop_end(dc, 0);

}

static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)

{

    uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB |

        PS_UM | PS_EXCM | PS_INTLEVEL;

    if (option_enabled(dc, XTENSA_OPTION_MMU)) {

        mask |= PS_RING;

    }

    tcg_gen_andi_i32(cpu_SR[sr], v, mask);

    reset_used_window(dc);

    gen_helper_check_interrupts(cpu_env);

    /* This can change mmu index and tb->flags, so exit tb */

    gen_jumpi_check_loop_end(dc, -1);

}

static void gen_wsr_debugcause(DisasContext *dc, uint32_t sr, TCGv_i32 v)

{

}

static void gen_wsr_prid(DisasContext *dc, uint32_t sr, TCGv_i32 v)

{

}

static void gen_wsr_icount(DisasContext *dc, uint32_t sr, TCGv_i32 v)

{

    if (dc->icount) {

        tcg_gen_mov_i32(dc->next_icount, v);

    } else {

        tcg_gen_mov_i32(cpu_SR[sr], v);

    }

}

static void gen_wsr_icountlevel(DisasContext *dc, uint32_t sr, TCGv_i32 v)

{

    tcg_gen_andi_i32(cpu_SR[sr], v, 0xf);

    /* This can change tb->flags, so exit tb */

    gen_jumpi_check_loop_end(dc, -1);

}

static void gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)

{

    uint32_t id = sr - CCOMPARE;

    if (id < dc->config->nccompare) {

        uint32_t int_bit = 1 << dc->config->timerint[id];

        gen_advance_ccount(dc);

        tcg_gen_mov_i32(cpu_SR[sr], v);

        tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit);

        gen_helper_check_interrupts(cpu_env);

    }

}

static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)

{

    static void (* const wsr_handler[256])(DisasContext *dc,

            uint32_t sr, TCGv_i32 v) = {

        [LBEG] = gen_wsr_lbeg,

        [LEND] = gen_wsr_lend,

        [SAR] = gen_wsr_sar,

        [BR] = gen_wsr_br,

        [LITBASE] = gen_wsr_litbase,

        [ACCHI] = gen_wsr_acchi,

        [WINDOW_BASE] = gen_wsr_windowbase,

        [WINDOW_START] = gen_wsr_windowstart,

        [PTEVADDR] = gen_wsr_ptevaddr,

        [RASID] = gen_wsr_rasid,

        [ITLBCFG] = gen_wsr_tlbcfg,

        [DTLBCFG] = gen_wsr_tlbcfg,

        [IBREAKENABLE] = gen_wsr_ibreakenable,

        [IBREAKA] = gen_wsr_ibreaka,

        [IBREAKA + 1] = gen_wsr_ibreaka,

        [DBREAKA] = gen_wsr_dbreaka,

        [DBREAKA + 1] = gen_wsr_dbreaka,

        [DBREAKC] = gen_wsr_dbreakc,

        [DBREAKC + 1] = gen_wsr_dbreakc,

        [INTSET] = gen_wsr_intset,

        [INTCLEAR] = gen_wsr_intclear,

        [INTENABLE] = gen_wsr_intenable,

        [PS] = gen_wsr_ps,

        [DEBUGCAUSE] = gen_wsr_debugcause,

        [PRID] = gen_wsr_prid,

        [ICOUNT] = gen_wsr_icount,

        [ICOUNTLEVEL] = gen_wsr_icountlevel,

        [CCOMPARE] = gen_wsr_ccompare,

        [CCOMPARE + 1] = gen_wsr_ccompare,

        [CCOMPARE + 2] = gen_wsr_ccompare,

    };

    if (sregnames[sr]) {

        if (wsr_handler[sr]) {

            wsr_handler[sr](dc, sr, s);

        } else {

            tcg_gen_mov_i32(cpu_SR[sr], s);

        }

    } else {

        qemu_log("WSR %d not implemented, ", sr);

    }

}

static void gen_wur(uint32_t ur, TCGv_i32 s)

{

    switch (ur) {

    case FCR:

        gen_helper_wur_fcr(cpu_env, s);

        break;

    case FSR:

        tcg_gen_andi_i32(cpu_UR[ur], s, 0xffffff80);

        break;

    default:

        tcg_gen_mov_i32(cpu_UR[ur], s);

        break;

    }

}

static void gen_load_store_alignment(DisasContext *dc, int shift,

        TCGv_i32 addr, bool no_hw_alignment)

{

    if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) {

        tcg_gen_andi_i32(addr, addr, ~0 << shift);

    } else if (option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT) &&

            no_hw_alignment) {

        int label = gen_new_label();

        TCGv_i32 tmp = tcg_temp_new_i32();

        tcg_gen_andi_i32(tmp, addr, ~(~0 << shift));

        tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);

        gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, addr);

        gen_set_label(label);

        tcg_temp_free(tmp);

    }

}

static void gen_waiti(DisasContext *dc, uint32_t imm4)

{

    TCGv_i32 pc = tcg_const_i32(dc->next_pc);

    TCGv_i32 intlevel = tcg_const_i32(imm4);

    gen_advance_ccount(dc);

    gen_helper_waiti(cpu_env, pc, intlevel);

    tcg_temp_free(pc);

    tcg_temp_free(intlevel);

}

static void gen_window_check1(DisasContext *dc, unsigned r1)

{

    if (dc->tb->flags & XTENSA_TBFLAG_EXCM) {

        return;

    }

    if (option_enabled(dc, XTENSA_OPTION_WINDOWED_REGISTER) &&

            r1 / 4 > dc->used_window) {

        TCGv_i32 pc = tcg_const_i32(dc->pc);

        TCGv_i32 w = tcg_const_i32(r1 / 4);

        dc->used_window = r1 / 4;

        gen_advance_ccount(dc);

        gen_helper_window_check(cpu_env, pc, w);

        tcg_temp_free(w);

        tcg_temp_free(pc);

    }

}

static void gen_window_check2(DisasContext *dc, unsigned r1, unsigned r2)

{

    gen_window_check1(dc, r1 > r2 ? r1 : r2);

}

static void gen_window_check3(DisasContext *dc, unsigned r1, unsigned r2,

        unsigned r3)

{

    gen_window_check2(dc, r1, r2 > r3 ? r2 : r3);

}

static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned)

{

    TCGv_i32 m = tcg_temp_new_i32();

    if (hi) {

        (is_unsigned ? tcg_gen_shri_i32 : tcg_gen_sari_i32)(m, v, 16);

    } else {

        (is_unsigned ? tcg_gen_ext16u_i32 : tcg_gen_ext16s_i32)(m, v);

    }

    return m;

}

static void disas_xtensa_insn(DisasContext *dc)

{

#define HAS_OPTION_BITS(opt) do { \

        if (!option_bits_enabled(dc, opt)) { \

            qemu_log("Option is not enabled %s:%d\n", \

                    __FILE__, __LINE__); \

            goto invalid_opcode; \

        } \

    } while (0)

#define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt))

#define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)

#define RESERVED() do { \

        qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \

                dc->pc, b0, b1, b2, __FILE__, __LINE__); \

        goto invalid_opcode; \

    } while (0)

#ifdef TARGET_WORDS_BIGENDIAN

#define OP0 (((b0) & 0xf0) >> 4)

#define OP1 (((b2) & 0xf0) >> 4)

#define OP2 ((b2) & 0xf)

#define RRR_R ((b1) & 0xf)

#define RRR_S (((b1) & 0xf0) >> 4)

#define RRR_T ((b0) & 0xf)

#else

#define OP0 (((b0) & 0xf))

#define OP1 (((b2) & 0xf))

#define OP2 (((b2) & 0xf0) >> 4)

#define RRR_R (((b1) & 0xf0) >> 4)

#define RRR_S (((b1) & 0xf))

#define RRR_T (((b0) & 0xf0) >> 4)

#endif

#define RRR_X ((RRR_R & 0x4) >> 2)

#define RRR_Y ((RRR_T & 0x4) >> 2)

#define RRR_W (RRR_R & 0x3)

#define RRRN_R RRR_R

#define RRRN_S RRR_S

#define RRRN_T RRR_T

#define RRI8_R RRR_R

#define RRI8_S RRR_S

#define RRI8_T RRR_T

#define RRI8_IMM8 (b2)

#define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)

#ifdef TARGET_WORDS_BIGENDIAN

#define RI16_IMM16 (((b1) << 8) | (b2))

#else

#define RI16_IMM16 (((b2) << 8) | (b1))

#endif

#ifdef TARGET_WORDS_BIGENDIAN

#define CALL_N (((b0) & 0xc) >> 2)

#define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))

#else

#define CALL_N (((b0) & 0x30) >> 4)

#define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))

#endif

#define CALL_OFFSET_SE \

    (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)

#define CALLX_N CALL_N

#ifdef TARGET_WORDS_BIGENDIAN

#define CALLX_M ((b0) & 0x3)

#else

#define CALLX_M (((b0) & 0xc0) >> 6)

#endif

#define CALLX_S RRR_S

#define BRI12_M CALLX_M

#define BRI12_S RRR_S

#ifdef TARGET_WORDS_BIGENDIAN

#define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))

#else