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/*
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* Xtensa ISA:
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* http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
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*
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* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Open Source and Linux Lab nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <stdio.h> |
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#include "cpu.h" |
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#include "exec-all.h" |
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#include "disas.h" |
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#include "tcg-op.h" |
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#include "qemu-log.h" |
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#include "sysemu.h" |
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#include "helper.h" |
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#define GEN_HELPER 1 |
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#include "helper.h" |
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typedef struct DisasContext { |
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const XtensaConfig *config;
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TranslationBlock *tb; |
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uint32_t pc; |
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uint32_t next_pc; |
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int cring;
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int ring;
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uint32_t lbeg; |
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uint32_t lend; |
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TCGv_i32 litbase; |
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int is_jmp;
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int singlestep_enabled;
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|
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bool sar_5bit;
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bool sar_m32_5bit;
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bool sar_m32_allocated;
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TCGv_i32 sar_m32; |
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|
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uint32_t ccount_delta; |
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unsigned used_window;
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|
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bool debug;
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bool icount;
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TCGv_i32 next_icount; |
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} DisasContext; |
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|
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static TCGv_ptr cpu_env;
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static TCGv_i32 cpu_pc;
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static TCGv_i32 cpu_R[16]; |
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static TCGv_i32 cpu_FR[16]; |
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static TCGv_i32 cpu_SR[256]; |
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static TCGv_i32 cpu_UR[256]; |
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#include "gen-icount.h" |
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static const char * const sregnames[256] = { |
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[LBEG] = "LBEG",
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[LEND] = "LEND",
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[LCOUNT] = "LCOUNT",
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[SAR] = "SAR",
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[BR] = "BR",
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[LITBASE] = "LITBASE",
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[SCOMPARE1] = "SCOMPARE1",
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[ACCLO] = "ACCLO",
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[ACCHI] = "ACCHI",
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[MR] = "MR0",
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[MR + 1] = "MR1", |
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[MR + 2] = "MR2", |
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[MR + 3] = "MR3", |
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[WINDOW_BASE] = "WINDOW_BASE",
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[WINDOW_START] = "WINDOW_START",
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[PTEVADDR] = "PTEVADDR",
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[RASID] = "RASID",
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[ITLBCFG] = "ITLBCFG",
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[DTLBCFG] = "DTLBCFG",
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[IBREAKENABLE] = "IBREAKENABLE",
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[IBREAKA] = "IBREAKA0",
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[IBREAKA + 1] = "IBREAKA1", |
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[DBREAKA] = "DBREAKA0",
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[DBREAKA + 1] = "DBREAKA1", |
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[DBREAKC] = "DBREAKC0",
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[DBREAKC + 1] = "DBREAKC1", |
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[EPC1] = "EPC1",
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[EPC1 + 1] = "EPC2", |
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[EPC1 + 2] = "EPC3", |
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[EPC1 + 3] = "EPC4", |
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[EPC1 + 4] = "EPC5", |
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[EPC1 + 5] = "EPC6", |
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[EPC1 + 6] = "EPC7", |
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[DEPC] = "DEPC",
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[EPS2] = "EPS2",
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[EPS2 + 1] = "EPS3", |
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[EPS2 + 2] = "EPS4", |
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[EPS2 + 3] = "EPS5", |
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[EPS2 + 4] = "EPS6", |
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[EPS2 + 5] = "EPS7", |
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[EXCSAVE1] = "EXCSAVE1",
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[EXCSAVE1 + 1] = "EXCSAVE2", |
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[EXCSAVE1 + 2] = "EXCSAVE3", |
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[EXCSAVE1 + 3] = "EXCSAVE4", |
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[EXCSAVE1 + 4] = "EXCSAVE5", |
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[EXCSAVE1 + 5] = "EXCSAVE6", |
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[EXCSAVE1 + 6] = "EXCSAVE7", |
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[CPENABLE] = "CPENABLE",
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[INTSET] = "INTSET",
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[INTCLEAR] = "INTCLEAR",
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[INTENABLE] = "INTENABLE",
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[PS] = "PS",
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[VECBASE] = "VECBASE",
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[EXCCAUSE] = "EXCCAUSE",
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[DEBUGCAUSE] = "DEBUGCAUSE",
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[CCOUNT] = "CCOUNT",
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[PRID] = "PRID",
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[ICOUNT] = "ICOUNT",
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[ICOUNTLEVEL] = "ICOUNTLEVEL",
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[EXCVADDR] = "EXCVADDR",
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[CCOMPARE] = "CCOMPARE0",
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[CCOMPARE + 1] = "CCOMPARE1", |
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[CCOMPARE + 2] = "CCOMPARE2", |
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}; |
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static const char * const uregnames[256] = { |
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[THREADPTR] = "THREADPTR",
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[FCR] = "FCR",
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[FSR] = "FSR",
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}; |
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void xtensa_translate_init(void) |
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{ |
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static const char * const regnames[] = { |
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"ar0", "ar1", "ar2", "ar3", |
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"ar4", "ar5", "ar6", "ar7", |
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"ar8", "ar9", "ar10", "ar11", |
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"ar12", "ar13", "ar14", "ar15", |
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}; |
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static const char * const fregnames[] = { |
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"f0", "f1", "f2", "f3", |
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"f4", "f5", "f6", "f7", |
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"f8", "f9", "f10", "f11", |
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"f12", "f13", "f14", "f15", |
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}; |
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int i;
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cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
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cpu_pc = tcg_global_mem_new_i32(TCG_AREG0, |
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offsetof(CPUXtensaState, pc), "pc");
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for (i = 0; i < 16; i++) { |
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cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0, |
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offsetof(CPUXtensaState, regs[i]), |
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regnames[i]); |
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} |
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for (i = 0; i < 16; i++) { |
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cpu_FR[i] = tcg_global_mem_new_i32(TCG_AREG0, |
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offsetof(CPUXtensaState, fregs[i]), |
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fregnames[i]); |
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} |
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for (i = 0; i < 256; ++i) { |
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if (sregnames[i]) {
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cpu_SR[i] = tcg_global_mem_new_i32(TCG_AREG0, |
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offsetof(CPUXtensaState, sregs[i]), |
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sregnames[i]); |
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} |
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} |
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for (i = 0; i < 256; ++i) { |
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if (uregnames[i]) {
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cpu_UR[i] = tcg_global_mem_new_i32(TCG_AREG0, |
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offsetof(CPUXtensaState, uregs[i]), |
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uregnames[i]); |
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} |
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} |
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#define GEN_HELPER 2 |
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#include "helper.h" |
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} |
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static inline bool option_bits_enabled(DisasContext *dc, uint64_t opt) |
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{ |
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return xtensa_option_bits_enabled(dc->config, opt);
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} |
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static inline bool option_enabled(DisasContext *dc, int opt) |
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{ |
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return xtensa_option_enabled(dc->config, opt);
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} |
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static void init_litbase(DisasContext *dc) |
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{ |
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if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
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dc->litbase = tcg_temp_local_new_i32(); |
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tcg_gen_andi_i32(dc->litbase, cpu_SR[LITBASE], 0xfffff000);
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} |
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} |
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static void reset_litbase(DisasContext *dc) |
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{ |
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if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
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tcg_temp_free(dc->litbase); |
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} |
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} |
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static void init_sar_tracker(DisasContext *dc) |
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{ |
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dc->sar_5bit = false;
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dc->sar_m32_5bit = false;
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dc->sar_m32_allocated = false;
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} |
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static void reset_sar_tracker(DisasContext *dc) |
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{ |
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if (dc->sar_m32_allocated) {
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tcg_temp_free(dc->sar_m32); |
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} |
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} |
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static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa) |
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{ |
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tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f);
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if (dc->sar_m32_5bit) {
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tcg_gen_discard_i32(dc->sar_m32); |
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} |
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dc->sar_5bit = true;
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dc->sar_m32_5bit = false;
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} |
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static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa) |
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{ |
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TCGv_i32 tmp = tcg_const_i32(32);
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if (!dc->sar_m32_allocated) {
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dc->sar_m32 = tcg_temp_local_new_i32(); |
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dc->sar_m32_allocated = true;
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} |
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tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
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tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32); |
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dc->sar_5bit = false;
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dc->sar_m32_5bit = true;
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tcg_temp_free(tmp); |
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} |
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static void gen_advance_ccount(DisasContext *dc) |
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{ |
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if (dc->ccount_delta > 0) { |
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TCGv_i32 tmp = tcg_const_i32(dc->ccount_delta); |
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dc->ccount_delta = 0;
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gen_helper_advance_ccount(cpu_env, tmp); |
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tcg_temp_free(tmp); |
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} |
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} |
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static void reset_used_window(DisasContext *dc) |
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{ |
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dc->used_window = 0;
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} |
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static void gen_exception(DisasContext *dc, int excp) |
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{ |
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TCGv_i32 tmp = tcg_const_i32(excp); |
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gen_advance_ccount(dc); |
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gen_helper_exception(cpu_env, tmp); |
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tcg_temp_free(tmp); |
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} |
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static void gen_exception_cause(DisasContext *dc, uint32_t cause) |
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{ |
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TCGv_i32 tpc = tcg_const_i32(dc->pc); |
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TCGv_i32 tcause = tcg_const_i32(cause); |
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gen_advance_ccount(dc); |
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gen_helper_exception_cause(cpu_env, tpc, tcause); |
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tcg_temp_free(tpc); |
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tcg_temp_free(tcause); |
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if (cause == ILLEGAL_INSTRUCTION_CAUSE ||
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cause == SYSCALL_CAUSE) { |
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dc->is_jmp = DISAS_UPDATE; |
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} |
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} |
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static void gen_exception_cause_vaddr(DisasContext *dc, uint32_t cause, |
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TCGv_i32 vaddr) |
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{ |
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TCGv_i32 tpc = tcg_const_i32(dc->pc); |
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TCGv_i32 tcause = tcg_const_i32(cause); |
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gen_advance_ccount(dc); |
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gen_helper_exception_cause_vaddr(cpu_env, tpc, tcause, vaddr); |
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tcg_temp_free(tpc); |
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tcg_temp_free(tcause); |
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} |
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|
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static void gen_debug_exception(DisasContext *dc, uint32_t cause) |
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{ |
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TCGv_i32 tpc = tcg_const_i32(dc->pc); |
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TCGv_i32 tcause = tcg_const_i32(cause); |
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gen_advance_ccount(dc); |
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gen_helper_debug_exception(cpu_env, tpc, tcause); |
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tcg_temp_free(tpc); |
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tcg_temp_free(tcause); |
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if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) {
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dc->is_jmp = DISAS_UPDATE; |
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} |
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} |
325 |
|
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static void gen_check_privilege(DisasContext *dc) |
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{ |
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if (dc->cring) {
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gen_exception_cause(dc, PRIVILEGED_CAUSE); |
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dc->is_jmp = DISAS_UPDATE; |
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} |
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} |
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|
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static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot) |
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{ |
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tcg_gen_mov_i32(cpu_pc, dest); |
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gen_advance_ccount(dc); |
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if (dc->icount) {
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tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount); |
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} |
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if (dc->singlestep_enabled) {
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gen_exception(dc, EXCP_DEBUG); |
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} else {
|
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if (slot >= 0) { |
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tcg_gen_goto_tb(slot); |
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tcg_gen_exit_tb((tcg_target_long)dc->tb + slot); |
347 |
} else {
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tcg_gen_exit_tb(0);
|
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} |
350 |
} |
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dc->is_jmp = DISAS_UPDATE; |
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} |
353 |
|
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static void gen_jump(DisasContext *dc, TCGv dest) |
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{ |
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gen_jump_slot(dc, dest, -1);
|
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} |
358 |
|
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static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot) |
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{ |
361 |
TCGv_i32 tmp = tcg_const_i32(dest); |
362 |
if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) { |
363 |
slot = -1;
|
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} |
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gen_jump_slot(dc, tmp, slot); |
366 |
tcg_temp_free(tmp); |
367 |
} |
368 |
|
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static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest, |
370 |
int slot)
|
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{ |
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TCGv_i32 tcallinc = tcg_const_i32(callinc); |
373 |
|
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tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS], |
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tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN); |
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tcg_temp_free(tcallinc); |
377 |
tcg_gen_movi_i32(cpu_R[callinc << 2],
|
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(callinc << 30) | (dc->next_pc & 0x3fffffff)); |
379 |
gen_jump_slot(dc, dest, slot); |
380 |
} |
381 |
|
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static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest) |
383 |
{ |
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gen_callw_slot(dc, callinc, dest, -1);
|
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} |
386 |
|
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static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot) |
388 |
{ |
389 |
TCGv_i32 tmp = tcg_const_i32(dest); |
390 |
if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) { |
391 |
slot = -1;
|
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} |
393 |
gen_callw_slot(dc, callinc, tmp, slot); |
394 |
tcg_temp_free(tmp); |
395 |
} |
396 |
|
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static bool gen_check_loop_end(DisasContext *dc, int slot) |
398 |
{ |
399 |
if (option_enabled(dc, XTENSA_OPTION_LOOP) &&
|
400 |
!(dc->tb->flags & XTENSA_TBFLAG_EXCM) && |
401 |
dc->next_pc == dc->lend) { |
402 |
int label = gen_new_label();
|
403 |
|
404 |
gen_advance_ccount(dc); |
405 |
tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label);
|
406 |
tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1);
|
407 |
gen_jumpi(dc, dc->lbeg, slot); |
408 |
gen_set_label(label); |
409 |
gen_jumpi(dc, dc->next_pc, -1);
|
410 |
return true; |
411 |
} |
412 |
return false; |
413 |
} |
414 |
|
415 |
static void gen_jumpi_check_loop_end(DisasContext *dc, int slot) |
416 |
{ |
417 |
if (!gen_check_loop_end(dc, slot)) {
|
418 |
gen_jumpi(dc, dc->next_pc, slot); |
419 |
} |
420 |
} |
421 |
|
422 |
static void gen_brcond(DisasContext *dc, TCGCond cond, |
423 |
TCGv_i32 t0, TCGv_i32 t1, uint32_t offset) |
424 |
{ |
425 |
int label = gen_new_label();
|
426 |
|
427 |
gen_advance_ccount(dc); |
428 |
tcg_gen_brcond_i32(cond, t0, t1, label); |
429 |
gen_jumpi_check_loop_end(dc, 0);
|
430 |
gen_set_label(label); |
431 |
gen_jumpi(dc, dc->pc + offset, 1);
|
432 |
} |
433 |
|
434 |
static void gen_brcondi(DisasContext *dc, TCGCond cond, |
435 |
TCGv_i32 t0, uint32_t t1, uint32_t offset) |
436 |
{ |
437 |
TCGv_i32 tmp = tcg_const_i32(t1); |
438 |
gen_brcond(dc, cond, t0, tmp, offset); |
439 |
tcg_temp_free(tmp); |
440 |
} |
441 |
|
442 |
static void gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr) |
443 |
{ |
444 |
gen_advance_ccount(dc); |
445 |
tcg_gen_mov_i32(d, cpu_SR[sr]); |
446 |
} |
447 |
|
448 |
static void gen_rsr_ptevaddr(DisasContext *dc, TCGv_i32 d, uint32_t sr) |
449 |
{ |
450 |
tcg_gen_shri_i32(d, cpu_SR[EXCVADDR], 10);
|
451 |
tcg_gen_or_i32(d, d, cpu_SR[sr]); |
452 |
tcg_gen_andi_i32(d, d, 0xfffffffc);
|
453 |
} |
454 |
|
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static void gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr) |
456 |
{ |
457 |
static void (* const rsr_handler[256])(DisasContext *dc, |
458 |
TCGv_i32 d, uint32_t sr) = { |
459 |
[CCOUNT] = gen_rsr_ccount, |
460 |
[PTEVADDR] = gen_rsr_ptevaddr, |
461 |
}; |
462 |
|
463 |
if (sregnames[sr]) {
|
464 |
if (rsr_handler[sr]) {
|
465 |
rsr_handler[sr](dc, d, sr); |
466 |
} else {
|
467 |
tcg_gen_mov_i32(d, cpu_SR[sr]); |
468 |
} |
469 |
} else {
|
470 |
qemu_log("RSR %d not implemented, ", sr);
|
471 |
} |
472 |
} |
473 |
|
474 |
static void gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s) |
475 |
{ |
476 |
gen_helper_wsr_lbeg(cpu_env, s); |
477 |
gen_jumpi_check_loop_end(dc, 0);
|
478 |
} |
479 |
|
480 |
static void gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s) |
481 |
{ |
482 |
gen_helper_wsr_lend(cpu_env, s); |
483 |
gen_jumpi_check_loop_end(dc, 0);
|
484 |
} |
485 |
|
486 |
static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s) |
487 |
{ |
488 |
tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f);
|
489 |
if (dc->sar_m32_5bit) {
|
490 |
tcg_gen_discard_i32(dc->sar_m32); |
491 |
} |
492 |
dc->sar_5bit = false;
|
493 |
dc->sar_m32_5bit = false;
|
494 |
} |
495 |
|
496 |
static void gen_wsr_br(DisasContext *dc, uint32_t sr, TCGv_i32 s) |
497 |
{ |
498 |
tcg_gen_andi_i32(cpu_SR[sr], s, 0xffff);
|
499 |
} |
500 |
|
501 |
static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s) |
502 |
{ |
503 |
tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001);
|
504 |
/* This can change tb->flags, so exit tb */
|
505 |
gen_jumpi_check_loop_end(dc, -1);
|
506 |
} |
507 |
|
508 |
static void gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s) |
509 |
{ |
510 |
tcg_gen_ext8s_i32(cpu_SR[sr], s); |
511 |
} |
512 |
|
513 |
static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
514 |
{ |
515 |
gen_helper_wsr_windowbase(cpu_env, v); |
516 |
reset_used_window(dc); |
517 |
} |
518 |
|
519 |
static void gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
520 |
{ |
521 |
tcg_gen_andi_i32(cpu_SR[sr], v, (1 << dc->config->nareg / 4) - 1); |
522 |
reset_used_window(dc); |
523 |
} |
524 |
|
525 |
static void gen_wsr_ptevaddr(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
526 |
{ |
527 |
tcg_gen_andi_i32(cpu_SR[sr], v, 0xffc00000);
|
528 |
} |
529 |
|
530 |
static void gen_wsr_rasid(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
531 |
{ |
532 |
gen_helper_wsr_rasid(cpu_env, v); |
533 |
/* This can change tb->flags, so exit tb */
|
534 |
gen_jumpi_check_loop_end(dc, -1);
|
535 |
} |
536 |
|
537 |
static void gen_wsr_tlbcfg(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
538 |
{ |
539 |
tcg_gen_andi_i32(cpu_SR[sr], v, 0x01130000);
|
540 |
} |
541 |
|
542 |
static void gen_wsr_ibreakenable(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
543 |
{ |
544 |
gen_helper_wsr_ibreakenable(cpu_env, v); |
545 |
gen_jumpi_check_loop_end(dc, 0);
|
546 |
} |
547 |
|
548 |
static void gen_wsr_ibreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
549 |
{ |
550 |
unsigned id = sr - IBREAKA;
|
551 |
|
552 |
if (id < dc->config->nibreak) {
|
553 |
TCGv_i32 tmp = tcg_const_i32(id); |
554 |
gen_helper_wsr_ibreaka(cpu_env, tmp, v); |
555 |
tcg_temp_free(tmp); |
556 |
gen_jumpi_check_loop_end(dc, 0);
|
557 |
} |
558 |
} |
559 |
|
560 |
static void gen_wsr_dbreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
561 |
{ |
562 |
unsigned id = sr - DBREAKA;
|
563 |
|
564 |
if (id < dc->config->ndbreak) {
|
565 |
TCGv_i32 tmp = tcg_const_i32(id); |
566 |
gen_helper_wsr_dbreaka(cpu_env, tmp, v); |
567 |
tcg_temp_free(tmp); |
568 |
} |
569 |
} |
570 |
|
571 |
static void gen_wsr_dbreakc(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
572 |
{ |
573 |
unsigned id = sr - DBREAKC;
|
574 |
|
575 |
if (id < dc->config->ndbreak) {
|
576 |
TCGv_i32 tmp = tcg_const_i32(id); |
577 |
gen_helper_wsr_dbreakc(cpu_env, tmp, v); |
578 |
tcg_temp_free(tmp); |
579 |
} |
580 |
} |
581 |
|
582 |
static void gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
583 |
{ |
584 |
tcg_gen_andi_i32(cpu_SR[sr], v, |
585 |
dc->config->inttype_mask[INTTYPE_SOFTWARE]); |
586 |
gen_helper_check_interrupts(cpu_env); |
587 |
gen_jumpi_check_loop_end(dc, 0);
|
588 |
} |
589 |
|
590 |
static void gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
591 |
{ |
592 |
TCGv_i32 tmp = tcg_temp_new_i32(); |
593 |
|
594 |
tcg_gen_andi_i32(tmp, v, |
595 |
dc->config->inttype_mask[INTTYPE_EDGE] | |
596 |
dc->config->inttype_mask[INTTYPE_NMI] | |
597 |
dc->config->inttype_mask[INTTYPE_SOFTWARE]); |
598 |
tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp); |
599 |
tcg_temp_free(tmp); |
600 |
gen_helper_check_interrupts(cpu_env); |
601 |
} |
602 |
|
603 |
static void gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
604 |
{ |
605 |
tcg_gen_mov_i32(cpu_SR[sr], v); |
606 |
gen_helper_check_interrupts(cpu_env); |
607 |
gen_jumpi_check_loop_end(dc, 0);
|
608 |
} |
609 |
|
610 |
static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
611 |
{ |
612 |
uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB | |
613 |
PS_UM | PS_EXCM | PS_INTLEVEL; |
614 |
|
615 |
if (option_enabled(dc, XTENSA_OPTION_MMU)) {
|
616 |
mask |= PS_RING; |
617 |
} |
618 |
tcg_gen_andi_i32(cpu_SR[sr], v, mask); |
619 |
reset_used_window(dc); |
620 |
gen_helper_check_interrupts(cpu_env); |
621 |
/* This can change mmu index and tb->flags, so exit tb */
|
622 |
gen_jumpi_check_loop_end(dc, -1);
|
623 |
} |
624 |
|
625 |
static void gen_wsr_debugcause(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
626 |
{ |
627 |
} |
628 |
|
629 |
static void gen_wsr_prid(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
630 |
{ |
631 |
} |
632 |
|
633 |
static void gen_wsr_icount(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
634 |
{ |
635 |
if (dc->icount) {
|
636 |
tcg_gen_mov_i32(dc->next_icount, v); |
637 |
} else {
|
638 |
tcg_gen_mov_i32(cpu_SR[sr], v); |
639 |
} |
640 |
} |
641 |
|
642 |
static void gen_wsr_icountlevel(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
643 |
{ |
644 |
tcg_gen_andi_i32(cpu_SR[sr], v, 0xf);
|
645 |
/* This can change tb->flags, so exit tb */
|
646 |
gen_jumpi_check_loop_end(dc, -1);
|
647 |
} |
648 |
|
649 |
static void gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
650 |
{ |
651 |
uint32_t id = sr - CCOMPARE; |
652 |
if (id < dc->config->nccompare) {
|
653 |
uint32_t int_bit = 1 << dc->config->timerint[id];
|
654 |
gen_advance_ccount(dc); |
655 |
tcg_gen_mov_i32(cpu_SR[sr], v); |
656 |
tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit); |
657 |
gen_helper_check_interrupts(cpu_env); |
658 |
} |
659 |
} |
660 |
|
661 |
static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s) |
662 |
{ |
663 |
static void (* const wsr_handler[256])(DisasContext *dc, |
664 |
uint32_t sr, TCGv_i32 v) = { |
665 |
[LBEG] = gen_wsr_lbeg, |
666 |
[LEND] = gen_wsr_lend, |
667 |
[SAR] = gen_wsr_sar, |
668 |
[BR] = gen_wsr_br, |
669 |
[LITBASE] = gen_wsr_litbase, |
670 |
[ACCHI] = gen_wsr_acchi, |
671 |
[WINDOW_BASE] = gen_wsr_windowbase, |
672 |
[WINDOW_START] = gen_wsr_windowstart, |
673 |
[PTEVADDR] = gen_wsr_ptevaddr, |
674 |
[RASID] = gen_wsr_rasid, |
675 |
[ITLBCFG] = gen_wsr_tlbcfg, |
676 |
[DTLBCFG] = gen_wsr_tlbcfg, |
677 |
[IBREAKENABLE] = gen_wsr_ibreakenable, |
678 |
[IBREAKA] = gen_wsr_ibreaka, |
679 |
[IBREAKA + 1] = gen_wsr_ibreaka,
|
680 |
[DBREAKA] = gen_wsr_dbreaka, |
681 |
[DBREAKA + 1] = gen_wsr_dbreaka,
|
682 |
[DBREAKC] = gen_wsr_dbreakc, |
683 |
[DBREAKC + 1] = gen_wsr_dbreakc,
|
684 |
[INTSET] = gen_wsr_intset, |
685 |
[INTCLEAR] = gen_wsr_intclear, |
686 |
[INTENABLE] = gen_wsr_intenable, |
687 |
[PS] = gen_wsr_ps, |
688 |
[DEBUGCAUSE] = gen_wsr_debugcause, |
689 |
[PRID] = gen_wsr_prid, |
690 |
[ICOUNT] = gen_wsr_icount, |
691 |
[ICOUNTLEVEL] = gen_wsr_icountlevel, |
692 |
[CCOMPARE] = gen_wsr_ccompare, |
693 |
[CCOMPARE + 1] = gen_wsr_ccompare,
|
694 |
[CCOMPARE + 2] = gen_wsr_ccompare,
|
695 |
}; |
696 |
|
697 |
if (sregnames[sr]) {
|
698 |
if (wsr_handler[sr]) {
|
699 |
wsr_handler[sr](dc, sr, s); |
700 |
} else {
|
701 |
tcg_gen_mov_i32(cpu_SR[sr], s); |
702 |
} |
703 |
} else {
|
704 |
qemu_log("WSR %d not implemented, ", sr);
|
705 |
} |
706 |
} |
707 |
|
708 |
static void gen_wur(uint32_t ur, TCGv_i32 s) |
709 |
{ |
710 |
switch (ur) {
|
711 |
case FCR:
|
712 |
gen_helper_wur_fcr(cpu_env, s); |
713 |
break;
|
714 |
|
715 |
case FSR:
|
716 |
tcg_gen_andi_i32(cpu_UR[ur], s, 0xffffff80);
|
717 |
break;
|
718 |
|
719 |
default:
|
720 |
tcg_gen_mov_i32(cpu_UR[ur], s); |
721 |
break;
|
722 |
} |
723 |
} |
724 |
|
725 |
static void gen_load_store_alignment(DisasContext *dc, int shift, |
726 |
TCGv_i32 addr, bool no_hw_alignment)
|
727 |
{ |
728 |
if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) {
|
729 |
tcg_gen_andi_i32(addr, addr, ~0 << shift);
|
730 |
} else if (option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT) && |
731 |
no_hw_alignment) { |
732 |
int label = gen_new_label();
|
733 |
TCGv_i32 tmp = tcg_temp_new_i32(); |
734 |
tcg_gen_andi_i32(tmp, addr, ~(~0 << shift));
|
735 |
tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
|
736 |
gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, addr); |
737 |
gen_set_label(label); |
738 |
tcg_temp_free(tmp); |
739 |
} |
740 |
} |
741 |
|
742 |
static void gen_waiti(DisasContext *dc, uint32_t imm4) |
743 |
{ |
744 |
TCGv_i32 pc = tcg_const_i32(dc->next_pc); |
745 |
TCGv_i32 intlevel = tcg_const_i32(imm4); |
746 |
gen_advance_ccount(dc); |
747 |
gen_helper_waiti(cpu_env, pc, intlevel); |
748 |
tcg_temp_free(pc); |
749 |
tcg_temp_free(intlevel); |
750 |
} |
751 |
|
752 |
static void gen_window_check1(DisasContext *dc, unsigned r1) |
753 |
{ |
754 |
if (dc->tb->flags & XTENSA_TBFLAG_EXCM) {
|
755 |
return;
|
756 |
} |
757 |
if (option_enabled(dc, XTENSA_OPTION_WINDOWED_REGISTER) &&
|
758 |
r1 / 4 > dc->used_window) {
|
759 |
TCGv_i32 pc = tcg_const_i32(dc->pc); |
760 |
TCGv_i32 w = tcg_const_i32(r1 / 4);
|
761 |
|
762 |
dc->used_window = r1 / 4;
|
763 |
gen_advance_ccount(dc); |
764 |
gen_helper_window_check(cpu_env, pc, w); |
765 |
|
766 |
tcg_temp_free(w); |
767 |
tcg_temp_free(pc); |
768 |
} |
769 |
} |
770 |
|
771 |
static void gen_window_check2(DisasContext *dc, unsigned r1, unsigned r2) |
772 |
{ |
773 |
gen_window_check1(dc, r1 > r2 ? r1 : r2); |
774 |
} |
775 |
|
776 |
static void gen_window_check3(DisasContext *dc, unsigned r1, unsigned r2, |
777 |
unsigned r3)
|
778 |
{ |
779 |
gen_window_check2(dc, r1, r2 > r3 ? r2 : r3); |
780 |
} |
781 |
|
782 |
static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned) |
783 |
{ |
784 |
TCGv_i32 m = tcg_temp_new_i32(); |
785 |
|
786 |
if (hi) {
|
787 |
(is_unsigned ? tcg_gen_shri_i32 : tcg_gen_sari_i32)(m, v, 16);
|
788 |
} else {
|
789 |
(is_unsigned ? tcg_gen_ext16u_i32 : tcg_gen_ext16s_i32)(m, v); |
790 |
} |
791 |
return m;
|
792 |
} |
793 |
|
794 |
static void disas_xtensa_insn(DisasContext *dc) |
795 |
{ |
796 |
#define HAS_OPTION_BITS(opt) do { \ |
797 |
if (!option_bits_enabled(dc, opt)) { \
|
798 |
qemu_log("Option is not enabled %s:%d\n", \
|
799 |
__FILE__, __LINE__); \ |
800 |
goto invalid_opcode; \
|
801 |
} \ |
802 |
} while (0) |
803 |
|
804 |
#define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt))
|
805 |
|
806 |
#define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__) |
807 |
#define RESERVED() do { \ |
808 |
qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
|
809 |
dc->pc, b0, b1, b2, __FILE__, __LINE__); \ |
810 |
goto invalid_opcode; \
|
811 |
} while (0) |
812 |
|
813 |
|
814 |
#ifdef TARGET_WORDS_BIGENDIAN
|
815 |
#define OP0 (((b0) & 0xf0) >> 4) |
816 |
#define OP1 (((b2) & 0xf0) >> 4) |
817 |
#define OP2 ((b2) & 0xf) |
818 |
#define RRR_R ((b1) & 0xf) |
819 |
#define RRR_S (((b1) & 0xf0) >> 4) |
820 |
#define RRR_T ((b0) & 0xf) |
821 |
#else
|
822 |
#define OP0 (((b0) & 0xf)) |
823 |
#define OP1 (((b2) & 0xf)) |
824 |
#define OP2 (((b2) & 0xf0) >> 4) |
825 |
#define RRR_R (((b1) & 0xf0) >> 4) |
826 |
#define RRR_S (((b1) & 0xf)) |
827 |
#define RRR_T (((b0) & 0xf0) >> 4) |
828 |
#endif
|
829 |
#define RRR_X ((RRR_R & 0x4) >> 2) |
830 |
#define RRR_Y ((RRR_T & 0x4) >> 2) |
831 |
#define RRR_W (RRR_R & 0x3) |
832 |
|
833 |
#define RRRN_R RRR_R
|
834 |
#define RRRN_S RRR_S
|
835 |
#define RRRN_T RRR_T
|
836 |
|
837 |
#define RRI8_R RRR_R
|
838 |
#define RRI8_S RRR_S
|
839 |
#define RRI8_T RRR_T
|
840 |
#define RRI8_IMM8 (b2)
|
841 |
#define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8) |
842 |
|
843 |
#ifdef TARGET_WORDS_BIGENDIAN
|
844 |
#define RI16_IMM16 (((b1) << 8) | (b2)) |
845 |
#else
|
846 |
#define RI16_IMM16 (((b2) << 8) | (b1)) |
847 |
#endif
|
848 |
|
849 |
#ifdef TARGET_WORDS_BIGENDIAN
|
850 |
#define CALL_N (((b0) & 0xc) >> 2) |
851 |
#define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2)) |
852 |
#else
|
853 |
#define CALL_N (((b0) & 0x30) >> 4) |
854 |
#define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10)) |
855 |
#endif
|
856 |
#define CALL_OFFSET_SE \
|
857 |
(((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET) |
858 |
|
859 |
#define CALLX_N CALL_N
|
860 |
#ifdef TARGET_WORDS_BIGENDIAN
|
861 |
#define CALLX_M ((b0) & 0x3) |
862 |
#else
|
863 |
#define CALLX_M (((b0) & 0xc0) >> 6) |
864 |
#endif
|
865 |
#define CALLX_S RRR_S
|
866 |
|
867 |
#define BRI12_M CALLX_M
|
868 |
#define BRI12_S RRR_S
|
869 |
#ifdef TARGET_WORDS_BIGENDIAN
|
870 |
#define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2)) |
871 |
#else
|
872 |
#define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4)) |
873 |
#endif
|
874 |
#define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12) |
875 |
|
876 |
#define BRI8_M BRI12_M
|
877 |
#define BRI8_R RRI8_R
|
878 |
#define BRI8_S RRI8_S
|
879 |
#define BRI8_IMM8 RRI8_IMM8
|
880 |
#define BRI8_IMM8_SE RRI8_IMM8_SE
|
881 |
|
882 |
#define RSR_SR (b1)
|
883 |
|
884 |
uint8_t b0 = cpu_ldub_code(cpu_single_env, dc->pc); |
885 |
uint8_t b1 = cpu_ldub_code(cpu_single_env, dc->pc + 1);
|
886 |
uint8_t b2 = 0;
|
887 |
|
888 |
static const uint32_t B4CONST[] = { |
889 |
0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256 |
890 |
}; |
891 |
|
892 |
static const uint32_t B4CONSTU[] = { |
893 |
32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256 |
894 |
}; |
895 |
|
896 |
if (OP0 >= 8) { |
897 |
dc->next_pc = dc->pc + 2;
|
898 |
HAS_OPTION(XTENSA_OPTION_CODE_DENSITY); |
899 |
} else {
|
900 |
dc->next_pc = dc->pc + 3;
|
901 |
b2 = cpu_ldub_code(cpu_single_env, dc->pc + 2);
|
902 |
} |
903 |
|
904 |
switch (OP0) {
|
905 |
case 0: /*QRST*/ |
906 |
switch (OP1) {
|
907 |
case 0: /*RST0*/ |
908 |
switch (OP2) {
|
909 |
case 0: /*ST0*/ |
910 |
if ((RRR_R & 0xc) == 0x8) { |
911 |
HAS_OPTION(XTENSA_OPTION_BOOLEAN); |
912 |
} |
913 |
|
914 |
switch (RRR_R) {
|
915 |
case 0: /*SNM0*/ |
916 |
switch (CALLX_M) {
|
917 |
case 0: /*ILL*/ |
918 |
gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); |
919 |
break;
|
920 |
|
921 |
case 1: /*reserved*/ |
922 |
RESERVED(); |
923 |
break;
|
924 |
|
925 |
case 2: /*JR*/ |
926 |
switch (CALLX_N) {
|
927 |
case 0: /*RET*/ |
928 |
case 2: /*JX*/ |
929 |
gen_window_check1(dc, CALLX_S); |
930 |
gen_jump(dc, cpu_R[CALLX_S]); |
931 |
break;
|
932 |
|
933 |
case 1: /*RETWw*/ |
934 |
HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); |
935 |
{ |
936 |
TCGv_i32 tmp = tcg_const_i32(dc->pc); |
937 |
gen_advance_ccount(dc); |
938 |
gen_helper_retw(tmp, cpu_env, tmp); |
939 |
gen_jump(dc, tmp); |
940 |
tcg_temp_free(tmp); |
941 |
} |
942 |
break;
|
943 |
|
944 |
case 3: /*reserved*/ |
945 |
RESERVED(); |
946 |
break;
|
947 |
} |
948 |
break;
|
949 |
|
950 |
case 3: /*CALLX*/ |
951 |
gen_window_check2(dc, CALLX_S, CALLX_N << 2);
|
952 |
switch (CALLX_N) {
|
953 |
case 0: /*CALLX0*/ |
954 |
{ |
955 |
TCGv_i32 tmp = tcg_temp_new_i32(); |
956 |
tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]); |
957 |
tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
|
958 |
gen_jump(dc, tmp); |
959 |
tcg_temp_free(tmp); |
960 |
} |
961 |
break;
|
962 |
|
963 |
case 1: /*CALLX4w*/ |
964 |
case 2: /*CALLX8w*/ |
965 |
case 3: /*CALLX12w*/ |
966 |
HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); |
967 |
{ |
968 |
TCGv_i32 tmp = tcg_temp_new_i32(); |
969 |
|
970 |
tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]); |
971 |
gen_callw(dc, CALLX_N, tmp); |
972 |
tcg_temp_free(tmp); |
973 |
} |
974 |
break;
|
975 |
} |
976 |
break;
|
977 |
} |
978 |
break;
|
979 |
|
980 |
case 1: /*MOVSPw*/ |
981 |
HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); |
982 |
gen_window_check2(dc, RRR_T, RRR_S); |
983 |
{ |
984 |
TCGv_i32 pc = tcg_const_i32(dc->pc); |
985 |
gen_advance_ccount(dc); |
986 |
gen_helper_movsp(cpu_env, pc); |
987 |
tcg_gen_mov_i32(cpu_R[RRR_T], cpu_R[RRR_S]); |
988 |
tcg_temp_free(pc); |
989 |
} |
990 |
break;
|
991 |
|
992 |
case 2: /*SYNC*/ |
993 |
switch (RRR_T) {
|
994 |
case 0: /*ISYNC*/ |
995 |
break;
|
996 |
|
997 |
case 1: /*RSYNC*/ |
998 |
break;
|
999 |
|
1000 |
case 2: /*ESYNC*/ |
1001 |
break;
|
1002 |
|
1003 |
case 3: /*DSYNC*/ |
1004 |
break;
|
1005 |
|
1006 |
case 8: /*EXCW*/ |
1007 |
HAS_OPTION(XTENSA_OPTION_EXCEPTION); |
1008 |
break;
|
1009 |
|
1010 |
case 12: /*MEMW*/ |
1011 |
break;
|
1012 |
|
1013 |
case 13: /*EXTW*/ |
1014 |
break;
|
1015 |
|
1016 |
case 15: /*NOP*/ |
1017 |
break;
|
1018 |
|
1019 |
default: /*reserved*/ |
1020 |
RESERVED(); |
1021 |
break;
|
1022 |
} |
1023 |
break;
|
1024 |
|
1025 |
case 3: /*RFEIx*/ |
1026 |
switch (RRR_T) {
|
1027 |
case 0: /*RFETx*/ |
1028 |
HAS_OPTION(XTENSA_OPTION_EXCEPTION); |
1029 |
switch (RRR_S) {
|
1030 |
case 0: /*RFEx*/ |
1031 |
gen_check_privilege(dc); |
1032 |
tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); |
1033 |
gen_helper_check_interrupts(cpu_env); |
1034 |
gen_jump(dc, cpu_SR[EPC1]); |
1035 |
break;
|
1036 |
|
1037 |
case 1: /*RFUEx*/ |
1038 |
RESERVED(); |
1039 |
break;
|
1040 |
|
1041 |
case 2: /*RFDEx*/ |
1042 |
gen_check_privilege(dc); |
1043 |
gen_jump(dc, cpu_SR[ |
1044 |
dc->config->ndepc ? DEPC : EPC1]); |
1045 |
break;
|
1046 |
|
1047 |
case 4: /*RFWOw*/ |
1048 |
case 5: /*RFWUw*/ |
1049 |
HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); |
1050 |
gen_check_privilege(dc); |
1051 |
{ |
1052 |
TCGv_i32 tmp = tcg_const_i32(1);
|
1053 |
|
1054 |
tcg_gen_andi_i32( |
1055 |
cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); |
1056 |
tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]); |
1057 |
|
1058 |
if (RRR_S == 4) { |
1059 |
tcg_gen_andc_i32(cpu_SR[WINDOW_START], |
1060 |
cpu_SR[WINDOW_START], tmp); |
1061 |
} else {
|
1062 |
tcg_gen_or_i32(cpu_SR[WINDOW_START], |
1063 |
cpu_SR[WINDOW_START], tmp); |
1064 |
} |
1065 |
|
1066 |
gen_helper_restore_owb(cpu_env); |
1067 |
gen_helper_check_interrupts(cpu_env); |
1068 |
gen_jump(dc, cpu_SR[EPC1]); |
1069 |
|
1070 |
tcg_temp_free(tmp); |
1071 |
} |
1072 |
break;
|
1073 |
|
1074 |
default: /*reserved*/ |
1075 |
RESERVED(); |
1076 |
break;
|
1077 |
} |
1078 |
break;
|
1079 |
|
1080 |
case 1: /*RFIx*/ |
1081 |
HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT); |
1082 |
if (RRR_S >= 2 && RRR_S <= dc->config->nlevel) { |
1083 |
gen_check_privilege(dc); |
1084 |
tcg_gen_mov_i32(cpu_SR[PS], |
1085 |
cpu_SR[EPS2 + RRR_S - 2]);
|
1086 |
gen_helper_check_interrupts(cpu_env); |
1087 |
gen_jump(dc, cpu_SR[EPC1 + RRR_S - 1]);
|
1088 |
} else {
|
1089 |
qemu_log("RFI %d is illegal\n", RRR_S);
|
1090 |
gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); |
1091 |
} |
1092 |
break;
|
1093 |
|
1094 |
case 2: /*RFME*/ |
1095 |
TBD(); |
1096 |
break;
|
1097 |
|
1098 |
default: /*reserved*/ |
1099 |
RESERVED(); |
1100 |
break;
|
1101 |
|
1102 |
} |
1103 |
break;
|
1104 |
|
1105 |
case 4: /*BREAKx*/ |
1106 |
HAS_OPTION(XTENSA_OPTION_DEBUG); |
1107 |
if (dc->debug) {
|
1108 |
gen_debug_exception(dc, DEBUGCAUSE_BI); |
1109 |
} |
1110 |
break;
|
1111 |
|
1112 |
case 5: /*SYSCALLx*/ |
1113 |
HAS_OPTION(XTENSA_OPTION_EXCEPTION); |
1114 |
switch (RRR_S) {
|
1115 |
case 0: /*SYSCALLx*/ |
1116 |
gen_exception_cause(dc, SYSCALL_CAUSE); |
1117 |
break;
|
1118 |
|
1119 |
case 1: /*SIMCALL*/ |
1120 |
if (semihosting_enabled) {
|
1121 |
gen_check_privilege(dc); |
1122 |
gen_helper_simcall(cpu_env); |
1123 |
} else {
|
1124 |
qemu_log("SIMCALL but semihosting is disabled\n");
|
1125 |
gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); |
1126 |
} |
1127 |
break;
|
1128 |
|
1129 |
default:
|
1130 |
RESERVED(); |
1131 |
break;
|
1132 |
} |
1133 |
break;
|
1134 |
|
1135 |
case 6: /*RSILx*/ |
1136 |
HAS_OPTION(XTENSA_OPTION_INTERRUPT); |
1137 |
gen_check_privilege(dc); |
1138 |
gen_window_check1(dc, RRR_T); |
1139 |
tcg_gen_mov_i32(cpu_R[RRR_T], cpu_SR[PS]); |
1140 |
tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL); |
1141 |
tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], RRR_S); |
1142 |
gen_helper_check_interrupts(cpu_env); |
1143 |
gen_jumpi_check_loop_end(dc, 0);
|
1144 |
break;
|
1145 |
|
1146 |
case 7: /*WAITIx*/ |
1147 |
HAS_OPTION(XTENSA_OPTION_INTERRUPT); |
1148 |
gen_check_privilege(dc); |
1149 |
gen_waiti(dc, RRR_S); |
1150 |
break;
|
1151 |
|
1152 |
case 8: /*ANY4p*/ |
1153 |
case 9: /*ALL4p*/ |
1154 |
case 10: /*ANY8p*/ |
1155 |
case 11: /*ALL8p*/ |
1156 |
HAS_OPTION(XTENSA_OPTION_BOOLEAN); |
1157 |
{ |
1158 |
const unsigned shift = (RRR_R & 2) ? 8 : 4; |
1159 |
TCGv_i32 mask = tcg_const_i32( |
1160 |
((1 << shift) - 1) << RRR_S); |
1161 |
TCGv_i32 tmp = tcg_temp_new_i32(); |
1162 |
|
1163 |
tcg_gen_and_i32(tmp, cpu_SR[BR], mask); |
1164 |
if (RRR_R & 1) { /*ALL*/ |
1165 |
tcg_gen_addi_i32(tmp, tmp, 1 << RRR_S);
|
1166 |
} else { /*ANY*/ |
1167 |
tcg_gen_add_i32(tmp, tmp, mask); |
1168 |
} |
1169 |
tcg_gen_shri_i32(tmp, tmp, RRR_S + shift); |
1170 |
tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], |
1171 |
tmp, RRR_T, 1);
|
1172 |
tcg_temp_free(mask); |
1173 |
tcg_temp_free(tmp); |
1174 |
} |
1175 |
break;
|
1176 |
|
1177 |
default: /*reserved*/ |
1178 |
RESERVED(); |
1179 |
break;
|
1180 |
|
1181 |
} |
1182 |
break;
|
1183 |
|
1184 |
case 1: /*AND*/ |
1185 |
gen_window_check3(dc, RRR_R, RRR_S, RRR_T); |
1186 |
tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); |
1187 |
break;
|
1188 |
|
1189 |
case 2: /*OR*/ |
1190 |
gen_window_check3(dc, RRR_R, RRR_S, RRR_T); |
1191 |
tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); |
1192 |
break;
|
1193 |
|
1194 |
case 3: /*XOR*/ |
1195 |
gen_window_check3(dc, RRR_R, RRR_S, RRR_T); |
1196 |
tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); |
1197 |
break;
|
1198 |
|
1199 |
case 4: /*ST1*/ |
1200 |
switch (RRR_R) {
|
1201 |
case 0: /*SSR*/ |
1202 |
gen_window_check1(dc, RRR_S); |
1203 |
gen_right_shift_sar(dc, cpu_R[RRR_S]); |
1204 |
break;
|
1205 |
|
1206 |
case 1: /*SSL*/ |
1207 |
gen_window_check1(dc, RRR_S); |
1208 |
gen_left_shift_sar(dc, cpu_R[RRR_S]); |
1209 |
break;
|
1210 |
|
1211 |
case 2: /*SSA8L*/ |
1212 |
gen_window_check1(dc, RRR_S); |
1213 |
{ |
1214 |
TCGv_i32 tmp = tcg_temp_new_i32(); |
1215 |
tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
|
1216 |
gen_right_shift_sar(dc, tmp); |
1217 |
tcg_temp_free(tmp); |
1218 |
} |
1219 |
break;
|
1220 |
|
1221 |
case 3: /*SSA8B*/ |
1222 |
gen_window_check1(dc, RRR_S); |
1223 |
{ |
1224 |
TCGv_i32 tmp = tcg_temp_new_i32(); |
1225 |
tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
|
1226 |
gen_left_shift_sar(dc, tmp); |
1227 |
tcg_temp_free(tmp); |
1228 |
} |
1229 |
break;
|
1230 |
|
1231 |
case 4: /*SSAI*/ |
1232 |
{ |
1233 |
TCGv_i32 tmp = tcg_const_i32( |
1234 |
RRR_S | ((RRR_T & 1) << 4)); |
1235 |
gen_right_shift_sar(dc, tmp); |
1236 |
tcg_temp_free(tmp); |
1237 |
} |
1238 |
break;
|
1239 |
|
1240 |
case 6: /*RER*/ |
1241 |
TBD(); |
1242 |
break;
|
1243 |
|
1244 |
case 7: /*WER*/ |
1245 |
TBD(); |
1246 |
break;
|
1247 |
|
1248 |
case 8: /*ROTWw*/ |
1249 |
HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); |
1250 |
gen_check_privilege(dc); |
1251 |
{ |
1252 |
TCGv_i32 tmp = tcg_const_i32( |
1253 |
RRR_T | ((RRR_T & 8) ? 0xfffffff0 : 0)); |
1254 |
gen_helper_rotw(cpu_env, tmp); |
1255 |
tcg_temp_free(tmp); |
1256 |
reset_used_window(dc); |
1257 |
} |
1258 |
break;
|
1259 |
|
1260 |
case 14: /*NSAu*/ |
1261 |
HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA); |
1262 |
gen_window_check2(dc, RRR_S, RRR_T); |
1263 |
gen_helper_nsa(cpu_R[RRR_T], cpu_R[RRR_S]); |
1264 |
break;
|
1265 |
|
1266 |
case 15: /*NSAUu*/ |
1267 |
HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA); |
1268 |
gen_window_check2(dc, RRR_S, RRR_T); |
1269 |
gen_helper_nsau(cpu_R[RRR_T], cpu_R[RRR_S]); |
1270 |
break;
|
1271 |
|
1272 |
default: /*reserved*/ |
1273 |
RESERVED(); |
1274 |
break;
|
1275 |
} |
1276 |
break;
|
1277 |
|
1278 |
case 5: /*TLB*/ |
1279 |
HAS_OPTION_BITS( |
1280 |
XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) | |
1281 |
XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) | |
1282 |
XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION)); |
1283 |
gen_check_privilege(dc); |
1284 |
gen_window_check2(dc, RRR_S, RRR_T); |
1285 |
{ |
1286 |
TCGv_i32 dtlb = tcg_const_i32((RRR_R & 8) != 0); |
1287 |
|
1288 |
switch (RRR_R & 7) { |
1289 |
case 3: /*RITLB0*/ /*RDTLB0*/ |
1290 |
gen_helper_rtlb0(cpu_R[RRR_T], |
1291 |
cpu_env, cpu_R[RRR_S], dtlb); |
1292 |
break;
|
1293 |
|
1294 |
case 4: /*IITLB*/ /*IDTLB*/ |
1295 |
gen_helper_itlb(cpu_env, cpu_R[RRR_S], dtlb); |
1296 |
/* This could change memory mapping, so exit tb */
|
1297 |
gen_jumpi_check_loop_end(dc, -1);
|
1298 |
break;
|
1299 |
|
1300 |
case 5: /*PITLB*/ /*PDTLB*/ |
1301 |
tcg_gen_movi_i32(cpu_pc, dc->pc); |
1302 |
gen_helper_ptlb(cpu_R[RRR_T], |
1303 |
cpu_env, cpu_R[RRR_S], dtlb); |
1304 |
break;
|
1305 |
|
1306 |
case 6: /*WITLB*/ /*WDTLB*/ |
1307 |
gen_helper_wtlb( |
1308 |
cpu_env, cpu_R[RRR_T], cpu_R[RRR_S], dtlb); |
1309 |
/* This could change memory mapping, so exit tb */
|
1310 |
gen_jumpi_check_loop_end(dc, -1);
|
1311 |
break;
|
1312 |
|
1313 |
case 7: /*RITLB1*/ /*RDTLB1*/ |
1314 |
gen_helper_rtlb1(cpu_R[RRR_T], |
1315 |
cpu_env, cpu_R[RRR_S], dtlb); |
1316 |
break;
|
1317 |
|
1318 |
default:
|
1319 |
tcg_temp_free(dtlb); |
1320 |
RESERVED(); |
1321 |
break;
|
1322 |
} |
1323 |
tcg_temp_free(dtlb); |
1324 |
} |
1325 |
break;
|
1326 |
|
1327 |
case 6: /*RT0*/ |
1328 |
gen_window_check2(dc, RRR_R, RRR_T); |
1329 |
switch (RRR_S) {
|
1330 |
case 0: /*NEG*/ |
1331 |
tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]); |
1332 |
break;
|
1333 |
|
1334 |
case 1: /*ABS*/ |
1335 |
{ |
1336 |
int label = gen_new_label();
|
1337 |
tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_T]); |
1338 |
tcg_gen_brcondi_i32( |
1339 |
TCG_COND_GE, cpu_R[RRR_R], 0, label);
|
1340 |
tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]); |
1341 |
gen_set_label(label); |
1342 |
} |
1343 |
break;
|
1344 |
|
1345 |
default: /*reserved*/ |
1346 |
RESERVED(); |
1347 |
break;
|
1348 |
} |
1349 |
break;
|
1350 |
|
1351 |
case 7: /*reserved*/ |
1352 |
RESERVED(); |
1353 |
break;
|
1354 |
|
1355 |
case 8: /*ADD*/ |
1356 |
gen_window_check3(dc, RRR_R, RRR_S, RRR_T); |
1357 |
tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); |
1358 |
break;
|
1359 |
|
1360 |
case 9: /*ADD**/ |
1361 |
case 10: |
1362 |
case 11: |
1363 |
gen_window_check3(dc, RRR_R, RRR_S, RRR_T); |
1364 |
{ |
1365 |
TCGv_i32 tmp = tcg_temp_new_i32(); |
1366 |
tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8);
|
1367 |
tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]); |
1368 |
tcg_temp_free(tmp); |
1369 |
} |
1370 |
break;
|
1371 |
|
1372 |
case 12: /*SUB*/ |
1373 |
gen_window_check3(dc, RRR_R, RRR_S, RRR_T); |
1374 |
tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); |
1375 |
break;
|
1376 |
|
1377 |
case 13: /*SUB**/ |
1378 |
case 14: |
1379 |
case 15: |
1380 |
gen_window_check3(dc, RRR_R, RRR_S, RRR_T); |
1381 |
{ |
1382 |
TCGv_i32 tmp = tcg_temp_new_i32(); |
1383 |
tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12);
|
1384 |
tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]); |
1385 |
tcg_temp_free(tmp); |
1386 |
} |
1387 |
break;
|
1388 |
} |
1389 |
break;
|
1390 |
|
1391 |
case 1: /*RST1*/ |
1392 |
switch (OP2) {
|
1393 |
case 0: /*SLLI*/ |
1394 |
case 1: |
1395 |
gen_window_check2(dc, RRR_R, RRR_S); |
1396 |
tcg_gen_shli_i32(cpu_R[RRR_R], cpu_R[RRR_S], |
1397 |
32 - (RRR_T | ((OP2 & 1) << 4))); |
1398 |
break;
|
1399 |
|
1400 |
case 2: /*SRAI*/ |
1401 |
case 3: |
1402 |
gen_window_check2(dc, RRR_R, RRR_T); |
1403 |
tcg_gen_sari_i32(cpu_R[RRR_R], cpu_R[RRR_T], |
1404 |
RRR_S | ((OP2 & 1) << 4)); |
1405 |
break;
|
1406 |
|
1407 |
case 4: /*SRLI*/ |
1408 |
gen_window_check2(dc, RRR_R, RRR_T); |
1409 |
tcg_gen_shri_i32(cpu_R[RRR_R], cpu_R[RRR_T], RRR_S); |
1410 |
break;
|
1411 |
|
1412 |
case 6: /*XSR*/ |
1413 |
{ |
1414 |
TCGv_i32 tmp = tcg_temp_new_i32(); |
1415 |
if (RSR_SR >= 64) { |
1416 |
gen_check_privilege(dc); |
1417 |
} |
1418 |
gen_window_check1(dc, RRR_T); |
1419 |
tcg_gen_mov_i32(tmp, cpu_R[RRR_T]); |
1420 |
gen_rsr(dc, cpu_R[RRR_T], RSR_SR); |
1421 |
gen_wsr(dc, RSR_SR, tmp); |
1422 |
tcg_temp_free(tmp); |
1423 |
if (!sregnames[RSR_SR]) {
|
1424 |
TBD(); |
1425 |
} |
1426 |
} |
1427 |
break;
|
1428 |
|
1429 |
/*
|
1430 |
* Note: 64 bit ops are used here solely because SAR values
|
1431 |
* have range 0..63
|
1432 |
*/
|
1433 |
#define gen_shift_reg(cmd, reg) do { \ |
1434 |
TCGv_i64 tmp = tcg_temp_new_i64(); \ |
1435 |
tcg_gen_extu_i32_i64(tmp, reg); \ |
1436 |
tcg_gen_##cmd##_i64(v, v, tmp); \ |
1437 |
tcg_gen_trunc_i64_i32(cpu_R[RRR_R], v); \ |
1438 |
tcg_temp_free_i64(v); \ |
1439 |
tcg_temp_free_i64(tmp); \ |
1440 |
} while (0) |
1441 |
|
1442 |
#define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
|
1443 |
|
1444 |
case 8: /*SRC*/ |
1445 |
gen_window_check3(dc, RRR_R, RRR_S, RRR_T); |
1446 |
{ |
1447 |
TCGv_i64 v = tcg_temp_new_i64(); |
1448 |
tcg_gen_concat_i32_i64(v, cpu_R[RRR_T], cpu_R[RRR_S]); |
1449 |
gen_shift(shr); |
1450 |
} |
1451 |
break;
|
1452 |
|
1453 |
case 9: /*SRL*/ |
1454 |
gen_window_check2(dc, RRR_R, RRR_T); |
1455 |
if (dc->sar_5bit) {
|
1456 |
tcg_gen_shr_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]); |
1457 |
} else {
|
1458 |
TCGv_i64 v = tcg_temp_new_i64(); |
1459 |
tcg_gen_extu_i32_i64(v, cpu_R[RRR_T]); |
1460 |
gen_shift(shr); |
1461 |
} |
1462 |
break;
|
1463 |
|
1464 |
case 10: /*SLL*/ |
1465 |
gen_window_check2(dc, RRR_R, RRR_S); |
1466 |
if (dc->sar_m32_5bit) {
|
1467 |
tcg_gen_shl_i32(cpu_R[RRR_R], cpu_R[RRR_S], dc->sar_m32); |
1468 |
} else {
|
1469 |
TCGv_i64 v = tcg_temp_new_i64(); |
1470 |
TCGv_i32 s = tcg_const_i32(32);
|
1471 |
tcg_gen_sub_i32(s, s, cpu_SR[SAR]); |
1472 |
tcg_gen_andi_i32(s, s, 0x3f);
|
1473 |
tcg_gen_extu_i32_i64(v, cpu_R[RRR_S]); |
1474 |
gen_shift_reg(shl, s); |
1475 |
tcg_temp_free(s); |
1476 |
} |
1477 |
break;
|
1478 |
|
1479 |
case 11: /*SRA*/ |
1480 |
gen_window_check2(dc, RRR_R, RRR_T); |
1481 |
if (dc->sar_5bit) {
|
1482 |
tcg_gen_sar_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]); |
1483 |
} else {
|
1484 |
TCGv_i64 v = tcg_temp_new_i64(); |
1485 |
tcg_gen_ext_i32_i64(v, cpu_R[RRR_T]); |
1486 |
gen_shift(sar); |
1487 |
} |
1488 |
break;
|
1489 |
#undef gen_shift
|
1490 |
#undef gen_shift_reg
|
1491 |
|
1492 |
case 12: /*MUL16U*/ |
1493 |
HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL); |
1494 |
gen_window_check3(dc, RRR_R, RRR_S, RRR_T); |
1495 |
{ |
1496 |
TCGv_i32 v1 = tcg_temp_new_i32(); |
1497 |
TCGv_i32 v2 = tcg_temp_new_i32(); |
1498 |
tcg_gen_ext16u_i32(v1, cpu_R[RRR_S]); |
1499 |
tcg_gen_ext16u_i32(v2, cpu_R[RRR_T]); |
1500 |
tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2); |
1501 |
tcg_temp_free(v2); |
1502 |
tcg_temp_free(v1); |
1503 |
} |
1504 |
break;
|
1505 |
|
1506 |
case 13: /*MUL16S*/ |
1507 |
HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL); |
1508 |
gen_window_check3(dc, RRR_R, RRR_S, RRR_T); |
1509 |
{ |
1510 |
TCGv_i32 v1 = tcg_temp_new_i32(); |
1511 |
TCGv_i32 v2 = tcg_temp_new_i32(); |
1512 |
tcg_gen_ext16s_i32(v1, cpu_R[RRR_S]); |
1513 |
tcg_gen_ext16s_i32(v2, cpu_R[RRR_T]); |
1514 |
tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2); |
1515 |
tcg_temp_free(v2); |
1516 |
tcg_temp_free(v1); |
1517 |
} |
1518 |
break;
|
1519 |
|
1520 |
default: /*reserved*/ |
1521 |
RESERVED(); |
1522 |
break;
|
1523 |
} |
1524 |
break;
|
1525 |
|
1526 |
case 2: /*RST2*/ |
1527 |
if (OP2 >= 8) { |
1528 |
gen_window_check3(dc, RRR_R, RRR_S, RRR_T); |
1529 |
} |
1530 |
|
1531 |
if (OP2 >= 12) { |
1532 |
HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV); |
1533 |
int label = gen_new_label();
|
1534 |
tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label);
|
1535 |
gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE); |
1536 |
gen_set_label(label); |
1537 |
} |
1538 |
|
1539 |
switch (OP2) {
|
1540 |
#define BOOLEAN_LOGIC(fn, r, s, t) \
|
1541 |
do { \
|
1542 |
HAS_OPTION(XTENSA_OPTION_BOOLEAN); \ |
1543 |
TCGv_i32 tmp1 = tcg_temp_new_i32(); \ |
1544 |
TCGv_i32 tmp2 = tcg_temp_new_i32(); \ |
1545 |
\ |
1546 |
tcg_gen_shri_i32(tmp1, cpu_SR[BR], s); \ |
1547 |
tcg_gen_shri_i32(tmp2, cpu_SR[BR], t); \ |
1548 |
tcg_gen_##fn##_i32(tmp1, tmp1, tmp2); \ |
1549 |
tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, r, 1); \
|
1550 |
tcg_temp_free(tmp1); \ |
1551 |
tcg_temp_free(tmp2); \ |
1552 |
} while (0) |
1553 |
|
1554 |
case 0: /*ANDBp*/ |
1555 |
BOOLEAN_LOGIC(and, RRR_R, RRR_S, RRR_T); |
1556 |
break;
|
1557 |
|
1558 |
case 1: /*ANDBCp*/ |
1559 |
BOOLEAN_LOGIC(andc, RRR_R, RRR_S, RRR_T); |
1560 |
break;
|
1561 |
|
1562 |
case 2: /*ORBp*/ |
1563 |
BOOLEAN_LOGIC(or, RRR_R, RRR_S, RRR_T); |
1564 |
break;
|
1565 |
|
1566 |
case 3: /*ORBCp*/ |
1567 |
BOOLEAN_LOGIC(orc, RRR_R, RRR_S, RRR_T); |
1568 |
break;
|
1569 |
|
1570 |
case 4: /*XORBp*/ |
1571 |
BOOLEAN_LOGIC(xor, RRR_R, RRR_S, RRR_T); |
1572 |
break;
|
1573 |
|
1574 |
#undef BOOLEAN_LOGIC
|
1575 |
|
1576 |
case 8: /*MULLi*/ |
1577 |
HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL); |
1578 |
tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); |
1579 |
break;
|
1580 |
|
1581 |
case 10: /*MULUHi*/ |
1582 |
case 11: /*MULSHi*/ |
1583 |
HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH); |
1584 |
{ |
1585 |
TCGv_i64 r = tcg_temp_new_i64(); |
1586 |
TCGv_i64 s = tcg_temp_new_i64(); |
1587 |
TCGv_i64 t = tcg_temp_new_i64(); |
1588 |
|
1589 |
if (OP2 == 10) { |
1590 |
tcg_gen_extu_i32_i64(s, cpu_R[RRR_S]); |
1591 |
tcg_gen_extu_i32_i64(t, cpu_R[RRR_T]); |
1592 |
} else {
|
1593 |
tcg_gen_ext_i32_i64(s, cpu_R[RRR_S]); |
1594 |
tcg_gen_ext_i32_i64(t, cpu_R[RRR_T]); |
1595 |
} |
1596 |
tcg_gen_mul_i64(r, s, t); |
1597 |
tcg_gen_shri_i64(r, r, 32);
|
1598 |
tcg_gen_trunc_i64_i32(cpu_R[RRR_R], r); |
1599 |
|
1600 |
tcg_temp_free_i64(r); |
1601 |
tcg_temp_free_i64(s); |
1602 |
tcg_temp_free_i64(t); |
1603 |
} |
1604 |
break;
|
1605 |
|
1606 |
case 12: /*QUOUi*/ |
1607 |
tcg_gen_divu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); |
1608 |
break;
|
1609 |
|
1610 |
case 13: /*QUOSi*/ |
1611 |
case 15: /*REMSi*/ |
1612 |
{ |
1613 |
int label1 = gen_new_label();
|
1614 |
int label2 = gen_new_label();
|
1615 |
|
1616 |
tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_S], 0x80000000,
|
1617 |
label1); |
1618 |
tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0xffffffff,
|
1619 |
label1); |
1620 |
tcg_gen_movi_i32(cpu_R[RRR_R], |
1621 |
OP2 == 13 ? 0x80000000 : 0); |
1622 |
tcg_gen_br(label2); |
1623 |
gen_set_label(label1); |
1624 |
if (OP2 == 13) { |
1625 |
tcg_gen_div_i32(cpu_R[RRR_R], |
1626 |
cpu_R[RRR_S], cpu_R[RRR_T]); |
1627 |
} else {
|
1628 |
tcg_gen_rem_i32(cpu_R[RRR_R], |
1629 |
cpu_R[RRR_S], cpu_R[RRR_T]); |
1630 |
} |
1631 |
gen_set_label(label2); |
1632 |
} |
1633 |
break;
|
1634 |
|
1635 |
case 14: /*REMUi*/ |
1636 |
tcg_gen_remu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); |
1637 |
break;
|
1638 |
|
1639 |
default: /*reserved*/ |
1640 |
RESERVED(); |
1641 |
break;
|
1642 |
} |
1643 |
break;
|
1644 |
|
1645 |
case 3: /*RST3*/ |
1646 |
switch (OP2) {
|
1647 |
case 0: /*RSR*/ |
1648 |
if (RSR_SR >= 64) { |
1649 |
gen_check_privilege(dc); |
1650 |
} |
1651 |
gen_window_check1(dc, RRR_T); |
1652 |
gen_rsr(dc, cpu_R[RRR_T], RSR_SR); |
1653 |
if (!sregnames[RSR_SR]) {
|
1654 |
TBD(); |
1655 |
} |
1656 |
break;
|
1657 |
|
1658 |
case 1: /*WSR*/ |
1659 |
if (RSR_SR >= 64) { |
1660 |
gen_check_privilege(dc); |
1661 |
} |
1662 |
gen_window_check1(dc, RRR_T); |
1663 |
gen_wsr(dc, RSR_SR, cpu_R[RRR_T]); |
1664 |
if (!sregnames[RSR_SR]) {
|
1665 |
TBD(); |
1666 |
} |
1667 |
break;
|
1668 |
|
1669 |
case 2: /*SEXTu*/ |
1670 |
HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT); |
1671 |
gen_window_check2(dc, RRR_R, RRR_S); |
1672 |
{ |
1673 |
int shift = 24 - RRR_T; |
1674 |
|
1675 |
if (shift == 24) { |
1676 |
tcg_gen_ext8s_i32(cpu_R[RRR_R], cpu_R[RRR_S]); |
1677 |
} else if (shift == 16) { |
1678 |
tcg_gen_ext16s_i32(cpu_R[RRR_R], cpu_R[RRR_S]); |
1679 |
} else {
|
1680 |
TCGv_i32 tmp = tcg_temp_new_i32(); |
1681 |
tcg_gen_shli_i32(tmp, cpu_R[RRR_S], shift); |
1682 |
tcg_gen_sari_i32(cpu_R[RRR_R], tmp, shift); |
1683 |
tcg_temp_free(tmp); |
1684 |
} |
1685 |
} |
1686 |
break;
|
1687 |
|
1688 |
case 3: /*CLAMPSu*/ |
1689 |
HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS); |
1690 |
gen_window_check2(dc, RRR_R, RRR_S); |
1691 |
{ |
1692 |
TCGv_i32 tmp1 = tcg_temp_new_i32(); |
1693 |
TCGv_i32 tmp2 = tcg_temp_new_i32(); |
1694 |
int label = gen_new_label();
|
1695 |
|
1696 |
tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 24 - RRR_T);
|
1697 |
tcg_gen_xor_i32(tmp2, tmp1, cpu_R[RRR_S]); |
1698 |
tcg_gen_andi_i32(tmp2, tmp2, 0xffffffff << (RRR_T + 7)); |
1699 |
tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]); |
1700 |
tcg_gen_brcondi_i32(TCG_COND_EQ, tmp2, 0, label);
|
1701 |
|
1702 |
tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 31);
|
1703 |
tcg_gen_xori_i32(cpu_R[RRR_R], tmp1, |
1704 |
0xffffffff >> (25 - RRR_T)); |
1705 |
|
1706 |
gen_set_label(label); |
1707 |
|
1708 |
tcg_temp_free(tmp1); |
1709 |
tcg_temp_free(tmp2); |
1710 |
} |
1711 |
break;
|
1712 |
|
1713 |
case 4: /*MINu*/ |
1714 |
case 5: /*MAXu*/ |
1715 |
case 6: /*MINUu*/ |
1716 |
case 7: /*MAXUu*/ |
1717 |
HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX); |
1718 |
gen_window_check3(dc, RRR_R, RRR_S, RRR_T); |
1719 |
{ |
1720 |
static const TCGCond cond[] = { |
1721 |
TCG_COND_LE, |
1722 |
TCG_COND_GE, |
1723 |
TCG_COND_LEU, |
1724 |
TCG_COND_GEU |
1725 |
}; |
1726 |
int label = gen_new_label();
|
1727 |
|
1728 |
if (RRR_R != RRR_T) {
|
1729 |
tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]); |
1730 |
tcg_gen_brcond_i32(cond[OP2 - 4],
|
1731 |
cpu_R[RRR_S], cpu_R[RRR_T], label); |
1732 |
tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_T]); |
1733 |
} else {
|
1734 |
tcg_gen_brcond_i32(cond[OP2 - 4],
|
1735 |
cpu_R[RRR_T], cpu_R[RRR_S], label); |
1736 |
tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]); |
1737 |
} |
1738 |
gen_set_label(label); |
1739 |
} |
1740 |
break;
|
1741 |
|
1742 |
case 8: /*MOVEQZ*/ |
1743 |
case 9: /*MOVNEZ*/ |
1744 |
case 10: /*MOVLTZ*/ |
1745 |
case 11: /*MOVGEZ*/ |
1746 |
gen_window_check3(dc, RRR_R, RRR_S, RRR_T); |
1747 |
{ |
1748 |
static const TCGCond cond[] = { |
1749 |
TCG_COND_NE, |
1750 |
TCG_COND_EQ, |
1751 |
TCG_COND_GE, |
1752 |
TCG_COND_LT |
1753 |
}; |
1754 |
int label = gen_new_label();
|
1755 |
tcg_gen_brcondi_i32(cond[OP2 - 8], cpu_R[RRR_T], 0, label); |
1756 |
tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]); |
1757 |
gen_set_label(label); |
1758 |
} |
1759 |
break;
|
1760 |
|
1761 |
case 12: /*MOVFp*/ |
1762 |
case 13: /*MOVTp*/ |
1763 |
HAS_OPTION(XTENSA_OPTION_BOOLEAN); |
1764 |
gen_window_check2(dc, RRR_R, RRR_S); |
1765 |
{ |
1766 |
int label = gen_new_label();
|
1767 |
TCGv_i32 tmp = tcg_temp_new_i32(); |
1768 |
|
1769 |
tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
|
1770 |
tcg_gen_brcondi_i32( |
1771 |
OP2 & 1 ? TCG_COND_EQ : TCG_COND_NE,
|
1772 |
tmp, 0, label);
|
1773 |
tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]); |
1774 |
gen_set_label(label); |
1775 |
tcg_temp_free(tmp); |
1776 |
} |
1777 |
break;
|
1778 |
|
1779 |
case 14: /*RUR*/ |
1780 |
gen_window_check1(dc, RRR_R); |
1781 |
{ |
1782 |
int st = (RRR_S << 4) + RRR_T; |
1783 |
if (uregnames[st]) {
|
1784 |
tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]); |
1785 |
} else {
|
1786 |
qemu_log("RUR %d not implemented, ", st);
|
1787 |
TBD(); |
1788 |
} |
1789 |
} |
1790 |
break;
|
1791 |
|
1792 |
case 15: /*WUR*/ |
1793 |
gen_window_check1(dc, RRR_T); |
1794 |
if (uregnames[RSR_SR]) {
|
1795 |
gen_wur(RSR_SR, cpu_R[RRR_T]); |
1796 |
} else {
|
1797 |
qemu_log("WUR %d not implemented, ", RSR_SR);
|
1798 |
TBD(); |
1799 |
} |
1800 |
break;
|
1801 |
|
1802 |
} |
1803 |
break;
|
1804 |
|
1805 |
case 4: /*EXTUI*/ |
1806 |
case 5: |
1807 |
gen_window_check2(dc, RRR_R, RRR_T); |
1808 |
{ |
1809 |
int shiftimm = RRR_S | ((OP1 & 1) << 4); |
1810 |
int maskimm = (1 << (OP2 + 1)) - 1; |
1811 |
|
1812 |
TCGv_i32 tmp = tcg_temp_new_i32(); |
1813 |
|
1814 |
if (shiftimm) {
|
1815 |
tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm); |
1816 |
} else {
|
1817 |
tcg_gen_mov_i32(tmp, cpu_R[RRR_T]); |
1818 |
} |
1819 |
|
1820 |
switch (maskimm) {
|
1821 |
case 0xff: |
1822 |
tcg_gen_ext8u_i32(cpu_R[RRR_R], tmp); |
1823 |
break;
|
1824 |
|
1825 |
case 0xffff: |
1826 |
tcg_gen_ext16u_i32(cpu_R[RRR_R], tmp); |
1827 |
break;
|
1828 |
|
1829 |
default:
|
1830 |
tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm); |
1831 |
break;
|
1832 |
} |
1833 |
tcg_temp_free(tmp); |
1834 |
} |
1835 |
break;
|
1836 |
|
1837 |
case 6: /*CUST0*/ |
1838 |
RESERVED(); |
1839 |
break;
|
1840 |
|
1841 |
case 7: /*CUST1*/ |
1842 |
RESERVED(); |
1843 |
break;
|
1844 |
|
1845 |
case 8: /*LSCXp*/ |
1846 |
HAS_OPTION(XTENSA_OPTION_COPROCESSOR); |
1847 |
TBD(); |
1848 |
break;
|
1849 |
|
1850 |
case 9: /*LSC4*/ |
1851 |
gen_window_check2(dc, RRR_S, RRR_T); |
1852 |
switch (OP2) {
|
1853 |
case 0: /*L32E*/ |
1854 |
HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); |
1855 |
gen_check_privilege(dc); |
1856 |
{ |
1857 |
TCGv_i32 addr = tcg_temp_new_i32(); |
1858 |
tcg_gen_addi_i32(addr, cpu_R[RRR_S], |
1859 |
(0xffffffc0 | (RRR_R << 2))); |
1860 |
tcg_gen_qemu_ld32u(cpu_R[RRR_T], addr, dc->ring); |
1861 |
tcg_temp_free(addr); |
1862 |
} |
1863 |
break;
|
1864 |
|
1865 |
case 4: /*S32E*/ |
1866 |
HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); |
1867 |
gen_check_privilege(dc); |
1868 |
{ |
1869 |
TCGv_i32 addr = tcg_temp_new_i32(); |
1870 |
tcg_gen_addi_i32(addr, cpu_R[RRR_S], |
1871 |
(0xffffffc0 | (RRR_R << 2))); |
1872 |
tcg_gen_qemu_st32(cpu_R[RRR_T], addr, dc->ring); |
1873 |
tcg_temp_free(addr); |
1874 |
} |
1875 |
break;
|
1876 |
|
1877 |
default:
|
1878 |
RESERVED(); |
1879 |
break;
|
1880 |
} |
1881 |
break;
|
1882 |
|
1883 |
case 10: /*FP0*/ |
1884 |
HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); |
1885 |
TBD(); |
1886 |
break;
|
1887 |
|
1888 |
case 11: /*FP1*/ |
1889 |
HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); |
1890 |
TBD(); |
1891 |
break;
|
1892 |
|
1893 |
default: /*reserved*/ |
1894 |
RESERVED(); |
1895 |
break;
|
1896 |
} |
1897 |
break;
|
1898 |
|
1899 |
case 1: /*L32R*/ |
1900 |
gen_window_check1(dc, RRR_T); |
1901 |
{ |
1902 |
TCGv_i32 tmp = tcg_const_i32( |
1903 |
((dc->tb->flags & XTENSA_TBFLAG_LITBASE) ? |
1904 |
0 : ((dc->pc + 3) & ~3)) + |
1905 |
(0xfffc0000 | (RI16_IMM16 << 2))); |
1906 |
|
1907 |
if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
|
1908 |
tcg_gen_add_i32(tmp, tmp, dc->litbase); |
1909 |
} |
1910 |
tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, dc->cring); |
1911 |
tcg_temp_free(tmp); |
1912 |
} |
1913 |
break;
|
1914 |
|
1915 |
case 2: /*LSAI*/ |
1916 |
#define gen_load_store(type, shift) do { \ |
1917 |
TCGv_i32 addr = tcg_temp_new_i32(); \ |
1918 |
gen_window_check2(dc, RRI8_S, RRI8_T); \ |
1919 |
tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \ |
1920 |
if (shift) { \
|
1921 |
gen_load_store_alignment(dc, shift, addr, false); \
|
1922 |
} \ |
1923 |
tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \ |
1924 |
tcg_temp_free(addr); \ |
1925 |
} while (0) |
1926 |
|
1927 |
switch (RRI8_R) {
|
1928 |
case 0: /*L8UI*/ |
1929 |
gen_load_store(ld8u, 0);
|
1930 |
break;
|
1931 |
|
1932 |
case 1: /*L16UI*/ |
1933 |
gen_load_store(ld16u, 1);
|
1934 |
break;
|
1935 |
|
1936 |
case 2: /*L32I*/ |
1937 |
gen_load_store(ld32u, 2);
|
1938 |
break;
|
1939 |
|
1940 |
case 4: /*S8I*/ |
1941 |
gen_load_store(st8, 0);
|
1942 |
break;
|
1943 |
|
1944 |
case 5: /*S16I*/ |
1945 |
gen_load_store(st16, 1);
|
1946 |
break;
|
1947 |
|
1948 |
case 6: /*S32I*/ |
1949 |
gen_load_store(st32, 2);
|
1950 |
break;
|
1951 |
|
1952 |
case 7: /*CACHEc*/ |
1953 |
if (RRI8_T < 8) { |
1954 |
HAS_OPTION(XTENSA_OPTION_DCACHE); |
1955 |
} |
1956 |
|
1957 |
switch (RRI8_T) {
|
1958 |
case 0: /*DPFRc*/ |
1959 |
break;
|
1960 |
|
1961 |
case 1: /*DPFWc*/ |
1962 |
break;
|
1963 |
|
1964 |
case 2: /*DPFROc*/ |
1965 |
break;
|
1966 |
|
1967 |
case 3: /*DPFWOc*/ |
1968 |
break;
|
1969 |
|
1970 |
case 4: /*DHWBc*/ |
1971 |
break;
|
1972 |
|
1973 |
case 5: /*DHWBIc*/ |
1974 |
break;
|
1975 |
|
1976 |
case 6: /*DHIc*/ |
1977 |
break;
|
1978 |
|
1979 |
case 7: /*DIIc*/ |
1980 |
break;
|
1981 |
|
1982 |
case 8: /*DCEc*/ |
1983 |
switch (OP1) {
|
1984 |
case 0: /*DPFLl*/ |
1985 |
HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK); |
1986 |
break;
|
1987 |
|
1988 |
case 2: /*DHUl*/ |
1989 |
HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK); |
1990 |
break;
|
1991 |
|
1992 |
case 3: /*DIUl*/ |
1993 |
HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK); |
1994 |
break;
|
1995 |
|
1996 |
case 4: /*DIWBc*/ |
1997 |
HAS_OPTION(XTENSA_OPTION_DCACHE); |
1998 |
break;
|
1999 |
|
2000 |
case 5: /*DIWBIc*/ |
2001 |
HAS_OPTION(XTENSA_OPTION_DCACHE); |
2002 |
break;
|
2003 |
|
2004 |
default: /*reserved*/ |
2005 |
RESERVED(); |
2006 |
break;
|
2007 |
|
2008 |
} |
2009 |
break;
|
2010 |
|
2011 |
case 12: /*IPFc*/ |
2012 |
HAS_OPTION(XTENSA_OPTION_ICACHE); |
2013 |
break;
|
2014 |
|
2015 |
case 13: /*ICEc*/ |
2016 |
switch (OP1) {
|
2017 |
case 0: /*IPFLl*/ |
2018 |
HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK); |
2019 |
break;
|
2020 |
|
2021 |
case 2: /*IHUl*/ |
2022 |
HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK); |
2023 |
break;
|
2024 |
|
2025 |
case 3: /*IIUl*/ |
2026 |
HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK); |
2027 |
break;
|
2028 |
|
2029 |
default: /*reserved*/ |
2030 |
RESERVED(); |
2031 |
break;
|
2032 |
} |
2033 |
break;
|
2034 |
|
2035 |
case 14: /*IHIc*/ |
2036 |
HAS_OPTION(XTENSA_OPTION_ICACHE); |
2037 |
break;
|
2038 |
|
2039 |
case 15: /*IIIc*/ |
2040 |
HAS_OPTION(XTENSA_OPTION_ICACHE); |
2041 |
break;
|
2042 |
|
2043 |
default: /*reserved*/ |
2044 |
RESERVED(); |
2045 |
break;
|
2046 |
} |
2047 |
break;
|
2048 |
|
2049 |
case 9: /*L16SI*/ |
2050 |
gen_load_store(ld16s, 1);
|
2051 |
break;
|
2052 |
#undef gen_load_store
|
2053 |
|
2054 |
case 10: /*MOVI*/ |
2055 |
gen_window_check1(dc, RRI8_T); |
2056 |
tcg_gen_movi_i32(cpu_R[RRI8_T], |
2057 |
RRI8_IMM8 | (RRI8_S << 8) |
|
2058 |
((RRI8_S & 0x8) ? 0xfffff000 : 0)); |
2059 |
break;
|
2060 |
|
2061 |
#define gen_load_store_no_hw_align(type) do { \ |
2062 |
TCGv_i32 addr = tcg_temp_local_new_i32(); \ |
2063 |
gen_window_check2(dc, RRI8_S, RRI8_T); \ |
2064 |
tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \
|
2065 |
gen_load_store_alignment(dc, 2, addr, true); \ |
2066 |
tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \ |
2067 |
tcg_temp_free(addr); \ |
2068 |
} while (0) |
2069 |
|
2070 |
case 11: /*L32AIy*/ |
2071 |
HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO); |
2072 |
gen_load_store_no_hw_align(ld32u); /*TODO acquire?*/
|
2073 |
break;
|
2074 |
|
2075 |
case 12: /*ADDI*/ |
2076 |
gen_window_check2(dc, RRI8_S, RRI8_T); |
2077 |
tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE); |
2078 |
break;
|
2079 |
|
2080 |
case 13: /*ADDMI*/ |
2081 |
gen_window_check2(dc, RRI8_S, RRI8_T); |
2082 |
tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE << 8);
|
2083 |
break;
|
2084 |
|
2085 |
case 14: /*S32C1Iy*/ |
2086 |
HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE); |
2087 |
gen_window_check2(dc, RRI8_S, RRI8_T); |
2088 |
{ |
2089 |
int label = gen_new_label();
|
2090 |
TCGv_i32 tmp = tcg_temp_local_new_i32(); |
2091 |
TCGv_i32 addr = tcg_temp_local_new_i32(); |
2092 |
|
2093 |
tcg_gen_mov_i32(tmp, cpu_R[RRI8_T]); |
2094 |
tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
|
2095 |
gen_load_store_alignment(dc, 2, addr, true); |
2096 |
tcg_gen_qemu_ld32u(cpu_R[RRI8_T], addr, dc->cring); |
2097 |
tcg_gen_brcond_i32(TCG_COND_NE, cpu_R[RRI8_T], |
2098 |
cpu_SR[SCOMPARE1], label); |
2099 |
|
2100 |
tcg_gen_qemu_st32(tmp, addr, dc->cring); |
2101 |
|
2102 |
gen_set_label(label); |
2103 |
tcg_temp_free(addr); |
2104 |
tcg_temp_free(tmp); |
2105 |
} |
2106 |
break;
|
2107 |
|
2108 |
case 15: /*S32RIy*/ |
2109 |
HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO); |
2110 |
gen_load_store_no_hw_align(st32); /*TODO release?*/
|
2111 |
break;
|
2112 |
#undef gen_load_store_no_hw_align
|
2113 |
|
2114 |
default: /*reserved*/ |
2115 |
RESERVED(); |
2116 |
break;
|
2117 |
} |
2118 |
break;
|
2119 |
|
2120 |
case 3: /*LSCIp*/ |
2121 |
HAS_OPTION(XTENSA_OPTION_COPROCESSOR); |
2122 |
TBD(); |
2123 |
break;
|
2124 |
|
2125 |
case 4: /*MAC16d*/ |
2126 |
HAS_OPTION(XTENSA_OPTION_MAC16); |
2127 |
{ |
2128 |
enum {
|
2129 |
MAC16_UMUL = 0x0,
|
2130 |
MAC16_MUL = 0x4,
|
2131 |
MAC16_MULA = 0x8,
|
2132 |
MAC16_MULS = 0xc,
|
2133 |
MAC16_NONE = 0xf,
|
2134 |
} op = OP1 & 0xc;
|
2135 |
bool is_m1_sr = (OP2 & 0x3) == 2; |
2136 |
bool is_m2_sr = (OP2 & 0xc) == 0; |
2137 |
uint32_t ld_offset = 0;
|
2138 |
|
2139 |
if (OP2 > 9) { |
2140 |
RESERVED(); |
2141 |
} |
2142 |
|
2143 |
switch (OP2 & 2) { |
2144 |
case 0: /*MACI?/MACC?*/ |
2145 |
is_m1_sr = true;
|
2146 |
ld_offset = (OP2 & 1) ? -4 : 4; |
2147 |
|
2148 |
if (OP2 >= 8) { /*MACI/MACC*/ |
2149 |
if (OP1 == 0) { /*LDINC/LDDEC*/ |
2150 |
op = MAC16_NONE; |
2151 |
} else {
|
2152 |
RESERVED(); |
2153 |
} |
2154 |
} else if (op != MAC16_MULA) { /*MULA.*.*.LDINC/LDDEC*/ |
2155 |
RESERVED(); |
2156 |
} |
2157 |
break;
|
2158 |
|
2159 |
case 2: /*MACD?/MACA?*/ |
2160 |
if (op == MAC16_UMUL && OP2 != 7) { /*UMUL only in MACAA*/ |
2161 |
RESERVED(); |
2162 |
} |
2163 |
break;
|
2164 |
} |
2165 |
|
2166 |
if (op != MAC16_NONE) {
|
2167 |
if (!is_m1_sr) {
|
2168 |
gen_window_check1(dc, RRR_S); |
2169 |
} |
2170 |
if (!is_m2_sr) {
|
2171 |
gen_window_check1(dc, RRR_T); |
2172 |
} |
2173 |
} |
2174 |
|
2175 |
{ |
2176 |
TCGv_i32 vaddr = tcg_temp_new_i32(); |
2177 |
TCGv_i32 mem32 = tcg_temp_new_i32(); |
2178 |
|
2179 |
if (ld_offset) {
|
2180 |
gen_window_check1(dc, RRR_S); |
2181 |
tcg_gen_addi_i32(vaddr, cpu_R[RRR_S], ld_offset); |
2182 |
gen_load_store_alignment(dc, 2, vaddr, false); |
2183 |
tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring); |
2184 |
} |
2185 |
if (op != MAC16_NONE) {
|
2186 |
TCGv_i32 m1 = gen_mac16_m( |
2187 |
is_m1_sr ? cpu_SR[MR + RRR_X] : cpu_R[RRR_S], |
2188 |
OP1 & 1, op == MAC16_UMUL);
|
2189 |
TCGv_i32 m2 = gen_mac16_m( |
2190 |
is_m2_sr ? cpu_SR[MR + 2 + RRR_Y] : cpu_R[RRR_T],
|
2191 |
OP1 & 2, op == MAC16_UMUL);
|
2192 |
|
2193 |
if (op == MAC16_MUL || op == MAC16_UMUL) {
|
2194 |
tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2); |
2195 |
if (op == MAC16_UMUL) {
|
2196 |
tcg_gen_movi_i32(cpu_SR[ACCHI], 0);
|
2197 |
} else {
|
2198 |
tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31);
|
2199 |
} |
2200 |
} else {
|
2201 |
TCGv_i32 res = tcg_temp_new_i32(); |
2202 |
TCGv_i64 res64 = tcg_temp_new_i64(); |
2203 |
TCGv_i64 tmp = tcg_temp_new_i64(); |
2204 |
|
2205 |
tcg_gen_mul_i32(res, m1, m2); |
2206 |
tcg_gen_ext_i32_i64(res64, res); |
2207 |
tcg_gen_concat_i32_i64(tmp, |
2208 |
cpu_SR[ACCLO], cpu_SR[ACCHI]); |
2209 |
if (op == MAC16_MULA) {
|
2210 |
tcg_gen_add_i64(tmp, tmp, res64); |
2211 |
} else {
|
2212 |
tcg_gen_sub_i64(tmp, tmp, res64); |
2213 |
} |
2214 |
tcg_gen_trunc_i64_i32(cpu_SR[ACCLO], tmp); |
2215 |
tcg_gen_shri_i64(tmp, tmp, 32);
|
2216 |
tcg_gen_trunc_i64_i32(cpu_SR[ACCHI], tmp); |
2217 |
tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]); |
2218 |
|
2219 |
tcg_temp_free(res); |
2220 |
tcg_temp_free_i64(res64); |
2221 |
tcg_temp_free_i64(tmp); |
2222 |
} |
2223 |
tcg_temp_free(m1); |
2224 |
tcg_temp_free(m2); |
2225 |
} |
2226 |
if (ld_offset) {
|
2227 |
tcg_gen_mov_i32(cpu_R[RRR_S], vaddr); |
2228 |
tcg_gen_mov_i32(cpu_SR[MR + RRR_W], mem32); |
2229 |
} |
2230 |
tcg_temp_free(vaddr); |
2231 |
tcg_temp_free(mem32); |
2232 |
} |
2233 |
} |
2234 |
break;
|
2235 |
|
2236 |
case 5: /*CALLN*/ |
2237 |
switch (CALL_N) {
|
2238 |
case 0: /*CALL0*/ |
2239 |
tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
|
2240 |
gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0); |
2241 |
break;
|
2242 |
|
2243 |
case 1: /*CALL4w*/ |
2244 |
case 2: /*CALL8w*/ |
2245 |
case 3: /*CALL12w*/ |
2246 |
HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); |
2247 |
gen_window_check1(dc, CALL_N << 2);
|
2248 |
gen_callwi(dc, CALL_N, |
2249 |
(dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0); |
2250 |
break;
|
2251 |
} |
2252 |
break;
|
2253 |
|
2254 |
case 6: /*SI*/ |
2255 |
switch (CALL_N) {
|
2256 |
case 0: /*J*/ |
2257 |
gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0); |
2258 |
break;
|
2259 |
|
2260 |
case 1: /*BZ*/ |
2261 |
gen_window_check1(dc, BRI12_S); |
2262 |
{ |
2263 |
static const TCGCond cond[] = { |
2264 |
TCG_COND_EQ, /*BEQZ*/
|
2265 |
TCG_COND_NE, /*BNEZ*/
|
2266 |
TCG_COND_LT, /*BLTZ*/
|
2267 |
TCG_COND_GE, /*BGEZ*/
|
2268 |
}; |
2269 |
|
2270 |
gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0, |
2271 |
4 + BRI12_IMM12_SE);
|
2272 |
} |
2273 |
break;
|
2274 |
|
2275 |
case 2: /*BI0*/ |
2276 |
gen_window_check1(dc, BRI8_S); |
2277 |
{ |
2278 |
static const TCGCond cond[] = { |
2279 |
TCG_COND_EQ, /*BEQI*/
|
2280 |
TCG_COND_NE, /*BNEI*/
|
2281 |
TCG_COND_LT, /*BLTI*/
|
2282 |
TCG_COND_GE, /*BGEI*/
|
2283 |
}; |
2284 |
|
2285 |
gen_brcondi(dc, cond[BRI8_M & 3],
|
2286 |
cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE);
|
2287 |
} |
2288 |
break;
|
2289 |
|
2290 |
case 3: /*BI1*/ |
2291 |
switch (BRI8_M) {
|
2292 |
case 0: /*ENTRYw*/ |
2293 |
HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); |
2294 |
{ |
2295 |
TCGv_i32 pc = tcg_const_i32(dc->pc); |
2296 |
TCGv_i32 s = tcg_const_i32(BRI12_S); |
2297 |
TCGv_i32 imm = tcg_const_i32(BRI12_IMM12); |
2298 |
gen_advance_ccount(dc); |
2299 |
gen_helper_entry(cpu_env, pc, s, imm); |
2300 |
tcg_temp_free(imm); |
2301 |
tcg_temp_free(s); |
2302 |
tcg_temp_free(pc); |
2303 |
reset_used_window(dc); |
2304 |
} |
2305 |
break;
|
2306 |
|
2307 |
case 1: /*B1*/ |
2308 |
switch (BRI8_R) {
|
2309 |
case 0: /*BFp*/ |
2310 |
case 1: /*BTp*/ |
2311 |
HAS_OPTION(XTENSA_OPTION_BOOLEAN); |
2312 |
{ |
2313 |
TCGv_i32 tmp = tcg_temp_new_i32(); |
2314 |
tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRI8_S);
|
2315 |
gen_brcondi(dc, |
2316 |
BRI8_R == 1 ? TCG_COND_NE : TCG_COND_EQ,
|
2317 |
tmp, 0, 4 + RRI8_IMM8_SE); |
2318 |
tcg_temp_free(tmp); |
2319 |
} |
2320 |
break;
|
2321 |
|
2322 |
case 8: /*LOOP*/ |
2323 |
case 9: /*LOOPNEZ*/ |
2324 |
case 10: /*LOOPGTZ*/ |
2325 |
HAS_OPTION(XTENSA_OPTION_LOOP); |
2326 |
gen_window_check1(dc, RRI8_S); |
2327 |
{ |
2328 |
uint32_t lend = dc->pc + RRI8_IMM8 + 4;
|
2329 |
TCGv_i32 tmp = tcg_const_i32(lend); |
2330 |
|
2331 |
tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[RRI8_S], 1);
|
2332 |
tcg_gen_movi_i32(cpu_SR[LBEG], dc->next_pc); |
2333 |
gen_helper_wsr_lend(cpu_env, tmp); |
2334 |
tcg_temp_free(tmp); |
2335 |
|
2336 |
if (BRI8_R > 8) { |
2337 |
int label = gen_new_label();
|
2338 |
tcg_gen_brcondi_i32( |
2339 |
BRI8_R == 9 ? TCG_COND_NE : TCG_COND_GT,
|
2340 |
cpu_R[RRI8_S], 0, label);
|
2341 |
gen_jumpi(dc, lend, 1);
|
2342 |
gen_set_label(label); |
2343 |
} |
2344 |
|
2345 |
gen_jumpi(dc, dc->next_pc, 0);
|
2346 |
} |
2347 |
break;
|
2348 |
|
2349 |
default: /*reserved*/ |
2350 |
RESERVED(); |
2351 |
break;
|
2352 |
|
2353 |
} |
2354 |
break;
|
2355 |
|
2356 |
case 2: /*BLTUI*/ |
2357 |
case 3: /*BGEUI*/ |
2358 |
gen_window_check1(dc, BRI8_S); |
2359 |
gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU,
|
2360 |
cpu_R[BRI8_S], B4CONSTU[BRI8_R], 4 + BRI8_IMM8_SE);
|
2361 |
break;
|
2362 |
} |
2363 |
break;
|
2364 |
|
2365 |
} |
2366 |
break;
|
2367 |
|
2368 |
case 7: /*B*/ |
2369 |
{ |
2370 |
TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ;
|
2371 |
|
2372 |
switch (RRI8_R & 7) { |
2373 |
case 0: /*BNONE*/ /*BANY*/ |
2374 |
gen_window_check2(dc, RRI8_S, RRI8_T); |
2375 |
{ |
2376 |
TCGv_i32 tmp = tcg_temp_new_i32(); |
2377 |
tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]); |
2378 |
gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE); |
2379 |
tcg_temp_free(tmp); |
2380 |
} |
2381 |
break;
|
2382 |
|
2383 |
case 1: /*BEQ*/ /*BNE*/ |
2384 |
case 2: /*BLT*/ /*BGE*/ |
2385 |
case 3: /*BLTU*/ /*BGEU*/ |
2386 |
gen_window_check2(dc, RRI8_S, RRI8_T); |
2387 |
{ |
2388 |
static const TCGCond cond[] = { |
2389 |
[1] = TCG_COND_EQ,
|
2390 |
[2] = TCG_COND_LT,
|
2391 |
[3] = TCG_COND_LTU,
|
2392 |
[9] = TCG_COND_NE,
|
2393 |
[10] = TCG_COND_GE,
|
2394 |
[11] = TCG_COND_GEU,
|
2395 |
}; |
2396 |
gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T], |
2397 |
4 + RRI8_IMM8_SE);
|
2398 |
} |
2399 |
break;
|
2400 |
|
2401 |
case 4: /*BALL*/ /*BNALL*/ |
2402 |
gen_window_check2(dc, RRI8_S, RRI8_T); |
2403 |
{ |
2404 |
TCGv_i32 tmp = tcg_temp_new_i32(); |
2405 |
tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]); |
2406 |
gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T], |
2407 |
4 + RRI8_IMM8_SE);
|
2408 |
tcg_temp_free(tmp); |
2409 |
} |
2410 |
break;
|
2411 |
|
2412 |
case 5: /*BBC*/ /*BBS*/ |
2413 |
gen_window_check2(dc, RRI8_S, RRI8_T); |
2414 |
{ |
2415 |
#ifdef TARGET_WORDS_BIGENDIAN
|
2416 |
TCGv_i32 bit = tcg_const_i32(0x80000000);
|
2417 |
#else
|
2418 |
TCGv_i32 bit = tcg_const_i32(0x00000001);
|
2419 |
#endif
|
2420 |
TCGv_i32 tmp = tcg_temp_new_i32(); |
2421 |
tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f);
|
2422 |
#ifdef TARGET_WORDS_BIGENDIAN
|
2423 |
tcg_gen_shr_i32(bit, bit, tmp); |
2424 |
#else
|
2425 |
tcg_gen_shl_i32(bit, bit, tmp); |
2426 |
#endif
|
2427 |
tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit); |
2428 |
gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE); |
2429 |
tcg_temp_free(tmp); |
2430 |
tcg_temp_free(bit); |
2431 |
} |
2432 |
break;
|
2433 |
|
2434 |
case 6: /*BBCI*/ /*BBSI*/ |
2435 |
case 7: |
2436 |
gen_window_check1(dc, RRI8_S); |
2437 |
{ |
2438 |
TCGv_i32 tmp = tcg_temp_new_i32(); |
2439 |
tcg_gen_andi_i32(tmp, cpu_R[RRI8_S], |
2440 |
#ifdef TARGET_WORDS_BIGENDIAN
|
2441 |
0x80000000 >> (((RRI8_R & 1) << 4) | RRI8_T)); |
2442 |
#else
|
2443 |
0x00000001 << (((RRI8_R & 1) << 4) | RRI8_T)); |
2444 |
#endif
|
2445 |
gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE); |
2446 |
tcg_temp_free(tmp); |
2447 |
} |
2448 |
break;
|
2449 |
|
2450 |
} |
2451 |
} |
2452 |
break;
|
2453 |
|
2454 |
#define gen_narrow_load_store(type) do { \ |
2455 |
TCGv_i32 addr = tcg_temp_new_i32(); \ |
2456 |
gen_window_check2(dc, RRRN_S, RRRN_T); \ |
2457 |
tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
|
2458 |
gen_load_store_alignment(dc, 2, addr, false); \ |
2459 |
tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \ |
2460 |
tcg_temp_free(addr); \ |
2461 |
} while (0) |
2462 |
|
2463 |
case 8: /*L32I.Nn*/ |
2464 |
gen_narrow_load_store(ld32u); |
2465 |
break;
|
2466 |
|
2467 |
case 9: /*S32I.Nn*/ |
2468 |
gen_narrow_load_store(st32); |
2469 |
break;
|
2470 |
#undef gen_narrow_load_store
|
2471 |
|
2472 |
case 10: /*ADD.Nn*/ |
2473 |
gen_window_check3(dc, RRRN_R, RRRN_S, RRRN_T); |
2474 |
tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]); |
2475 |
break;
|
2476 |
|
2477 |
case 11: /*ADDI.Nn*/ |
2478 |
gen_window_check2(dc, RRRN_R, RRRN_S); |
2479 |
tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], RRRN_T ? RRRN_T : -1);
|
2480 |
break;
|
2481 |
|
2482 |
case 12: /*ST2n*/ |
2483 |
gen_window_check1(dc, RRRN_S); |
2484 |
if (RRRN_T < 8) { /*MOVI.Nn*/ |
2485 |
tcg_gen_movi_i32(cpu_R[RRRN_S], |
2486 |
RRRN_R | (RRRN_T << 4) |
|
2487 |
((RRRN_T & 6) == 6 ? 0xffffff80 : 0)); |
2488 |
} else { /*BEQZ.Nn*/ /*BNEZ.Nn*/ |
2489 |
TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ;
|
2490 |
|
2491 |
gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0,
|
2492 |
4 + (RRRN_R | ((RRRN_T & 3) << 4))); |
2493 |
} |
2494 |
break;
|
2495 |
|
2496 |
case 13: /*ST3n*/ |
2497 |
switch (RRRN_R) {
|
2498 |
case 0: /*MOV.Nn*/ |
2499 |
gen_window_check2(dc, RRRN_S, RRRN_T); |
2500 |
tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]); |
2501 |
break;
|
2502 |
|
2503 |
case 15: /*S3*/ |
2504 |
switch (RRRN_T) {
|
2505 |
case 0: /*RET.Nn*/ |
2506 |
gen_jump(dc, cpu_R[0]);
|
2507 |
break;
|
2508 |
|
2509 |
case 1: /*RETW.Nn*/ |
2510 |
HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); |
2511 |
{ |
2512 |
TCGv_i32 tmp = tcg_const_i32(dc->pc); |
2513 |
gen_advance_ccount(dc); |
2514 |
gen_helper_retw(tmp, cpu_env, tmp); |
2515 |
gen_jump(dc, tmp); |
2516 |
tcg_temp_free(tmp); |
2517 |
} |
2518 |
break;
|
2519 |
|
2520 |
case 2: /*BREAK.Nn*/ |
2521 |
HAS_OPTION(XTENSA_OPTION_DEBUG); |
2522 |
if (dc->debug) {
|
2523 |
gen_debug_exception(dc, DEBUGCAUSE_BN); |
2524 |
} |
2525 |
break;
|
2526 |
|
2527 |
case 3: /*NOP.Nn*/ |
2528 |
break;
|
2529 |
|
2530 |
case 6: /*ILL.Nn*/ |
2531 |
gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); |
2532 |
break;
|
2533 |
|
2534 |
default: /*reserved*/ |
2535 |
RESERVED(); |
2536 |
break;
|
2537 |
} |
2538 |
break;
|
2539 |
|
2540 |
default: /*reserved*/ |
2541 |
RESERVED(); |
2542 |
break;
|
2543 |
} |
2544 |
break;
|
2545 |
|
2546 |
default: /*reserved*/ |
2547 |
RESERVED(); |
2548 |
break;
|
2549 |
} |
2550 |
|
2551 |
if (dc->is_jmp == DISAS_NEXT) {
|
2552 |
gen_check_loop_end(dc, 0);
|
2553 |
} |
2554 |
dc->pc = dc->next_pc; |
2555 |
|
2556 |
return;
|
2557 |
|
2558 |
invalid_opcode:
|
2559 |
qemu_log("INVALID(pc = %08x)\n", dc->pc);
|
2560 |
gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); |
2561 |
#undef HAS_OPTION
|
2562 |
} |
2563 |
|
2564 |
static void check_breakpoint(CPUXtensaState *env, DisasContext *dc) |
2565 |
{ |
2566 |
CPUBreakpoint *bp; |
2567 |
|
2568 |
if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
|
2569 |
QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
2570 |
if (bp->pc == dc->pc) {
|
2571 |
tcg_gen_movi_i32(cpu_pc, dc->pc); |
2572 |
gen_exception(dc, EXCP_DEBUG); |
2573 |
dc->is_jmp = DISAS_UPDATE; |
2574 |
} |
2575 |
} |
2576 |
} |
2577 |
} |
2578 |
|
2579 |
static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc) |
2580 |
{ |
2581 |
unsigned i;
|
2582 |
|
2583 |
for (i = 0; i < dc->config->nibreak; ++i) { |
2584 |
if ((env->sregs[IBREAKENABLE] & (1 << i)) && |
2585 |
env->sregs[IBREAKA + i] == dc->pc) { |
2586 |
gen_debug_exception(dc, DEBUGCAUSE_IB); |
2587 |
break;
|
2588 |
} |
2589 |
} |
2590 |
} |
2591 |
|
2592 |
static void gen_intermediate_code_internal( |
2593 |
CPUXtensaState *env, TranslationBlock *tb, int search_pc)
|
2594 |
{ |
2595 |
DisasContext dc; |
2596 |
int insn_count = 0; |
2597 |
int j, lj = -1; |
2598 |
uint16_t *gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
2599 |
int max_insns = tb->cflags & CF_COUNT_MASK;
|
2600 |
uint32_t pc_start = tb->pc; |
2601 |
uint32_t next_page_start = |
2602 |
(pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; |
2603 |
|
2604 |
if (max_insns == 0) { |
2605 |
max_insns = CF_COUNT_MASK; |
2606 |
} |
2607 |
|
2608 |
dc.config = env->config; |
2609 |
dc.singlestep_enabled = env->singlestep_enabled; |
2610 |
dc.tb = tb; |
2611 |
dc.pc = pc_start; |
2612 |
dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK; |
2613 |
dc.cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring;
|
2614 |
dc.lbeg = env->sregs[LBEG]; |
2615 |
dc.lend = env->sregs[LEND]; |
2616 |
dc.is_jmp = DISAS_NEXT; |
2617 |
dc.ccount_delta = 0;
|
2618 |
dc.debug = tb->flags & XTENSA_TBFLAG_DEBUG; |
2619 |
dc.icount = tb->flags & XTENSA_TBFLAG_ICOUNT; |
2620 |
|
2621 |
init_litbase(&dc); |
2622 |
init_sar_tracker(&dc); |
2623 |
reset_used_window(&dc); |
2624 |
if (dc.icount) {
|
2625 |
dc.next_icount = tcg_temp_local_new_i32(); |
2626 |
} |
2627 |
|
2628 |
gen_icount_start(); |
2629 |
|
2630 |
if (env->singlestep_enabled && env->exception_taken) {
|
2631 |
env->exception_taken = 0;
|
2632 |
tcg_gen_movi_i32(cpu_pc, dc.pc); |
2633 |
gen_exception(&dc, EXCP_DEBUG); |
2634 |
} |
2635 |
|
2636 |
do {
|
2637 |
check_breakpoint(env, &dc); |
2638 |
|
2639 |
if (search_pc) {
|
2640 |
j = gen_opc_ptr - gen_opc_buf; |
2641 |
if (lj < j) {
|
2642 |
lj++; |
2643 |
while (lj < j) {
|
2644 |
gen_opc_instr_start[lj++] = 0;
|
2645 |
} |
2646 |
} |
2647 |
gen_opc_pc[lj] = dc.pc; |
2648 |
gen_opc_instr_start[lj] = 1;
|
2649 |
gen_opc_icount[lj] = insn_count; |
2650 |
} |
2651 |
|
2652 |
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
|
2653 |
tcg_gen_debug_insn_start(dc.pc); |
2654 |
} |
2655 |
|
2656 |
++dc.ccount_delta; |
2657 |
|
2658 |
if (insn_count + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { |
2659 |
gen_io_start(); |
2660 |
} |
2661 |
|
2662 |
if (dc.icount) {
|
2663 |
int label = gen_new_label();
|
2664 |
|
2665 |
tcg_gen_addi_i32(dc.next_icount, cpu_SR[ICOUNT], 1);
|
2666 |
tcg_gen_brcondi_i32(TCG_COND_NE, dc.next_icount, 0, label);
|
2667 |
tcg_gen_mov_i32(dc.next_icount, cpu_SR[ICOUNT]); |
2668 |
if (dc.debug) {
|
2669 |
gen_debug_exception(&dc, DEBUGCAUSE_IC); |
2670 |
} |
2671 |
gen_set_label(label); |
2672 |
} |
2673 |
|
2674 |
if (dc.debug) {
|
2675 |
gen_ibreak_check(env, &dc); |
2676 |
} |
2677 |
|
2678 |
disas_xtensa_insn(&dc); |
2679 |
++insn_count; |
2680 |
if (dc.icount) {
|
2681 |
tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount); |
2682 |
} |
2683 |
if (env->singlestep_enabled) {
|
2684 |
tcg_gen_movi_i32(cpu_pc, dc.pc); |
2685 |
gen_exception(&dc, EXCP_DEBUG); |
2686 |
break;
|
2687 |
} |
2688 |
} while (dc.is_jmp == DISAS_NEXT &&
|
2689 |
insn_count < max_insns && |
2690 |
dc.pc < next_page_start && |
2691 |
gen_opc_ptr < gen_opc_end); |
2692 |
|
2693 |
reset_litbase(&dc); |
2694 |
reset_sar_tracker(&dc); |
2695 |
if (dc.icount) {
|
2696 |
tcg_temp_free(dc.next_icount); |
2697 |
} |
2698 |
|
2699 |
if (tb->cflags & CF_LAST_IO) {
|
2700 |
gen_io_end(); |
2701 |
} |
2702 |
|
2703 |
if (dc.is_jmp == DISAS_NEXT) {
|
2704 |
gen_jumpi(&dc, dc.pc, 0);
|
2705 |
} |
2706 |
gen_icount_end(tb, insn_count); |
2707 |
*gen_opc_ptr = INDEX_op_end; |
2708 |
|
2709 |
if (!search_pc) {
|
2710 |
tb->size = dc.pc - pc_start; |
2711 |
tb->icount = insn_count; |
2712 |
} |
2713 |
} |
2714 |
|
2715 |
void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb)
|
2716 |
{ |
2717 |
gen_intermediate_code_internal(env, tb, 0);
|
2718 |
} |
2719 |
|
2720 |
void gen_intermediate_code_pc(CPUXtensaState *env, TranslationBlock *tb)
|
2721 |
{ |
2722 |
gen_intermediate_code_internal(env, tb, 1);
|
2723 |
} |
2724 |
|
2725 |
void cpu_dump_state(CPUXtensaState *env, FILE *f, fprintf_function cpu_fprintf,
|
2726 |
int flags)
|
2727 |
{ |
2728 |
int i, j;
|
2729 |
|
2730 |
cpu_fprintf(f, "PC=%08x\n\n", env->pc);
|
2731 |
|
2732 |
for (i = j = 0; i < 256; ++i) { |
2733 |
if (sregnames[i]) {
|
2734 |
cpu_fprintf(f, "%s=%08x%c", sregnames[i], env->sregs[i],
|
2735 |
(j++ % 4) == 3 ? '\n' : ' '); |
2736 |
} |
2737 |
} |
2738 |
|
2739 |
cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n"); |
2740 |
|
2741 |
for (i = j = 0; i < 256; ++i) { |
2742 |
if (uregnames[i]) {
|
2743 |
cpu_fprintf(f, "%s=%08x%c", uregnames[i], env->uregs[i],
|
2744 |
(j++ % 4) == 3 ? '\n' : ' '); |
2745 |
} |
2746 |
} |
2747 |
|
2748 |
cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n"); |
2749 |
|
2750 |
for (i = 0; i < 16; ++i) { |
2751 |
cpu_fprintf(f, "A%02d=%08x%c", i, env->regs[i],
|
2752 |
(i % 4) == 3 ? '\n' : ' '); |
2753 |
} |
2754 |
|
2755 |
cpu_fprintf(f, "\n");
|
2756 |
|
2757 |
for (i = 0; i < env->config->nareg; ++i) { |
2758 |
cpu_fprintf(f, "AR%02d=%08x%c", i, env->phys_regs[i],
|
2759 |
(i % 4) == 3 ? '\n' : ' '); |
2760 |
} |
2761 |
|
2762 |
if (xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) {
|
2763 |
cpu_fprintf(f, "\n");
|
2764 |
|
2765 |
for (i = 0; i < 16; ++i) { |
2766 |
cpu_fprintf(f, "F%02d=%08x (%+10.8e)%c", i,
|
2767 |
float32_val(env->fregs[i]), |
2768 |
*(float *)&env->fregs[i], (i % 2) == 1 ? '\n' : ' '); |
2769 |
} |
2770 |
} |
2771 |
} |
2772 |
|
2773 |
void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb, int pc_pos) |
2774 |
{ |
2775 |
env->pc = gen_opc_pc[pc_pos]; |
2776 |
} |