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1 | 3475187d | bellard | /*
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2 | c7ba218d | blueswir1 | * QEMU Sun4u/Sun4v System Emulator
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3 | 5fafdf24 | ths | *
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4 | 3475187d | bellard | * Copyright (c) 2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 3475187d | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 3475187d | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 3475187d | bellard | * in the Software without restriction, including without limitation the rights
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9 | 3475187d | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 3475187d | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 3475187d | bellard | * furnished to do so, subject to the following conditions:
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12 | 3475187d | bellard | *
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13 | 3475187d | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 3475187d | bellard | * all copies or substantial portions of the Software.
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15 | 3475187d | bellard | *
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16 | 3475187d | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 3475187d | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 3475187d | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 3475187d | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 3475187d | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 3475187d | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 3475187d | bellard | * THE SOFTWARE.
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23 | 3475187d | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "pci.h" |
26 | 18e08a55 | Michael S. Tsirkin | #include "apb_pci.h" |
27 | 87ecb68b | pbrook | #include "pc.h" |
28 | 87ecb68b | pbrook | #include "nvram.h" |
29 | 87ecb68b | pbrook | #include "fdc.h" |
30 | 87ecb68b | pbrook | #include "net.h" |
31 | 87ecb68b | pbrook | #include "qemu-timer.h" |
32 | 87ecb68b | pbrook | #include "sysemu.h" |
33 | 87ecb68b | pbrook | #include "boards.h" |
34 | d2c63fc1 | blueswir1 | #include "firmware_abi.h" |
35 | 3cce6243 | blueswir1 | #include "fw_cfg.h" |
36 | 1baffa46 | Blue Swirl | #include "sysbus.h" |
37 | 977e1244 | Gerd Hoffmann | #include "ide.h" |
38 | ca20cf32 | Blue Swirl | #include "loader.h" |
39 | ca20cf32 | Blue Swirl | #include "elf.h" |
40 | 3475187d | bellard | |
41 | 9d926598 | blueswir1 | //#define DEBUG_IRQ
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42 | b430a225 | Blue Swirl | //#define DEBUG_EBUS
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43 | 9d926598 | blueswir1 | |
44 | 9d926598 | blueswir1 | #ifdef DEBUG_IRQ
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45 | b430a225 | Blue Swirl | #define CPUIRQ_DPRINTF(fmt, ...) \
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46 | 001faf32 | Blue Swirl | do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) |
47 | 9d926598 | blueswir1 | #else
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48 | b430a225 | Blue Swirl | #define CPUIRQ_DPRINTF(fmt, ...)
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49 | b430a225 | Blue Swirl | #endif
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50 | b430a225 | Blue Swirl | |
51 | b430a225 | Blue Swirl | #ifdef DEBUG_EBUS
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52 | b430a225 | Blue Swirl | #define EBUS_DPRINTF(fmt, ...) \
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53 | b430a225 | Blue Swirl | do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0) |
54 | b430a225 | Blue Swirl | #else
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55 | b430a225 | Blue Swirl | #define EBUS_DPRINTF(fmt, ...)
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56 | 9d926598 | blueswir1 | #endif
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57 | 9d926598 | blueswir1 | |
58 | 83469015 | bellard | #define KERNEL_LOAD_ADDR 0x00404000 |
59 | 83469015 | bellard | #define CMDLINE_ADDR 0x003ff000 |
60 | 83469015 | bellard | #define INITRD_LOAD_ADDR 0x00300000 |
61 | ac2e9d66 | blueswir1 | #define PROM_SIZE_MAX (4 * 1024 * 1024) |
62 | f930d07e | blueswir1 | #define PROM_VADDR 0x000ffd00000ULL |
63 | 83469015 | bellard | #define APB_SPECIAL_BASE 0x1fe00000000ULL |
64 | f930d07e | blueswir1 | #define APB_MEM_BASE 0x1ff00000000ULL |
65 | f930d07e | blueswir1 | #define VGA_BASE (APB_MEM_BASE + 0x400000ULL) |
66 | f930d07e | blueswir1 | #define PROM_FILENAME "openbios-sparc64" |
67 | 83469015 | bellard | #define NVRAM_SIZE 0x2000 |
68 | e4bcb14c | ths | #define MAX_IDE_BUS 2 |
69 | 3cce6243 | blueswir1 | #define BIOS_CFG_IOPORT 0x510 |
70 | 7589690c | Blue Swirl | #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) |
71 | 7589690c | Blue Swirl | #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) |
72 | 7589690c | Blue Swirl | #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) |
73 | 3475187d | bellard | |
74 | 9d926598 | blueswir1 | #define MAX_PILS 16 |
75 | 9d926598 | blueswir1 | |
76 | 8fa211e8 | blueswir1 | #define TICK_MAX 0x7fffffffffffffffULL |
77 | 8fa211e8 | blueswir1 | |
78 | c7ba218d | blueswir1 | struct hwdef {
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79 | c7ba218d | blueswir1 | const char * const default_cpu_model; |
80 | 905fdcb5 | blueswir1 | uint16_t machine_id; |
81 | e87231d4 | blueswir1 | uint64_t prom_addr; |
82 | e87231d4 | blueswir1 | uint64_t console_serial_base; |
83 | c7ba218d | blueswir1 | }; |
84 | c7ba218d | blueswir1 | |
85 | 3475187d | bellard | int DMA_get_channel_mode (int nchan) |
86 | 3475187d | bellard | { |
87 | 3475187d | bellard | return 0; |
88 | 3475187d | bellard | } |
89 | 3475187d | bellard | int DMA_read_memory (int nchan, void *buf, int pos, int size) |
90 | 3475187d | bellard | { |
91 | 3475187d | bellard | return 0; |
92 | 3475187d | bellard | } |
93 | 3475187d | bellard | int DMA_write_memory (int nchan, void *buf, int pos, int size) |
94 | 3475187d | bellard | { |
95 | 3475187d | bellard | return 0; |
96 | 3475187d | bellard | } |
97 | 3475187d | bellard | void DMA_hold_DREQ (int nchan) {} |
98 | 3475187d | bellard | void DMA_release_DREQ (int nchan) {} |
99 | 3475187d | bellard | void DMA_schedule(int nchan) {} |
100 | 3475187d | bellard | void DMA_init (int high_page_enable) {} |
101 | 3475187d | bellard | void DMA_register_channel (int nchan, |
102 | 3475187d | bellard | DMA_transfer_handler transfer_handler, |
103 | 3475187d | bellard | void *opaque)
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104 | 3475187d | bellard | { |
105 | 3475187d | bellard | } |
106 | 3475187d | bellard | |
107 | 513f789f | blueswir1 | static int fw_cfg_boot_set(void *opaque, const char *boot_device) |
108 | 81864572 | blueswir1 | { |
109 | 513f789f | blueswir1 | fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
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110 | 81864572 | blueswir1 | return 0; |
111 | 81864572 | blueswir1 | } |
112 | 81864572 | blueswir1 | |
113 | c227f099 | Anthony Liguori | static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size, |
114 | e7fb1406 | blueswir1 | const char *arch, |
115 | c227f099 | Anthony Liguori | ram_addr_t RAM_size, |
116 | 77f193da | blueswir1 | const char *boot_devices, |
117 | d2c63fc1 | blueswir1 | uint32_t kernel_image, uint32_t kernel_size, |
118 | d2c63fc1 | blueswir1 | const char *cmdline, |
119 | d2c63fc1 | blueswir1 | uint32_t initrd_image, uint32_t initrd_size, |
120 | d2c63fc1 | blueswir1 | uint32_t NVRAM_image, |
121 | 0d31cb99 | blueswir1 | int width, int height, int depth, |
122 | 0d31cb99 | blueswir1 | const uint8_t *macaddr)
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123 | 83469015 | bellard | { |
124 | 66508601 | blueswir1 | unsigned int i; |
125 | 66508601 | blueswir1 | uint32_t start, end; |
126 | d2c63fc1 | blueswir1 | uint8_t image[0x1ff0];
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127 | d2c63fc1 | blueswir1 | struct OpenBIOS_nvpart_v1 *part_header;
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128 | d2c63fc1 | blueswir1 | |
129 | d2c63fc1 | blueswir1 | memset(image, '\0', sizeof(image)); |
130 | d2c63fc1 | blueswir1 | |
131 | 513f789f | blueswir1 | start = 0;
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132 | 83469015 | bellard | |
133 | 66508601 | blueswir1 | // OpenBIOS nvram variables
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134 | 66508601 | blueswir1 | // Variable partition
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135 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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136 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_SYSTEM; |
137 | 363a37d5 | blueswir1 | pstrcpy(part_header->name, sizeof(part_header->name), "system"); |
138 | 66508601 | blueswir1 | |
139 | d2c63fc1 | blueswir1 | end = start + sizeof(struct OpenBIOS_nvpart_v1); |
140 | 66508601 | blueswir1 | for (i = 0; i < nb_prom_envs; i++) |
141 | d2c63fc1 | blueswir1 | end = OpenBIOS_set_var(image, end, prom_envs[i]); |
142 | d2c63fc1 | blueswir1 | |
143 | d2c63fc1 | blueswir1 | // End marker
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144 | d2c63fc1 | blueswir1 | image[end++] = '\0';
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145 | 66508601 | blueswir1 | |
146 | 66508601 | blueswir1 | end = start + ((end - start + 15) & ~15); |
147 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
148 | 66508601 | blueswir1 | |
149 | 66508601 | blueswir1 | // free partition
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150 | 66508601 | blueswir1 | start = end; |
151 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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152 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_FREE; |
153 | 363a37d5 | blueswir1 | pstrcpy(part_header->name, sizeof(part_header->name), "free"); |
154 | 66508601 | blueswir1 | |
155 | 66508601 | blueswir1 | end = 0x1fd0;
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156 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
157 | d2c63fc1 | blueswir1 | |
158 | 0d31cb99 | blueswir1 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); |
159 | 0d31cb99 | blueswir1 | |
160 | d2c63fc1 | blueswir1 | for (i = 0; i < sizeof(image); i++) |
161 | d2c63fc1 | blueswir1 | m48t59_write(nvram, i, image[i]); |
162 | 66508601 | blueswir1 | |
163 | 83469015 | bellard | return 0; |
164 | 3475187d | bellard | } |
165 | 636aa70a | Blue Swirl | static unsigned long sun4u_load_kernel(const char *kernel_filename, |
166 | 636aa70a | Blue Swirl | const char *initrd_filename, |
167 | c227f099 | Anthony Liguori | ram_addr_t RAM_size, long *initrd_size)
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168 | 636aa70a | Blue Swirl | { |
169 | 636aa70a | Blue Swirl | int linux_boot;
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170 | 636aa70a | Blue Swirl | unsigned int i; |
171 | 636aa70a | Blue Swirl | long kernel_size;
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172 | 636aa70a | Blue Swirl | |
173 | 636aa70a | Blue Swirl | linux_boot = (kernel_filename != NULL);
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174 | 636aa70a | Blue Swirl | |
175 | 636aa70a | Blue Swirl | kernel_size = 0;
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176 | 636aa70a | Blue Swirl | if (linux_boot) {
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177 | ca20cf32 | Blue Swirl | int bswap_needed;
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178 | ca20cf32 | Blue Swirl | |
179 | ca20cf32 | Blue Swirl | #ifdef BSWAP_NEEDED
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180 | ca20cf32 | Blue Swirl | bswap_needed = 1;
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181 | ca20cf32 | Blue Swirl | #else
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182 | ca20cf32 | Blue Swirl | bswap_needed = 0;
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183 | ca20cf32 | Blue Swirl | #endif
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184 | ca20cf32 | Blue Swirl | kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL, |
185 | ca20cf32 | Blue Swirl | 1, ELF_MACHINE, 0); |
186 | 636aa70a | Blue Swirl | if (kernel_size < 0) |
187 | 636aa70a | Blue Swirl | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
188 | ca20cf32 | Blue Swirl | RAM_size - KERNEL_LOAD_ADDR, bswap_needed, |
189 | ca20cf32 | Blue Swirl | TARGET_PAGE_SIZE); |
190 | 636aa70a | Blue Swirl | if (kernel_size < 0) |
191 | 636aa70a | Blue Swirl | kernel_size = load_image_targphys(kernel_filename, |
192 | 636aa70a | Blue Swirl | KERNEL_LOAD_ADDR, |
193 | 636aa70a | Blue Swirl | RAM_size - KERNEL_LOAD_ADDR); |
194 | 636aa70a | Blue Swirl | if (kernel_size < 0) { |
195 | 636aa70a | Blue Swirl | fprintf(stderr, "qemu: could not load kernel '%s'\n",
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196 | 636aa70a | Blue Swirl | kernel_filename); |
197 | 636aa70a | Blue Swirl | exit(1);
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198 | 636aa70a | Blue Swirl | } |
199 | 636aa70a | Blue Swirl | |
200 | 636aa70a | Blue Swirl | /* load initrd */
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201 | 636aa70a | Blue Swirl | *initrd_size = 0;
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202 | 636aa70a | Blue Swirl | if (initrd_filename) {
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203 | 636aa70a | Blue Swirl | *initrd_size = load_image_targphys(initrd_filename, |
204 | 636aa70a | Blue Swirl | INITRD_LOAD_ADDR, |
205 | 636aa70a | Blue Swirl | RAM_size - INITRD_LOAD_ADDR); |
206 | 636aa70a | Blue Swirl | if (*initrd_size < 0) { |
207 | 636aa70a | Blue Swirl | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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208 | 636aa70a | Blue Swirl | initrd_filename); |
209 | 636aa70a | Blue Swirl | exit(1);
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210 | 636aa70a | Blue Swirl | } |
211 | 636aa70a | Blue Swirl | } |
212 | 636aa70a | Blue Swirl | if (*initrd_size > 0) { |
213 | 636aa70a | Blue Swirl | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
214 | 636aa70a | Blue Swirl | if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS |
215 | 636aa70a | Blue Swirl | stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
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216 | 636aa70a | Blue Swirl | stl_phys(KERNEL_LOAD_ADDR + i + 20, *initrd_size);
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217 | 636aa70a | Blue Swirl | break;
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218 | 636aa70a | Blue Swirl | } |
219 | 636aa70a | Blue Swirl | } |
220 | 636aa70a | Blue Swirl | } |
221 | 636aa70a | Blue Swirl | } |
222 | 636aa70a | Blue Swirl | return kernel_size;
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223 | 636aa70a | Blue Swirl | } |
224 | 3475187d | bellard | |
225 | b4950060 | blueswir1 | void pic_info(Monitor *mon)
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226 | 3475187d | bellard | { |
227 | 3475187d | bellard | } |
228 | 3475187d | bellard | |
229 | b4950060 | blueswir1 | void irq_info(Monitor *mon)
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230 | 3475187d | bellard | { |
231 | 3475187d | bellard | } |
232 | 3475187d | bellard | |
233 | 9d926598 | blueswir1 | void cpu_check_irqs(CPUState *env)
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234 | 9d926598 | blueswir1 | { |
235 | d532b26c | Igor V. Kovalenko | uint32_t pil = env->pil_in | |
236 | d532b26c | Igor V. Kovalenko | (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER)); |
237 | d532b26c | Igor V. Kovalenko | |
238 | d532b26c | Igor V. Kovalenko | /* check if TM or SM in SOFTINT are set
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239 | d532b26c | Igor V. Kovalenko | setting these also causes interrupt 14 */
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240 | d532b26c | Igor V. Kovalenko | if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
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241 | d532b26c | Igor V. Kovalenko | pil |= 1 << 14; |
242 | d532b26c | Igor V. Kovalenko | } |
243 | d532b26c | Igor V. Kovalenko | |
244 | d532b26c | Igor V. Kovalenko | if (!pil) {
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245 | d532b26c | Igor V. Kovalenko | if (env->interrupt_request & CPU_INTERRUPT_HARD) {
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246 | d532b26c | Igor V. Kovalenko | CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
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247 | d532b26c | Igor V. Kovalenko | env->interrupt_index); |
248 | d532b26c | Igor V. Kovalenko | env->interrupt_index = 0;
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249 | d532b26c | Igor V. Kovalenko | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
250 | d532b26c | Igor V. Kovalenko | } |
251 | d532b26c | Igor V. Kovalenko | return;
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252 | d532b26c | Igor V. Kovalenko | } |
253 | d532b26c | Igor V. Kovalenko | |
254 | d532b26c | Igor V. Kovalenko | if (cpu_interrupts_enabled(env)) {
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255 | 9d926598 | blueswir1 | |
256 | 9d926598 | blueswir1 | unsigned int i; |
257 | 9d926598 | blueswir1 | |
258 | d532b26c | Igor V. Kovalenko | for (i = 15; i > env->psrpil; i--) { |
259 | 9d926598 | blueswir1 | if (pil & (1 << i)) { |
260 | 9d926598 | blueswir1 | int old_interrupt = env->interrupt_index;
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261 | d532b26c | Igor V. Kovalenko | int new_interrupt = TT_EXTINT | i;
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262 | d532b26c | Igor V. Kovalenko | |
263 | d532b26c | Igor V. Kovalenko | if (env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt) { |
264 | d532b26c | Igor V. Kovalenko | CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
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265 | d532b26c | Igor V. Kovalenko | "current %x >= pending %x\n",
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266 | d532b26c | Igor V. Kovalenko | env->tl, cpu_tsptr(env)->tt, new_interrupt); |
267 | d532b26c | Igor V. Kovalenko | } else if (old_interrupt != new_interrupt) { |
268 | d532b26c | Igor V. Kovalenko | env->interrupt_index = new_interrupt; |
269 | d532b26c | Igor V. Kovalenko | CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i,
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270 | d532b26c | Igor V. Kovalenko | old_interrupt, new_interrupt); |
271 | 9d926598 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
272 | 9d926598 | blueswir1 | } |
273 | 9d926598 | blueswir1 | break;
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274 | 9d926598 | blueswir1 | } |
275 | 9d926598 | blueswir1 | } |
276 | d532b26c | Igor V. Kovalenko | } else {
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277 | d532b26c | Igor V. Kovalenko | CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
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278 | d532b26c | Igor V. Kovalenko | "current interrupt %x\n",
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279 | d532b26c | Igor V. Kovalenko | pil, env->pil_in, env->softint, env->interrupt_index); |
280 | 9d926598 | blueswir1 | } |
281 | 9d926598 | blueswir1 | } |
282 | 9d926598 | blueswir1 | |
283 | 9d926598 | blueswir1 | static void cpu_set_irq(void *opaque, int irq, int level) |
284 | 9d926598 | blueswir1 | { |
285 | 9d926598 | blueswir1 | CPUState *env = opaque; |
286 | 9d926598 | blueswir1 | |
287 | 9d926598 | blueswir1 | if (level) {
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288 | b430a225 | Blue Swirl | CPUIRQ_DPRINTF("Raise CPU IRQ %d\n", irq);
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289 | 9d926598 | blueswir1 | env->halted = 0;
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290 | 9d926598 | blueswir1 | env->pil_in |= 1 << irq;
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291 | 9d926598 | blueswir1 | cpu_check_irqs(env); |
292 | 9d926598 | blueswir1 | } else {
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293 | b430a225 | Blue Swirl | CPUIRQ_DPRINTF("Lower CPU IRQ %d\n", irq);
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294 | 9d926598 | blueswir1 | env->pil_in &= ~(1 << irq);
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295 | 9d926598 | blueswir1 | cpu_check_irqs(env); |
296 | 9d926598 | blueswir1 | } |
297 | 9d926598 | blueswir1 | } |
298 | 9d926598 | blueswir1 | |
299 | e87231d4 | blueswir1 | typedef struct ResetData { |
300 | e87231d4 | blueswir1 | CPUState *env; |
301 | 44a99354 | Blue Swirl | uint64_t prom_addr; |
302 | e87231d4 | blueswir1 | } ResetData; |
303 | e87231d4 | blueswir1 | |
304 | c68ea704 | bellard | static void main_cpu_reset(void *opaque) |
305 | c68ea704 | bellard | { |
306 | e87231d4 | blueswir1 | ResetData *s = (ResetData *)opaque; |
307 | e87231d4 | blueswir1 | CPUState *env = s->env; |
308 | 44a99354 | Blue Swirl | static unsigned int nr_resets; |
309 | 20c9f095 | blueswir1 | |
310 | c68ea704 | bellard | cpu_reset(env); |
311 | 8fa211e8 | blueswir1 | env->tick_cmpr = TICK_INT_DIS | 0;
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312 | 8fa211e8 | blueswir1 | ptimer_set_limit(env->tick, TICK_MAX, 1);
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313 | 2f43e00e | blueswir1 | ptimer_run(env->tick, 1);
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314 | 8fa211e8 | blueswir1 | env->stick_cmpr = TICK_INT_DIS | 0;
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315 | 8fa211e8 | blueswir1 | ptimer_set_limit(env->stick, TICK_MAX, 1);
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316 | 2f43e00e | blueswir1 | ptimer_run(env->stick, 1);
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317 | 8fa211e8 | blueswir1 | env->hstick_cmpr = TICK_INT_DIS | 0;
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318 | 8fa211e8 | blueswir1 | ptimer_set_limit(env->hstick, TICK_MAX, 1);
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319 | 2f43e00e | blueswir1 | ptimer_run(env->hstick, 1);
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320 | e87231d4 | blueswir1 | env->gregs[1] = 0; // Memory start |
321 | e87231d4 | blueswir1 | env->gregs[2] = ram_size; // Memory size |
322 | e87231d4 | blueswir1 | env->gregs[3] = 0; // Machine description XXX |
323 | 44a99354 | Blue Swirl | if (nr_resets++ == 0) { |
324 | 44a99354 | Blue Swirl | /* Power on reset */
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325 | 44a99354 | Blue Swirl | env->pc = s->prom_addr + 0x20ULL;
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326 | 44a99354 | Blue Swirl | } else {
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327 | 44a99354 | Blue Swirl | env->pc = s->prom_addr + 0x40ULL;
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328 | 44a99354 | Blue Swirl | } |
329 | e87231d4 | blueswir1 | env->npc = env->pc + 4;
|
330 | 20c9f095 | blueswir1 | } |
331 | 20c9f095 | blueswir1 | |
332 | 22548760 | blueswir1 | static void tick_irq(void *opaque) |
333 | 20c9f095 | blueswir1 | { |
334 | 20c9f095 | blueswir1 | CPUState *env = opaque; |
335 | 20c9f095 | blueswir1 | |
336 | 8fa211e8 | blueswir1 | if (!(env->tick_cmpr & TICK_INT_DIS)) {
|
337 | 8fa211e8 | blueswir1 | env->softint |= SOFTINT_TIMER; |
338 | 8fa211e8 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); |
339 | 8fa211e8 | blueswir1 | } |
340 | 20c9f095 | blueswir1 | } |
341 | 20c9f095 | blueswir1 | |
342 | 22548760 | blueswir1 | static void stick_irq(void *opaque) |
343 | 20c9f095 | blueswir1 | { |
344 | 20c9f095 | blueswir1 | CPUState *env = opaque; |
345 | 20c9f095 | blueswir1 | |
346 | 8fa211e8 | blueswir1 | if (!(env->stick_cmpr & TICK_INT_DIS)) {
|
347 | 8fa211e8 | blueswir1 | env->softint |= SOFTINT_STIMER; |
348 | 8fa211e8 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); |
349 | 8fa211e8 | blueswir1 | } |
350 | 20c9f095 | blueswir1 | } |
351 | 20c9f095 | blueswir1 | |
352 | 22548760 | blueswir1 | static void hstick_irq(void *opaque) |
353 | 20c9f095 | blueswir1 | { |
354 | 20c9f095 | blueswir1 | CPUState *env = opaque; |
355 | 20c9f095 | blueswir1 | |
356 | 8fa211e8 | blueswir1 | if (!(env->hstick_cmpr & TICK_INT_DIS)) {
|
357 | 8fa211e8 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); |
358 | 8fa211e8 | blueswir1 | } |
359 | c68ea704 | bellard | } |
360 | c68ea704 | bellard | |
361 | f4b1a842 | blueswir1 | void cpu_tick_set_count(void *opaque, uint64_t count) |
362 | f4b1a842 | blueswir1 | { |
363 | f4b1a842 | blueswir1 | ptimer_set_count(opaque, -count); |
364 | f4b1a842 | blueswir1 | } |
365 | f4b1a842 | blueswir1 | |
366 | f4b1a842 | blueswir1 | uint64_t cpu_tick_get_count(void *opaque)
|
367 | f4b1a842 | blueswir1 | { |
368 | f4b1a842 | blueswir1 | return -ptimer_get_count(opaque);
|
369 | f4b1a842 | blueswir1 | } |
370 | f4b1a842 | blueswir1 | |
371 | f4b1a842 | blueswir1 | void cpu_tick_set_limit(void *opaque, uint64_t limit) |
372 | f4b1a842 | blueswir1 | { |
373 | f4b1a842 | blueswir1 | ptimer_set_limit(opaque, -limit, 0);
|
374 | f4b1a842 | blueswir1 | } |
375 | f4b1a842 | blueswir1 | |
376 | c190ea07 | blueswir1 | static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num, |
377 | 6e355d90 | Isaku Yamahata | pcibus_t addr, pcibus_t size, int type)
|
378 | c190ea07 | blueswir1 | { |
379 | b430a225 | Blue Swirl | EBUS_DPRINTF("Mapping region %d registers at %" FMT_PCIBUS "\n", |
380 | b430a225 | Blue Swirl | region_num, addr); |
381 | c190ea07 | blueswir1 | switch (region_num) {
|
382 | c190ea07 | blueswir1 | case 0: |
383 | c190ea07 | blueswir1 | isa_mmio_init(addr, 0x1000000);
|
384 | c190ea07 | blueswir1 | break;
|
385 | c190ea07 | blueswir1 | case 1: |
386 | c190ea07 | blueswir1 | isa_mmio_init(addr, 0x800000);
|
387 | c190ea07 | blueswir1 | break;
|
388 | c190ea07 | blueswir1 | } |
389 | c190ea07 | blueswir1 | } |
390 | c190ea07 | blueswir1 | |
391 | 1387fe4a | Blue Swirl | static void dummy_isa_irq_handler(void *opaque, int n, int level) |
392 | 1387fe4a | Blue Swirl | { |
393 | 1387fe4a | Blue Swirl | } |
394 | 1387fe4a | Blue Swirl | |
395 | c190ea07 | blueswir1 | /* EBUS (Eight bit bus) bridge */
|
396 | c190ea07 | blueswir1 | static void |
397 | c190ea07 | blueswir1 | pci_ebus_init(PCIBus *bus, int devfn)
|
398 | c190ea07 | blueswir1 | { |
399 | 1387fe4a | Blue Swirl | qemu_irq *isa_irq; |
400 | 1387fe4a | Blue Swirl | |
401 | 53e3c4f9 | Blue Swirl | pci_create_simple(bus, devfn, "ebus");
|
402 | 1387fe4a | Blue Swirl | isa_irq = qemu_allocate_irqs(dummy_isa_irq_handler, NULL, 16); |
403 | 1387fe4a | Blue Swirl | isa_bus_irqs(isa_irq); |
404 | 53e3c4f9 | Blue Swirl | } |
405 | c190ea07 | blueswir1 | |
406 | 81a322d4 | Gerd Hoffmann | static int |
407 | 53e3c4f9 | Blue Swirl | pci_ebus_init1(PCIDevice *s) |
408 | 53e3c4f9 | Blue Swirl | { |
409 | 0c5b8d83 | Blue Swirl | isa_bus_new(&s->qdev); |
410 | 0c5b8d83 | Blue Swirl | |
411 | deb54399 | aliguori | pci_config_set_vendor_id(s->config, PCI_VENDOR_ID_SUN); |
412 | deb54399 | aliguori | pci_config_set_device_id(s->config, PCI_DEVICE_ID_SUN_EBUS); |
413 | c190ea07 | blueswir1 | s->config[0x04] = 0x06; // command = bus master, pci mem |
414 | c190ea07 | blueswir1 | s->config[0x05] = 0x00; |
415 | c190ea07 | blueswir1 | s->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error |
416 | c190ea07 | blueswir1 | s->config[0x07] = 0x03; // status = medium devsel |
417 | c190ea07 | blueswir1 | s->config[0x08] = 0x01; // revision |
418 | c190ea07 | blueswir1 | s->config[0x09] = 0x00; // programming i/f |
419 | 173a543b | blueswir1 | pci_config_set_class(s->config, PCI_CLASS_BRIDGE_OTHER); |
420 | c190ea07 | blueswir1 | s->config[0x0D] = 0x0a; // latency_timer |
421 | 6407f373 | Isaku Yamahata | s->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
|
422 | c190ea07 | blueswir1 | |
423 | 0392a017 | Isaku Yamahata | pci_register_bar(s, 0, 0x1000000, PCI_BASE_ADDRESS_SPACE_MEMORY, |
424 | c190ea07 | blueswir1 | ebus_mmio_mapfunc); |
425 | 0392a017 | Isaku Yamahata | pci_register_bar(s, 1, 0x800000, PCI_BASE_ADDRESS_SPACE_MEMORY, |
426 | c190ea07 | blueswir1 | ebus_mmio_mapfunc); |
427 | 81a322d4 | Gerd Hoffmann | return 0; |
428 | c190ea07 | blueswir1 | } |
429 | c190ea07 | blueswir1 | |
430 | 53e3c4f9 | Blue Swirl | static PCIDeviceInfo ebus_info = {
|
431 | 53e3c4f9 | Blue Swirl | .qdev.name = "ebus",
|
432 | 53e3c4f9 | Blue Swirl | .qdev.size = sizeof(PCIDevice),
|
433 | 53e3c4f9 | Blue Swirl | .init = pci_ebus_init1, |
434 | 53e3c4f9 | Blue Swirl | }; |
435 | 53e3c4f9 | Blue Swirl | |
436 | 53e3c4f9 | Blue Swirl | static void pci_ebus_register(void) |
437 | 53e3c4f9 | Blue Swirl | { |
438 | 53e3c4f9 | Blue Swirl | pci_qdev_register(&ebus_info); |
439 | 53e3c4f9 | Blue Swirl | } |
440 | 53e3c4f9 | Blue Swirl | |
441 | 53e3c4f9 | Blue Swirl | device_init(pci_ebus_register); |
442 | 53e3c4f9 | Blue Swirl | |
443 | 1baffa46 | Blue Swirl | /* Boot PROM (OpenBIOS) */
|
444 | c227f099 | Anthony Liguori | static void prom_init(target_phys_addr_t addr, const char *bios_name) |
445 | 1baffa46 | Blue Swirl | { |
446 | 1baffa46 | Blue Swirl | DeviceState *dev; |
447 | 1baffa46 | Blue Swirl | SysBusDevice *s; |
448 | 1baffa46 | Blue Swirl | char *filename;
|
449 | 1baffa46 | Blue Swirl | int ret;
|
450 | 1baffa46 | Blue Swirl | |
451 | 1baffa46 | Blue Swirl | dev = qdev_create(NULL, "openprom"); |
452 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
453 | 1baffa46 | Blue Swirl | s = sysbus_from_qdev(dev); |
454 | 1baffa46 | Blue Swirl | |
455 | 1baffa46 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
456 | 1baffa46 | Blue Swirl | |
457 | 1baffa46 | Blue Swirl | /* load boot prom */
|
458 | 1baffa46 | Blue Swirl | if (bios_name == NULL) { |
459 | 1baffa46 | Blue Swirl | bios_name = PROM_FILENAME; |
460 | 1baffa46 | Blue Swirl | } |
461 | 1baffa46 | Blue Swirl | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
462 | 1baffa46 | Blue Swirl | if (filename) {
|
463 | ca20cf32 | Blue Swirl | ret = load_elf(filename, addr - PROM_VADDR, NULL, NULL, NULL, |
464 | ca20cf32 | Blue Swirl | 1, ELF_MACHINE, 0); |
465 | 1baffa46 | Blue Swirl | if (ret < 0 || ret > PROM_SIZE_MAX) { |
466 | 1baffa46 | Blue Swirl | ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); |
467 | 1baffa46 | Blue Swirl | } |
468 | 1baffa46 | Blue Swirl | qemu_free(filename); |
469 | 1baffa46 | Blue Swirl | } else {
|
470 | 1baffa46 | Blue Swirl | ret = -1;
|
471 | 1baffa46 | Blue Swirl | } |
472 | 1baffa46 | Blue Swirl | if (ret < 0 || ret > PROM_SIZE_MAX) { |
473 | 1baffa46 | Blue Swirl | fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
|
474 | 1baffa46 | Blue Swirl | exit(1);
|
475 | 1baffa46 | Blue Swirl | } |
476 | 1baffa46 | Blue Swirl | } |
477 | 1baffa46 | Blue Swirl | |
478 | 81a322d4 | Gerd Hoffmann | static int prom_init1(SysBusDevice *dev) |
479 | 1baffa46 | Blue Swirl | { |
480 | c227f099 | Anthony Liguori | ram_addr_t prom_offset; |
481 | 1baffa46 | Blue Swirl | |
482 | 1baffa46 | Blue Swirl | prom_offset = qemu_ram_alloc(PROM_SIZE_MAX); |
483 | 1baffa46 | Blue Swirl | sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM); |
484 | 81a322d4 | Gerd Hoffmann | return 0; |
485 | 1baffa46 | Blue Swirl | } |
486 | 1baffa46 | Blue Swirl | |
487 | 1baffa46 | Blue Swirl | static SysBusDeviceInfo prom_info = {
|
488 | 1baffa46 | Blue Swirl | .init = prom_init1, |
489 | 1baffa46 | Blue Swirl | .qdev.name = "openprom",
|
490 | 1baffa46 | Blue Swirl | .qdev.size = sizeof(SysBusDevice),
|
491 | 1baffa46 | Blue Swirl | .qdev.props = (Property[]) { |
492 | 1baffa46 | Blue Swirl | {/* end of property list */}
|
493 | 1baffa46 | Blue Swirl | } |
494 | 1baffa46 | Blue Swirl | }; |
495 | 1baffa46 | Blue Swirl | |
496 | 1baffa46 | Blue Swirl | static void prom_register_devices(void) |
497 | 1baffa46 | Blue Swirl | { |
498 | 1baffa46 | Blue Swirl | sysbus_register_withprop(&prom_info); |
499 | 1baffa46 | Blue Swirl | } |
500 | 1baffa46 | Blue Swirl | |
501 | 1baffa46 | Blue Swirl | device_init(prom_register_devices); |
502 | 1baffa46 | Blue Swirl | |
503 | bda42033 | Blue Swirl | |
504 | bda42033 | Blue Swirl | typedef struct RamDevice |
505 | bda42033 | Blue Swirl | { |
506 | bda42033 | Blue Swirl | SysBusDevice busdev; |
507 | 04843626 | Blue Swirl | uint64_t size; |
508 | bda42033 | Blue Swirl | } RamDevice; |
509 | bda42033 | Blue Swirl | |
510 | bda42033 | Blue Swirl | /* System RAM */
|
511 | 81a322d4 | Gerd Hoffmann | static int ram_init1(SysBusDevice *dev) |
512 | bda42033 | Blue Swirl | { |
513 | c227f099 | Anthony Liguori | ram_addr_t RAM_size, ram_offset; |
514 | bda42033 | Blue Swirl | RamDevice *d = FROM_SYSBUS(RamDevice, dev); |
515 | bda42033 | Blue Swirl | |
516 | bda42033 | Blue Swirl | RAM_size = d->size; |
517 | bda42033 | Blue Swirl | |
518 | bda42033 | Blue Swirl | ram_offset = qemu_ram_alloc(RAM_size); |
519 | bda42033 | Blue Swirl | sysbus_init_mmio(dev, RAM_size, ram_offset); |
520 | 81a322d4 | Gerd Hoffmann | return 0; |
521 | bda42033 | Blue Swirl | } |
522 | bda42033 | Blue Swirl | |
523 | c227f099 | Anthony Liguori | static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size) |
524 | bda42033 | Blue Swirl | { |
525 | bda42033 | Blue Swirl | DeviceState *dev; |
526 | bda42033 | Blue Swirl | SysBusDevice *s; |
527 | bda42033 | Blue Swirl | RamDevice *d; |
528 | bda42033 | Blue Swirl | |
529 | bda42033 | Blue Swirl | /* allocate RAM */
|
530 | bda42033 | Blue Swirl | dev = qdev_create(NULL, "memory"); |
531 | bda42033 | Blue Swirl | s = sysbus_from_qdev(dev); |
532 | bda42033 | Blue Swirl | |
533 | bda42033 | Blue Swirl | d = FROM_SYSBUS(RamDevice, s); |
534 | bda42033 | Blue Swirl | d->size = RAM_size; |
535 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
536 | bda42033 | Blue Swirl | |
537 | bda42033 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
538 | bda42033 | Blue Swirl | } |
539 | bda42033 | Blue Swirl | |
540 | bda42033 | Blue Swirl | static SysBusDeviceInfo ram_info = {
|
541 | bda42033 | Blue Swirl | .init = ram_init1, |
542 | bda42033 | Blue Swirl | .qdev.name = "memory",
|
543 | bda42033 | Blue Swirl | .qdev.size = sizeof(RamDevice),
|
544 | bda42033 | Blue Swirl | .qdev.props = (Property[]) { |
545 | 32a7ee98 | Gerd Hoffmann | DEFINE_PROP_UINT64("size", RamDevice, size, 0), |
546 | 32a7ee98 | Gerd Hoffmann | DEFINE_PROP_END_OF_LIST(), |
547 | bda42033 | Blue Swirl | } |
548 | bda42033 | Blue Swirl | }; |
549 | bda42033 | Blue Swirl | |
550 | bda42033 | Blue Swirl | static void ram_register_devices(void) |
551 | bda42033 | Blue Swirl | { |
552 | bda42033 | Blue Swirl | sysbus_register_withprop(&ram_info); |
553 | bda42033 | Blue Swirl | } |
554 | bda42033 | Blue Swirl | |
555 | bda42033 | Blue Swirl | device_init(ram_register_devices); |
556 | bda42033 | Blue Swirl | |
557 | 7b833f5b | Blue Swirl | static CPUState *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef) |
558 | 3475187d | bellard | { |
559 | c68ea704 | bellard | CPUState *env; |
560 | 20c9f095 | blueswir1 | QEMUBH *bh; |
561 | e87231d4 | blueswir1 | ResetData *reset_info; |
562 | 3475187d | bellard | |
563 | c7ba218d | blueswir1 | if (!cpu_model)
|
564 | c7ba218d | blueswir1 | cpu_model = hwdef->default_cpu_model; |
565 | aaed909a | bellard | env = cpu_init(cpu_model); |
566 | aaed909a | bellard | if (!env) {
|
567 | 62724a37 | blueswir1 | fprintf(stderr, "Unable to find Sparc CPU definition\n");
|
568 | 62724a37 | blueswir1 | exit(1);
|
569 | 62724a37 | blueswir1 | } |
570 | 20c9f095 | blueswir1 | bh = qemu_bh_new(tick_irq, env); |
571 | 20c9f095 | blueswir1 | env->tick = ptimer_init(bh); |
572 | 20c9f095 | blueswir1 | ptimer_set_period(env->tick, 1ULL);
|
573 | 20c9f095 | blueswir1 | |
574 | 20c9f095 | blueswir1 | bh = qemu_bh_new(stick_irq, env); |
575 | 20c9f095 | blueswir1 | env->stick = ptimer_init(bh); |
576 | 20c9f095 | blueswir1 | ptimer_set_period(env->stick, 1ULL);
|
577 | 20c9f095 | blueswir1 | |
578 | 20c9f095 | blueswir1 | bh = qemu_bh_new(hstick_irq, env); |
579 | 20c9f095 | blueswir1 | env->hstick = ptimer_init(bh); |
580 | 20c9f095 | blueswir1 | ptimer_set_period(env->hstick, 1ULL);
|
581 | e87231d4 | blueswir1 | |
582 | e87231d4 | blueswir1 | reset_info = qemu_mallocz(sizeof(ResetData));
|
583 | e87231d4 | blueswir1 | reset_info->env = env; |
584 | 44a99354 | Blue Swirl | reset_info->prom_addr = hwdef->prom_addr; |
585 | a08d4367 | Jan Kiszka | qemu_register_reset(main_cpu_reset, reset_info); |
586 | c68ea704 | bellard | |
587 | 7b833f5b | Blue Swirl | return env;
|
588 | 7b833f5b | Blue Swirl | } |
589 | 7b833f5b | Blue Swirl | |
590 | c227f099 | Anthony Liguori | static void sun4uv_init(ram_addr_t RAM_size, |
591 | 7b833f5b | Blue Swirl | const char *boot_devices, |
592 | 7b833f5b | Blue Swirl | const char *kernel_filename, const char *kernel_cmdline, |
593 | 7b833f5b | Blue Swirl | const char *initrd_filename, const char *cpu_model, |
594 | 7b833f5b | Blue Swirl | const struct hwdef *hwdef) |
595 | 7b833f5b | Blue Swirl | { |
596 | 7b833f5b | Blue Swirl | CPUState *env; |
597 | c227f099 | Anthony Liguori | m48t59_t *nvram; |
598 | 7b833f5b | Blue Swirl | unsigned int i; |
599 | 7b833f5b | Blue Swirl | long initrd_size, kernel_size;
|
600 | 7b833f5b | Blue Swirl | PCIBus *pci_bus, *pci_bus2, *pci_bus3; |
601 | 7b833f5b | Blue Swirl | qemu_irq *irq; |
602 | f455e98c | Gerd Hoffmann | DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
603 | fd8014e1 | Gerd Hoffmann | DriveInfo *fd[MAX_FD]; |
604 | 7b833f5b | Blue Swirl | void *fw_cfg;
|
605 | 7b833f5b | Blue Swirl | |
606 | 7b833f5b | Blue Swirl | /* init CPUs */
|
607 | 7b833f5b | Blue Swirl | env = cpu_devinit(cpu_model, hwdef); |
608 | 7b833f5b | Blue Swirl | |
609 | bda42033 | Blue Swirl | /* set up devices */
|
610 | bda42033 | Blue Swirl | ram_init(0, RAM_size);
|
611 | 3475187d | bellard | |
612 | 1baffa46 | Blue Swirl | prom_init(hwdef->prom_addr, bios_name); |
613 | 3475187d | bellard | |
614 | 7d55273f | Igor Kovalenko | |
615 | 7d55273f | Igor Kovalenko | irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); |
616 | 7d55273f | Igor Kovalenko | pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, irq, &pci_bus2, |
617 | c190ea07 | blueswir1 | &pci_bus3); |
618 | 83469015 | bellard | isa_mem_base = VGA_BASE; |
619 | fbe1b595 | Paul Brook | pci_vga_init(pci_bus, 0, 0); |
620 | 83469015 | bellard | |
621 | c190ea07 | blueswir1 | // XXX Should be pci_bus3
|
622 | c190ea07 | blueswir1 | pci_ebus_init(pci_bus, -1);
|
623 | c190ea07 | blueswir1 | |
624 | e87231d4 | blueswir1 | i = 0;
|
625 | e87231d4 | blueswir1 | if (hwdef->console_serial_base) {
|
626 | e87231d4 | blueswir1 | serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200, |
627 | e87231d4 | blueswir1 | serial_hds[i], 1);
|
628 | e87231d4 | blueswir1 | i++; |
629 | e87231d4 | blueswir1 | } |
630 | e87231d4 | blueswir1 | for(; i < MAX_SERIAL_PORTS; i++) {
|
631 | 83469015 | bellard | if (serial_hds[i]) {
|
632 | ac0be998 | Gerd Hoffmann | serial_isa_init(i, serial_hds[i]); |
633 | 83469015 | bellard | } |
634 | 83469015 | bellard | } |
635 | 83469015 | bellard | |
636 | 83469015 | bellard | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { |
637 | 83469015 | bellard | if (parallel_hds[i]) {
|
638 | 021f0674 | Gerd Hoffmann | parallel_init(i, parallel_hds[i]); |
639 | 83469015 | bellard | } |
640 | 83469015 | bellard | } |
641 | 83469015 | bellard | |
642 | cb457d76 | aliguori | for(i = 0; i < nb_nics; i++) |
643 | 07caea31 | Markus Armbruster | pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL); |
644 | 83469015 | bellard | |
645 | e4bcb14c | ths | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
|
646 | e4bcb14c | ths | fprintf(stderr, "qemu: too many IDE bus\n");
|
647 | e4bcb14c | ths | exit(1);
|
648 | e4bcb14c | ths | } |
649 | e4bcb14c | ths | for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { |
650 | f455e98c | Gerd Hoffmann | hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, |
651 | 751c6a17 | Gerd Hoffmann | i % MAX_IDE_DEVS); |
652 | e4bcb14c | ths | } |
653 | e4bcb14c | ths | |
654 | 3b898dda | blueswir1 | pci_cmd646_ide_init(pci_bus, hd, 1);
|
655 | 3b898dda | blueswir1 | |
656 | 2e15e23b | Gerd Hoffmann | isa_create_simple("i8042");
|
657 | e4bcb14c | ths | for(i = 0; i < MAX_FD; i++) { |
658 | fd8014e1 | Gerd Hoffmann | fd[i] = drive_get(IF_FLOPPY, 0, i);
|
659 | e4bcb14c | ths | } |
660 | 86c86157 | Gerd Hoffmann | fdctrl_init_isa(fd); |
661 | f80237d4 | Blue Swirl | nvram = m48t59_init_isa(0x0074, NVRAM_SIZE, 59); |
662 | 636aa70a | Blue Swirl | |
663 | 636aa70a | Blue Swirl | initrd_size = 0;
|
664 | 636aa70a | Blue Swirl | kernel_size = sun4u_load_kernel(kernel_filename, initrd_filename, |
665 | 636aa70a | Blue Swirl | ram_size, &initrd_size); |
666 | 636aa70a | Blue Swirl | |
667 | 22548760 | blueswir1 | sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
|
668 | 0d31cb99 | blueswir1 | KERNEL_LOAD_ADDR, kernel_size, |
669 | 0d31cb99 | blueswir1 | kernel_cmdline, |
670 | 0d31cb99 | blueswir1 | INITRD_LOAD_ADDR, initrd_size, |
671 | 0d31cb99 | blueswir1 | /* XXX: need an option to load a NVRAM image */
|
672 | 0d31cb99 | blueswir1 | 0,
|
673 | 0d31cb99 | blueswir1 | graphic_width, graphic_height, graphic_depth, |
674 | 0d31cb99 | blueswir1 | (uint8_t *)&nd_table[0].macaddr);
|
675 | 83469015 | bellard | |
676 | 3cce6243 | blueswir1 | fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); |
677 | 3cce6243 | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
678 | 905fdcb5 | blueswir1 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
679 | 905fdcb5 | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
680 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
681 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
682 | 513f789f | blueswir1 | if (kernel_cmdline) {
|
683 | 9c9b0512 | Blue Swirl | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, |
684 | 9c9b0512 | Blue Swirl | strlen(kernel_cmdline) + 1);
|
685 | 6bb4ca57 | Blue Swirl | fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA, |
686 | 6bb4ca57 | Blue Swirl | (uint8_t*)strdup(kernel_cmdline), |
687 | 6bb4ca57 | Blue Swirl | strlen(kernel_cmdline) + 1);
|
688 | 513f789f | blueswir1 | } else {
|
689 | 9c9b0512 | Blue Swirl | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
|
690 | 513f789f | blueswir1 | } |
691 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); |
692 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); |
693 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]);
|
694 | 7589690c | Blue Swirl | |
695 | 7589690c | Blue Swirl | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); |
696 | 7589690c | Blue Swirl | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); |
697 | 7589690c | Blue Swirl | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); |
698 | 7589690c | Blue Swirl | |
699 | 513f789f | blueswir1 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
700 | 3475187d | bellard | } |
701 | 3475187d | bellard | |
702 | 905fdcb5 | blueswir1 | enum {
|
703 | 905fdcb5 | blueswir1 | sun4u_id = 0,
|
704 | 905fdcb5 | blueswir1 | sun4v_id = 64,
|
705 | e87231d4 | blueswir1 | niagara_id, |
706 | 905fdcb5 | blueswir1 | }; |
707 | 905fdcb5 | blueswir1 | |
708 | c7ba218d | blueswir1 | static const struct hwdef hwdefs[] = { |
709 | c7ba218d | blueswir1 | /* Sun4u generic PC-like machine */
|
710 | c7ba218d | blueswir1 | { |
711 | c7ba218d | blueswir1 | .default_cpu_model = "TI UltraSparc II",
|
712 | 905fdcb5 | blueswir1 | .machine_id = sun4u_id, |
713 | e87231d4 | blueswir1 | .prom_addr = 0x1fff0000000ULL,
|
714 | e87231d4 | blueswir1 | .console_serial_base = 0,
|
715 | c7ba218d | blueswir1 | }, |
716 | c7ba218d | blueswir1 | /* Sun4v generic PC-like machine */
|
717 | c7ba218d | blueswir1 | { |
718 | c7ba218d | blueswir1 | .default_cpu_model = "Sun UltraSparc T1",
|
719 | 905fdcb5 | blueswir1 | .machine_id = sun4v_id, |
720 | e87231d4 | blueswir1 | .prom_addr = 0x1fff0000000ULL,
|
721 | e87231d4 | blueswir1 | .console_serial_base = 0,
|
722 | e87231d4 | blueswir1 | }, |
723 | e87231d4 | blueswir1 | /* Sun4v generic Niagara machine */
|
724 | e87231d4 | blueswir1 | { |
725 | e87231d4 | blueswir1 | .default_cpu_model = "Sun UltraSparc T1",
|
726 | e87231d4 | blueswir1 | .machine_id = niagara_id, |
727 | e87231d4 | blueswir1 | .prom_addr = 0xfff0000000ULL,
|
728 | e87231d4 | blueswir1 | .console_serial_base = 0xfff0c2c000ULL,
|
729 | c7ba218d | blueswir1 | }, |
730 | c7ba218d | blueswir1 | }; |
731 | c7ba218d | blueswir1 | |
732 | c7ba218d | blueswir1 | /* Sun4u hardware initialisation */
|
733 | c227f099 | Anthony Liguori | static void sun4u_init(ram_addr_t RAM_size, |
734 | 3023f332 | aliguori | const char *boot_devices, |
735 | c7ba218d | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
736 | c7ba218d | blueswir1 | const char *initrd_filename, const char *cpu_model) |
737 | c7ba218d | blueswir1 | { |
738 | fbe1b595 | Paul Brook | sun4uv_init(RAM_size, boot_devices, kernel_filename, |
739 | c7ba218d | blueswir1 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
|
740 | c7ba218d | blueswir1 | } |
741 | c7ba218d | blueswir1 | |
742 | c7ba218d | blueswir1 | /* Sun4v hardware initialisation */
|
743 | c227f099 | Anthony Liguori | static void sun4v_init(ram_addr_t RAM_size, |
744 | 3023f332 | aliguori | const char *boot_devices, |
745 | c7ba218d | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
746 | c7ba218d | blueswir1 | const char *initrd_filename, const char *cpu_model) |
747 | c7ba218d | blueswir1 | { |
748 | fbe1b595 | Paul Brook | sun4uv_init(RAM_size, boot_devices, kernel_filename, |
749 | c7ba218d | blueswir1 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
|
750 | c7ba218d | blueswir1 | } |
751 | c7ba218d | blueswir1 | |
752 | e87231d4 | blueswir1 | /* Niagara hardware initialisation */
|
753 | c227f099 | Anthony Liguori | static void niagara_init(ram_addr_t RAM_size, |
754 | 3023f332 | aliguori | const char *boot_devices, |
755 | e87231d4 | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
756 | e87231d4 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
757 | e87231d4 | blueswir1 | { |
758 | fbe1b595 | Paul Brook | sun4uv_init(RAM_size, boot_devices, kernel_filename, |
759 | e87231d4 | blueswir1 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
|
760 | e87231d4 | blueswir1 | } |
761 | e87231d4 | blueswir1 | |
762 | f80f9ec9 | Anthony Liguori | static QEMUMachine sun4u_machine = {
|
763 | 66de733b | blueswir1 | .name = "sun4u",
|
764 | 66de733b | blueswir1 | .desc = "Sun4u platform",
|
765 | 66de733b | blueswir1 | .init = sun4u_init, |
766 | 1bcee014 | blueswir1 | .max_cpus = 1, // XXX for now |
767 | 0c257437 | Anthony Liguori | .is_default = 1,
|
768 | 3475187d | bellard | }; |
769 | c7ba218d | blueswir1 | |
770 | f80f9ec9 | Anthony Liguori | static QEMUMachine sun4v_machine = {
|
771 | 66de733b | blueswir1 | .name = "sun4v",
|
772 | 66de733b | blueswir1 | .desc = "Sun4v platform",
|
773 | 66de733b | blueswir1 | .init = sun4v_init, |
774 | 1bcee014 | blueswir1 | .max_cpus = 1, // XXX for now |
775 | c7ba218d | blueswir1 | }; |
776 | e87231d4 | blueswir1 | |
777 | f80f9ec9 | Anthony Liguori | static QEMUMachine niagara_machine = {
|
778 | e87231d4 | blueswir1 | .name = "Niagara",
|
779 | e87231d4 | blueswir1 | .desc = "Sun4v platform, Niagara",
|
780 | e87231d4 | blueswir1 | .init = niagara_init, |
781 | 1bcee014 | blueswir1 | .max_cpus = 1, // XXX for now |
782 | e87231d4 | blueswir1 | }; |
783 | f80f9ec9 | Anthony Liguori | |
784 | f80f9ec9 | Anthony Liguori | static void sun4u_machine_init(void) |
785 | f80f9ec9 | Anthony Liguori | { |
786 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&sun4u_machine); |
787 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&sun4v_machine); |
788 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&niagara_machine); |
789 | f80f9ec9 | Anthony Liguori | } |
790 | f80f9ec9 | Anthony Liguori | |
791 | f80f9ec9 | Anthony Liguori | machine_init(sun4u_machine_init); |