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# Date Author Comment
24c7f754 10/13/2012 01:39 pm Richard Henderson

tcg-sparc: Fix brcond2

Much the same problem as recently fixed for hppa.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>
ded37f0d 10/13/2012 01:39 pm Richard Henderson

tcg-sparc: Implement movcond.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>
0aed257f 10/06/2012 07:48 pm Richard Henderson

tcg: Add TCG_COND_NEVER, TCG_COND_ALWAYS

There are several cases that can be handled easier inside both
translators and code generators if we have out-of-band values
for conditions. It's easy enough to handle ALWAYS and NEVER in
the natural way inside the tcg middle-end....
626cd050 10/06/2012 07:47 pm Aurelien Jarno

tcg: remove obsolete jmp op

The TCG jmp operation doesn't really make sense in the QEMU context, it
is unused, it is not implemented by some targets, and it is wrongly
implemented by some others.

This patch simply removes it.

Reviewed-by: Richard Henderson <>...
04cbbdee 09/22/2012 08:59 pm Blue Swirl

Merge branch 'tcg-sparc' of git://repo.or.cz/qemu/rth

  • 'tcg-sparc' of git://repo.or.cz/qemu/rth:
    tcg-sparc: Preserve branch destinations during retranslation
    tcg-sparc: Fix and enable direct TB chaining.
    tcg-sparc: Add %g/%o registers to alloc_order...
6e17d0c5 09/22/2012 05:52 pm Stefan Weil

tcg: Remove tcg_target_get_call_iarg_regs_count

The TCG targets no longer need individual implementations.

Since commit 6a18ae2d2947532d5c26439548afa0481c4529f9,
'flags' is no longer used in tcg_target_get_call_iarg_regs_count.

The remaining tcg_target_get_call_iarg_regs_count is trivial and only...
f4bf0b91 09/21/2012 11:02 pm Richard Henderson

tcg-sparc: Preserve branch destinations during retranslation

Signed-off-by: Richard Henderson <>
26adfb75 09/21/2012 11:02 pm Richard Henderson

tcg-sparc: Add %g/%o registers to alloc_order

Signed-off-by: Richard Henderson <>
5bbd2cae 09/21/2012 11:02 pm Richard Henderson

tcg-sparc: Fix and enable direct TB chaining.

Signed-off-by: Richard Henderson <>
4c3204cb 09/21/2012 11:02 pm Richard Henderson

tcg-sparc: Clean up cruft stemming from attempts to use global registers.

Don't use -ffixed-gN. Don't link statically. Don't save/restore
AREG0 around calls. Don't allocate space on the stack for AREG0 save.

Signed-off-by: Richard Henderson <>
1fd95946 09/21/2012 11:02 pm Richard Henderson

tcg-sparc: Mask shift immediates to avoid illegal insns.

The xtensa-test image generates a sra_i32 with count 0x40.
Whether this is accident of tcg constant propagation or
originating directly from the instruction stream is immaterial.

Signed-off-by: Richard Henderson <>
375816f8 09/21/2012 11:02 pm Richard Henderson

tcg-sparc: Use defines for temporaries.

And change from %i4/%i5 to %g1/%o7 to remove a v8plus fixme.

Signed-off-by: Richard Henderson <>
c6f7e4fb 09/21/2012 11:02 pm Richard Henderson

tcg-sparc: Support GUEST_BASE.

Signed-off-by: Richard Henderson <>
0c554161 09/21/2012 11:02 pm Richard Henderson

tcg-sparc: Change AREG0 in generated code to %i0.

We can now move the TCG variable from %g56 to a call-preserved
windowed register.

Signed-off-by: Richard Henderson <>
a0ce341a 09/21/2012 11:02 pm Richard Henderson

tcg-sparc: Fix qemu_ld/st to handle 32-bit host.

At the same time, split out the tlb load logic to a new function.
Fixes the cases of two data registers and two address registers.
Fixes the signature of, and adds missing, qemu_ld/st opcodes.

Signed-off-by: Richard Henderson <>
9b9c37c3 09/21/2012 11:02 pm Richard Henderson

tcg-sparc: Assume v9 cpu always, i.e. force v8plus in 32-bit mode.

Current code doesn't actually work in 32-bit mode at all. Since
no one really noticed, drop the complication of v7 and v8 cpus.
Eliminate the --sparc_cpu configure option and standardize macro...
3ee60ad4 09/21/2012 11:02 pm Richard Henderson

tcg-sparc: Hack in qemu_ld/st64 for 32-bit.

Not actually implemented, but at least we avoid the tcg assert at startup.

Signed-off-by: Richard Henderson <>
a221ae3f 09/21/2012 11:02 pm Richard Henderson

tcg-sparc: Fix ADDX opcode.

Signed-off-by: Richard Henderson <>
89c33337 09/15/2012 08:51 pm Blue Swirl

Remove unused CONFIG_TCG_PASS_AREG0 and dead code

Now that CONFIG_TCG_PASS_AREG0 is enabled for all targets,
remove dead code and support for !CONFIG_TCG_PASS_AREG0 case.

Remove dyngen-exec.h and all references to it. Although included by
hw/spapr_hcall.c, it does not seem to use it....
cb1977d3 03/24/2012 09:57 pm Richard Henderson

tcg-sparc: Add debug_frame support.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>
5bd33de6 03/18/2012 09:15 pm Blue Swirl

tcg: fix sparc host for AREG0 free operation

e141ab52d2ea5d0bc6ad3b1ad32841127ca04adc didn't handle
the other memory access helper case, fix.

Signed-off-by: Blue Swirl <>
e141ab52 03/18/2012 02:21 pm Blue Swirl

softmmu templates: optionally pass CPUState to memory access functions

Optionally, make memory access helpers take a parameter for CPUState
instead of relying on global env.

On most targets, perform simple moves to reorder registers. On i386,
switch from regparm(3) calling convention to standard stack-based...
9349b4f9 03/14/2012 11:20 pm Andreas Färber

Rename CPUState -> CPUArchState

Scripted conversion:
for file in .[hc] hw/.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do
sed -i "s/CPUState/CPUArchState/g" $file
done...
9d6fca70 03/11/2012 01:28 pm Stefan Weil

tcg: Improve tcg_out_label and fix its usage for w64

tcg_out_label is always called with a third argument of pointer type
which was casted to tcg_target_long.

These casts can be avoided by changing the prototype of tcg_out_label.

There was also a cast to long. For most hosts with...
b08d26b7 11/19/2011 01:20 pm Richard Henderson

tcg-sparc: Fix set-but-not used warnings.

In both cases, val is computed, but then not used in the
subsequent line, which then re-computes the quantity in
a different type (int32_t vs unsigned long).

Keep the computation type that's been working so far....
2a534aff 11/14/2011 06:47 pm Richard Henderson

tcg: Use TCGReg for standard tcg-target entry points.

Including tcg_out_ld, tcg_out_st, tcg_out_mov, tcg_out_movi.

Signed-off-by: Richard Henderson <>
Reviewed-by: Andreas Färber <>
Reviewed-by: Stefan Weil <>...
26a74ae3 09/17/2011 08:55 pm Stefan Weil

tcg/sparc: Only one call output register needed for 64 bit hosts

The second register is only needed for 32 bit hosts.

Cc: Blue Swirl <>
Signed-off-by: Stefan Weil <>
Signed-off-by: Blue Swirl <>
f44c9960 06/26/2011 09:25 pm Blue Swirl

TCG/Sparc64: use stack for TCG temps

Use stack instead of temp_buf array in CPUState for TCG temps.

On Sparc64, stack pointer is not aligned but there is a fixed bias of 2047,
so don't try to enforce alignment.

Signed-off-by: Blue Swirl <>
614f104d 06/26/2011 09:25 pm Blue Swirl

Delegate setup of TCG temporaries to targets

Delegate TCG temp_buf setup to targets, so that they can use a stack
frame later instead.

Signed-off-by: Blue Swirl <>
cea5f9a2 06/26/2011 09:25 pm Blue Swirl

cpu-exec.c: avoid AREG0 use

Make functions take a parameter for CPUState instead of relying
on global env. Pass CPUState pointer to TCG prologue, which moves
it to AREG0.

Thanks to Peter Maydell and Laurent Desnogues for the ARM prologue
change.

Revert the hacks to avoid AREG0 use on Sparc hosts....
e4d58b41 06/09/2010 12:18 pm Richard Henderson

tcg: Make some tcg-target.c routines static.

Both tcg_target_init and tcg_target_qemu_prologue
are unused outside of tcg.c.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
3b6dac34 06/09/2010 12:18 pm Richard Henderson

tcg: Add TYPE parameter to tcg_out_mov.

Mirror tcg_out_movi in having a TYPE parameter. This allows x86_64
to perform the move at the proper width, which may elide a REX prefix.

Introduce a TCG_TYPE_REG enumerator to represent the "native width"
of the host register, and to distinguish the usage from "pointer data"...
355b1943 04/05/2010 02:28 am Paul Brook

Split TLB addend and target_phys_addr_t

Historically the qemu tlb "addend" field was used for both RAM and IO accesses,
so needed to be able to hold both host addresses (unsigned long) and guest
physical addresses (target_phys_addr_t). However since the introduction of...
86feb1c8 03/27/2010 12:01 am Richard Henderson

tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.

Some targets (e.g. Alpha and MIPS64) need to keep 32-bit operands
sign-extended in 64-bit registers (regardless of the "real" sign
of the operand). For that, we need to be able to distinguish
between a 32-bit load with a 32-bit result and a 32-bit load with...
8a56e840 03/26/2010 10:29 pm Richard Henderson

tcg: Use TCGCond where appropriate.

Use the TCGCond enumeration type in the brcond and setcond
related prototypes in tcg-op.h and each code generator.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
a9751609 03/26/2010 10:28 pm Richard Henderson

tcg: Name the opcode enumeration.

Give the enumeration formed from tcg-opc.h a name: TCGOpcode.
Use that enumeration type instead of "int" whereever appropriate.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
65850a02 03/13/2010 11:52 am Blue Swirl

Fix Sparc host build breakage

Fix error:
CC sparc-bsd-user/op_helper.o
In file included from /src/qemu/tcg/tcg.c:158:
/src/qemu/tcg/sparc/tcg-target.c:728:5: "TARGET_PHYS_ADDR_BITS" is not defined

Signed-off-by: Blue Swirl <>
30c0c76c 02/22/2010 06:38 pm Jay Foad

tcg: fix build on 32-bit hppa, ppc and sparc hosts

The qemu_ld32s op is only defined if TCG_TARGET_REG_BITS == 64.

Signed-off-by: Jay Foad <>
Signed-off-by: malc <>
18c8f7a3 02/20/2010 10:34 am Richard Henderson

tcg-sparc: Implement ORC.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>
dc69960d 02/20/2010 10:34 am Richard Henderson

tcg-sparc: Implement ANDC.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>
be6551b1 02/20/2010 10:32 am Richard Henderson

tcg-sparc: Implement not.

The fallback implementation of "ret = arg1 ^ -1" isn't ideal
because of the extra tcg op to load the minus one.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>
4b5a85c1 02/20/2010 10:31 am Richard Henderson

tcg-sparc: Implement neg.

The fallback implementation of "ret = 0 - arg1" isn't ideal,
first because of the extra tcg op to load the zero, and second
because we fail to handle zero as %g0 for arg1 of the sub.

Signed-off-by: Richard Henderson <>...
dbfe80e1 02/16/2010 07:53 pm Richard Henderson

tcg-sparc: Implement setcond, setcond2.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>
cc6dfecf 01/12/2010 09:59 pm Richard Henderson

tcg-sparc: Implement ext32[su]_i64

The 32-bit right-shift instructions is defined to extend the shifted
output to 64-bits. A shift count of zero therefore is a simple
extension without actually shifting.

Signed-off-by: Richard Henderson <>...
583d1215 01/12/2010 09:59 pm Richard Henderson

tcg-sparc: Implement division properly.

The {div,divu}2 opcodes are intended for systems for which the
division instruction produces both quotient and remainder. Sparc
is not such a system. Indeed, the remainder must be computed as

quot = a / b
  rem = a - (quot * b)...
5e143c43 01/12/2010 09:59 pm Richard Henderson

tcg-sparc: Do not remove %o012 from 'r' constraint.

Only 'L' constraint needs that.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>
7a3766f3 01/12/2010 09:59 pm Richard Henderson

tcg-sparc: Implement add2, sub2, mulu2.

Add missing 32-bit double-word support opcodes.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>
ba225198 01/12/2010 09:59 pm Richard Henderson

tcg-sparc: Add tcg_out_arithc.

Add a function to handle the register-vs-immediate test for arithmetic.

Also, adjust the OP_32_64 macro so that it auto-indents properly.
Rename the gen_arith32 label to gen_arith, since it handles 64-bit
arithmetic as well....
56f4927e 12/21/2009 10:52 pm Richard Henderson

tcg-sparc: Implement brcond2.

Split out tcg_out_cmp and properly handle immediate arguments.
Fix constraints on brcond to match what SUBCC accepts.
Add tcg_out_brcond2_i32 for 32-bit host.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>
a212ea75 12/21/2009 10:52 pm Richard Henderson

tcg-sparc: Use TCG_TARGET_REG_BITS in conditional compilation.

The test TCG_TARGET_REG_BITS==64 is exactly the feature that we
are checking for, whereas something involving sparc_v9 or
sparc_v8plus should be reserved for something ISA related,
as with SMULX....
43172207 12/21/2009 10:52 pm Richard Henderson

tcg-sparc: Improve tcg_out_movi for sparc64.

Generate sign-extended 32-bit constants with SETHI+XOR.
Otherwise tidy the routine to avoid the need for
conditional compilation and code duplication with movi_imm32.

Signed-off-by: Richard Henderson <>...
4a09aa89 12/21/2009 10:49 pm Richard Henderson

tcg-sparc: Fix imm13 check in movi.

We were unnecessarily restricting imm13 constants to 12 bits.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>
1da92db2 04/04/2009 10:10 pm blueswir1

Fix branches and TLB matches for 64 bit targets

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6974 c046a42c-6fe2-441c-8c8c-71466251a162
f843e528 04/04/2009 06:33 pm blueswir1

Allocate space for static call args, increase stack frame size on Sparc64

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6973 c046a42c-6fe2-441c-8c8c-71466251a162
d4a9eb1f 10/05/2008 12:59 pm blueswir1

Add some missing static and const qualifiers, reg_names only used if NDEBUG set

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5421 c046a42c-6fe2-441c-8c8c-71466251a162
9d0efc88 09/13/2008 11:07 pm blueswir1

Use 64 bit loads for tlb addend only if addend size is 64 bits

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5203 c046a42c-6fe2-441c-8c8c-71466251a162
79383c9c 08/30/2008 12:51 pm blueswir1

Fix some warnings that would be generated by gcc -Wredundant-decls

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162
6f41b777 08/17/2008 11:14 pm blueswir1

Fix 64 bit constant generation

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5020 c046a42c-6fe2-441c-8c8c-71466251a162
90cbed46 08/17/2008 07:13 pm blueswir1

Fix 32 bit address overflow

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5019 c046a42c-6fe2-441c-8c8c-71466251a162
bffe1431 08/17/2008 05:34 pm blueswir1

Restore AREG0 after calls

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5018 c046a42c-6fe2-441c-8c8c-71466251a162
56fc64df 08/16/2008 10:54 pm blueswir1

Sparc code generator update (fix qemu_ld & qemu_st)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5014 c046a42c-6fe2-441c-8c8c-71466251a162
53c37487 08/15/2008 09:14 pm blueswir1

Sparc code generator update

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5009 c046a42c-6fe2-441c-8c8c-71466251a162
e97b640d 07/26/2008 08:19 pm blueswir1

Try to avoid glibc global register mangling, again

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4953 c046a42c-6fe2-441c-8c8c-71466251a162
d795eb86 07/07/2008 10:34 pm blueswir1

Fix 64 bit constant generation

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4854 c046a42c-6fe2-441c-8c8c-71466251a162
8384dd67 05/25/2008 02:19 pm blueswir1

Implement byte swapping accesses

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4574 c046a42c-6fe2-441c-8c8c-71466251a162
b101234a 05/24/2008 09:09 pm blueswir1

Implement 64-bit constant loads

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4561 c046a42c-6fe2-441c-8c8c-71466251a162
26cc915c 05/24/2008 09:06 pm blueswir1

Use sethi and arith functions, fix comment

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4560 c046a42c-6fe2-441c-8c8c-71466251a162
57e49b40 05/18/2008 11:11 am blueswir1

Fix constant checks on Sparc64 host

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4486 c046a42c-6fe2-441c-8c8c-71466251a162
9a7f3228 05/17/2008 12:41 pm blueswir1

Fix qemu_ld/st branches, constification, use orcc for tst synthetic op

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4466 c046a42c-6fe2-441c-8c8c-71466251a162
f5ef6aac 05/16/2008 11:15 pm blueswir1

Implement qemu_ld/st, fix brcond, handle more corner cases

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4463 c046a42c-6fe2-441c-8c8c-71466251a162
cf7c2ca5 05/15/2008 10:44 pm blueswir1

Implement brcond, ldst with large offset; fix direct jump, prologue

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4461 c046a42c-6fe2-441c-8c8c-71466251a162
f02ca5cb 05/15/2008 08:30 pm blueswir1

Fix bit fitting checks

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4460 c046a42c-6fe2-441c-8c8c-71466251a162
7d551702 05/14/2008 10:22 pm blueswir1

Fix compilation on Sparc host, implement ld and st

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4457 c046a42c-6fe2-441c-8c8c-71466251a162
f54b3f92 04/12/2008 11:14 pm aurel32

HPPA (PA-RISC) host support

(Stuart Brady)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4199 c046a42c-6fe2-441c-8c8c-71466251a162
e4d5434c 03/13/2008 07:34 pm blueswir1

Fix i32 memory backed variables on 64-bit host

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4044 c046a42c-6fe2-441c-8c8c-71466251a162
0954d0d9 03/11/2008 11:01 pm blueswir1

Remove blank elements in tcg_target_reg_alloc_order[] (Stuart Brady)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4039 c046a42c-6fe2-441c-8c8c-71466251a162
b3db8758 03/08/2008 03:33 pm blueswir1

Add function prologue, fix pointer load on Sparc64 host

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4027 c046a42c-6fe2-441c-8c8c-71466251a162
53cd9273 03/07/2008 08:21 pm blueswir1

Update based on Stuart Brady's comments

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4026 c046a42c-6fe2-441c-8c8c-71466251a162
2f0a5008 02/29/2008 09:34 pm blueswir1

Fix register references (Igor Kovalenko)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4002 c046a42c-6fe2-441c-8c8c-71466251a162
8289b279 02/27/2008 07:53 pm blueswir1

Preliminary Sparc TCG target

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3995 c046a42c-6fe2-441c-8c8c-71466251a162