Archipelago » qemu

/*

 *  Alpha emulation cpu translation for qemu.

 *

 *  Copyright (c) 2007 Jocelyn Mayer

 *

 * This library is free software; you can redistribute it and/or

 * modify it under the terms of the GNU Lesser General Public

 * License as published by the Free Software Foundation; either

 * version 2 of the License, or (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public

 * License along with this library; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

 */

#include <stdint.h>

#include <stdlib.h>

#include <stdio.h>

#include "cpu.h"

#include "exec-all.h"

#include "disas.h"

#include "host-utils.h"

#include "helper.h"

#include "tcg-op.h"

#include "qemu-common.h"

#define DO_SINGLE_STEP

#define GENERATE_NOP

#define ALPHA_DEBUG_DISAS

#define DO_TB_FLUSH

typedef struct DisasContext DisasContext;

struct DisasContext {

    uint64_t pc;

    int mem_idx;

#if !defined (CONFIG_USER_ONLY)

    int pal_mode;

#endif

    uint32_t amask;

};

/* global register indexes */

static TCGv cpu_env;

static TCGv cpu_ir[31];

static TCGv cpu_pc;

/* dyngen register indexes */

static TCGv cpu_T[3];

/* register names */

static char cpu_reg_names[10*4+21*5];

#include "gen-icount.h"

static void alpha_translate_init(void)

{

    int i;

    char *p;

    static int done_init = 0;

    if (done_init)

        return;

    cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");

#if TARGET_LONG_BITS > HOST_LONG_BITS

    cpu_T[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,

                                  offsetof(CPUState, t0), "T0");

    cpu_T[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,

                                  offsetof(CPUState, t1), "T1");

    cpu_T[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,

                                  offsetof(CPUState, t2), "T2");

#else

    cpu_T[0] = tcg_global_reg_new(TCG_TYPE_I64, TCG_AREG1, "T0");

    cpu_T[1] = tcg_global_reg_new(TCG_TYPE_I64, TCG_AREG2, "T1");

    cpu_T[2] = tcg_global_reg_new(TCG_TYPE_I64, TCG_AREG3, "T2");

#endif

    p = cpu_reg_names;

    for (i = 0; i < 31; i++) {

        sprintf(p, "ir%d", i);

        cpu_ir[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,

                                       offsetof(CPUState, ir[i]), p);

        p += (i < 10) ? 4 : 5;

    }

    cpu_pc = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,

                                offsetof(CPUState, pc), "pc");

    /* register helpers */

#undef DEF_HELPER

#define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);

#include "helper.h"

    done_init = 1;

}

static always_inline void gen_op_nop (void)

{

#if defined(GENERATE_NOP)

    gen_op_no_op();

#endif

}

#define GEN32(func, NAME) \

static GenOpFunc *NAME ## _table [32] = {                                     \

NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \

NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \

NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \

NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \

NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19,                               \

NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \

NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \

NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \

};                                                                            \

static always_inline void func (int n)                                        \

{                                                                             \

    NAME ## _table[n]();                                                      \

}

/* FIR moves */

/* Special hacks for fir31 */

#define gen_op_load_FT0_fir31 gen_op_reset_FT0

#define gen_op_load_FT1_fir31 gen_op_reset_FT1

#define gen_op_load_FT2_fir31 gen_op_reset_FT2

#define gen_op_store_FT0_fir31 gen_op_nop

#define gen_op_store_FT1_fir31 gen_op_nop

#define gen_op_store_FT2_fir31 gen_op_nop

#define gen_op_cmov_fir31 gen_op_nop

GEN32(gen_op_load_FT0_fir, gen_op_load_FT0_fir);

GEN32(gen_op_load_FT1_fir, gen_op_load_FT1_fir);

GEN32(gen_op_load_FT2_fir, gen_op_load_FT2_fir);

GEN32(gen_op_store_FT0_fir, gen_op_store_FT0_fir);

GEN32(gen_op_store_FT1_fir, gen_op_store_FT1_fir);

GEN32(gen_op_store_FT2_fir, gen_op_store_FT2_fir);

GEN32(gen_op_cmov_fir, gen_op_cmov_fir);

static always_inline void gen_load_fir (DisasContext *ctx, int firn, int Tn)

{

    switch (Tn) {

    case 0:

        gen_op_load_FT0_fir(firn);

        break;

    case 1:

        gen_op_load_FT1_fir(firn);

        break;

    case 2:

        gen_op_load_FT2_fir(firn);

        break;

    }

}

static always_inline void gen_store_fir (DisasContext *ctx, int firn, int Tn)

{

    switch (Tn) {

    case 0:

        gen_op_store_FT0_fir(firn);

        break;

    case 1:

        gen_op_store_FT1_fir(firn);

        break;

    case 2:

        gen_op_store_FT2_fir(firn);

        break;

    }

}

/* Memory moves */

#if defined(CONFIG_USER_ONLY)

#define OP_LD_TABLE(width)                                                    \

static GenOpFunc *gen_op_ld##width[] = {                                      \

    &gen_op_ld##width##_raw,                                                  \

}

#define OP_ST_TABLE(width)                                                    \

static GenOpFunc *gen_op_st##width[] = {                                      \

    &gen_op_st##width##_raw,                                                  \

}

#else

#define OP_LD_TABLE(width)                                                    \

static GenOpFunc *gen_op_ld##width[] = {                                      \

    &gen_op_ld##width##_kernel,                                               \

    &gen_op_ld##width##_executive,                                            \

    &gen_op_ld##width##_supervisor,                                           \

    &gen_op_ld##width##_user,                                                 \

}

#define OP_ST_TABLE(width)                                                    \

static GenOpFunc *gen_op_st##width[] = {                                      \

    &gen_op_st##width##_kernel,                                               \

    &gen_op_st##width##_executive,                                            \

    &gen_op_st##width##_supervisor,                                           \

    &gen_op_st##width##_user,                                                 \

}

#endif

#define GEN_LD(width)                                                         \

OP_LD_TABLE(width);                                                           \

static always_inline void gen_ld##width (DisasContext *ctx)                   \

{                                                                             \

    (*gen_op_ld##width[ctx->mem_idx])();                                      \

}

#define GEN_ST(width)                                                         \

OP_ST_TABLE(width);                                                           \

static always_inline void gen_st##width (DisasContext *ctx)                   \

{                                                                             \

    (*gen_op_st##width[ctx->mem_idx])();                                      \

}

GEN_LD(bu);

GEN_ST(b);

GEN_LD(wu);

GEN_ST(w);

GEN_LD(l);

GEN_ST(l);

GEN_LD(q);

GEN_ST(q);

GEN_LD(q_u);

GEN_ST(q_u);

GEN_LD(l_l);

GEN_ST(l_c);

GEN_LD(q_l);

GEN_ST(q_c);

#if 0 /* currently unused */

GEN_LD(f);

GEN_ST(f);

GEN_LD(g);

GEN_ST(g);

#endif /* 0 */

GEN_LD(s);

GEN_ST(s);

GEN_LD(t);

GEN_ST(t);

static always_inline void _gen_op_bcond (DisasContext *ctx)

{

#if 0 // Qemu does not know how to do this...

    gen_op_bcond(ctx->pc);

#else

    gen_op_bcond(ctx->pc >> 32, ctx->pc);

#endif

}

static always_inline void gen_excp (DisasContext *ctx,

                                    int exception, int error_code)

{

    TCGv tmp1, tmp2;

    tcg_gen_movi_i64(cpu_pc, ctx->pc);

    tmp1 = tcg_const_i32(exception);

    tmp2 = tcg_const_i32(error_code);

    tcg_gen_helper_0_2(helper_excp, tmp1, tmp2);

    tcg_temp_free(tmp2);

    tcg_temp_free(tmp1);

}

static always_inline void gen_invalid (DisasContext *ctx)

{

    gen_excp(ctx, EXCP_OPCDEC, 0);

}

static always_inline void gen_load_mem (DisasContext *ctx,

                                        void (*gen_load_op)(DisasContext *ctx),

                                        int ra, int rb, int32_t disp16,

                                        int clear)

{

    if (ra == 31 && disp16 == 0) {

        /* UNOP */

        gen_op_nop();

    } else {

        if (rb != 31)

            tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);

        else

            tcg_gen_movi_i64(cpu_T[0], disp16);

        if (clear)

            tcg_gen_andi_i64(cpu_T[0], cpu_T[0], ~0x7);

        (*gen_load_op)(ctx);

        if (ra != 31)

            tcg_gen_mov_i64(cpu_ir[ra], cpu_T[1]);

    }

}

static always_inline void gen_store_mem (DisasContext *ctx,

                                         void (*gen_store_op)(DisasContext *ctx),

                                         int ra, int rb, int32_t disp16,

                                         int clear)

{

    if (rb != 31)

        tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);

    else

        tcg_gen_movi_i64(cpu_T[0], disp16);

    if (clear)

        tcg_gen_andi_i64(cpu_T[0], cpu_T[0], ~0x7);

    if (ra != 31)

        tcg_gen_mov_i64(cpu_T[1], cpu_ir[ra]);

    else

        tcg_gen_movi_i64(cpu_T[1], 0);

    (*gen_store_op)(ctx);

}

static always_inline void gen_load_fmem (DisasContext *ctx,

                                         void (*gen_load_fop)(DisasContext *ctx),

                                         int ra, int rb, int32_t disp16)

{

    if (rb != 31)

        tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);

    else

        tcg_gen_movi_i64(cpu_T[0], disp16);

    (*gen_load_fop)(ctx);

    gen_store_fir(ctx, ra, 1);

}

static always_inline void gen_store_fmem (DisasContext *ctx,

                                          void (*gen_store_fop)(DisasContext *ctx),

                                          int ra, int rb, int32_t disp16)

{

    if (rb != 31)

        tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);

    else

        tcg_gen_movi_i64(cpu_T[0], disp16);

    gen_load_fir(ctx, ra, 1);

    (*gen_store_fop)(ctx);

}

static always_inline void gen_bcond (DisasContext *ctx,

                                     TCGCond cond,

                                     int ra, int32_t disp16, int mask)

{

    int l1, l2;

    l1 = gen_new_label();

    l2 = gen_new_label();

    if (likely(ra != 31)) {

        if (mask) {

            TCGv tmp = tcg_temp_new(TCG_TYPE_I64);

            tcg_gen_andi_i64(tmp, cpu_ir[ra], 1);

            tcg_gen_brcondi_i64(cond, tmp, 0, l1);

            tcg_temp_free(tmp);

        } else

            tcg_gen_brcondi_i64(cond, cpu_ir[ra], 0, l1);

    } else {

        /* Very uncommon case - Do not bother to optimize.  */

        TCGv tmp = tcg_const_i64(0);

        tcg_gen_brcondi_i64(cond, tmp, 0, l1);

        tcg_temp_free(tmp);

    }

    tcg_gen_movi_i64(cpu_pc, ctx->pc);

    tcg_gen_br(l2);

    gen_set_label(l1);

    tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp16 << 2));

    gen_set_label(l2);

}

static always_inline void gen_fbcond (DisasContext *ctx,

                                      void (*gen_test_op)(void),

                                      int ra, int32_t disp16)

{

    tcg_gen_movi_i64(cpu_T[1], ctx->pc + (int64_t)(disp16 << 2));

    gen_load_fir(ctx, ra, 0);

    (*gen_test_op)();

    _gen_op_bcond(ctx);

}

static always_inline void gen_arith3 (DisasContext *ctx,

                                      void (*gen_arith_op)(void),

                                      int ra, int rb, int rc,

                                      int islit, uint8_t lit)

{

    if (ra != 31)

        tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);

    else

        tcg_gen_movi_i64(cpu_T[0], 0);

    if (islit)

        tcg_gen_movi_i64(cpu_T[1], lit);

    else

        tcg_gen_mov_i64(cpu_T[1], cpu_ir[rb]);

    (*gen_arith_op)();

    if (rc != 31)

        tcg_gen_mov_i64(cpu_ir[rc], cpu_T[0]);

}

static always_inline void gen_cmov (DisasContext *ctx,

                                    TCGCond inv_cond,

                                    int ra, int rb, int rc,

                                    int islit, uint8_t lit, int mask)

{

    int l1;

    if (unlikely(rc == 31))

        return;

    l1 = gen_new_label();

    if (ra != 31) {

        if (mask) {

            TCGv tmp = tcg_temp_new(TCG_TYPE_I64);

            tcg_gen_andi_i64(tmp, cpu_ir[ra], 1);

            tcg_gen_brcondi_i64(inv_cond, tmp, 0, l1);

            tcg_temp_free(tmp);

        } else

            tcg_gen_brcondi_i64(inv_cond, cpu_ir[ra], 0, l1);

    } else {

        /* Very uncommon case - Do not bother to optimize.  */

        TCGv tmp = tcg_const_i64(0);

        tcg_gen_brcondi_i64(inv_cond, tmp, 0, l1);

        tcg_temp_free(tmp);

    }

    if (islit)

        tcg_gen_movi_i64(cpu_ir[rc], lit);

    else

        tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);

    gen_set_label(l1);

}

static always_inline void gen_farith2 (DisasContext *ctx,

                                       void (*gen_arith_fop)(void),

                                       int rb, int rc)

{

    gen_load_fir(ctx, rb, 0);

    (*gen_arith_fop)();

    gen_store_fir(ctx, rc, 0);

}

static always_inline void gen_farith3 (DisasContext *ctx,

                                       void (*gen_arith_fop)(void),

                                       int ra, int rb, int rc)

{

    gen_load_fir(ctx, ra, 0);

    gen_load_fir(ctx, rb, 1);

    (*gen_arith_fop)();

    gen_store_fir(ctx, rc, 0);

}

static always_inline void gen_fcmov (DisasContext *ctx,

                                     void (*gen_test_fop)(void),

                                     int ra, int rb, int rc)

{

    gen_load_fir(ctx, ra, 0);

    gen_load_fir(ctx, rb, 1);

    (*gen_test_fop)();

    gen_op_cmov_fir(rc);

}

static always_inline void gen_fti (DisasContext *ctx,

                                   void (*gen_move_fop)(void),

                                   int ra, int rc)

{

    gen_load_fir(ctx, rc, 0);

    (*gen_move_fop)();

    if (ra != 31)

        tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]);

}

static always_inline void gen_itf (DisasContext *ctx,

                                   void (*gen_move_fop)(void),

                                   int ra, int rc)

{

    if (ra != 31)

        tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);

    else

        tcg_gen_movi_i64(cpu_T[0], 0);

    (*gen_move_fop)();

    gen_store_fir(ctx, rc, 0);

}

/* EXTWH, EXTWH, EXTLH, EXTQH */

static always_inline void gen_ext_h(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1),

                                    int ra, int rb, int rc,

                                    int islit, uint8_t lit)

{

    if (unlikely(rc == 31))

        return;

    if (ra != 31) {

        if (islit) {

            if (lit != 0)

                tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], 64 - ((lit & 7) * 8));

            else

                tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]);

        } else {

            TCGv tmp1, tmp2;

            tmp1 = tcg_temp_new(TCG_TYPE_I64);

            tcg_gen_andi_i64(tmp1, cpu_ir[rb], 7);

            tcg_gen_shli_i64(tmp1, tmp1, 3);

            tmp2 = tcg_const_i64(64);

            tcg_gen_sub_i64(tmp1, tmp2, tmp1);

            tcg_temp_free(tmp2);

            tcg_gen_shl_i64(cpu_ir[rc], cpu_ir[ra], tmp1);

            tcg_temp_free(tmp1);

        }

        if (tcg_gen_ext_i64)

            tcg_gen_ext_i64(cpu_ir[rc], cpu_ir[rc]);

    } else

        tcg_gen_movi_i64(cpu_ir[rc], 0);

}

/* EXTBL, EXTWL, EXTWL, EXTLL, EXTQL */

static always_inline void gen_ext_l(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1),

                                    int ra, int rb, int rc,

                                    int islit, uint8_t lit)

{

    if (unlikely(rc == 31))

        return;

    if (ra != 31) {

        if (islit) {

                tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[ra], (lit & 7) * 8);

        } else {

            TCGv tmp = tcg_temp_new(TCG_TYPE_I64);

            tcg_gen_andi_i64(tmp, cpu_ir[rb], 7);

            tcg_gen_shli_i64(tmp, tmp, 3);

            tcg_gen_shr_i64(cpu_ir[rc], cpu_ir[ra], tmp);

            tcg_temp_free(tmp);

        }

        if (tcg_gen_ext_i64)

            tcg_gen_ext_i64(cpu_ir[rc], cpu_ir[rc]);

    } else

        tcg_gen_movi_i64(cpu_ir[rc], 0);

}

/* Code to call byte manipulation helpers, used by:

   INSWH, INSLH, INSQH, INSBL, INSWL, INSLL, INSQL,

   MSKWH, MSKLH, MSKQH, MSKBL, MSKWL, MSKLL, MSKQL,

   ZAP, ZAPNOT

   WARNING: it assumes that when ra31 is used, the result is 0.

*/

static always_inline void gen_byte_manipulation(void *helper,

                                                int ra, int rb, int rc,

                                                int islit, uint8_t lit)

{

    if (unlikely(rc == 31))

        return;

    if (ra != 31) {

        if (islit) {

            TCGv tmp = tcg_const_i64(lit);

            tcg_gen_helper_1_2(helper, cpu_ir[rc], cpu_ir[ra], tmp);

            tcg_temp_free(tmp);

        } else

            tcg_gen_helper_1_2(helper, cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);

    } else

        tcg_gen_movi_i64(cpu_ir[rc], 0);

}

static always_inline void gen_cmp(TCGCond cond,

                                  int ra, int rb, int rc,

                                  int islit, int8_t lit)

{

    int l1, l2;

    TCGv tmp;

    if (unlikely(rc == 31))

    return;

    l1 = gen_new_label();

    l2 = gen_new_label();

    if (ra != 31) {

        tmp = tcg_temp_new(TCG_TYPE_I64);

        tcg_gen_mov_i64(tmp, cpu_ir[ra]);

    } else

        tmp = tcg_const_i64(0);

    if (islit)

        tcg_gen_brcondi_i64(cond, tmp, lit, l1);

    else

        tcg_gen_brcond_i64(cond, tmp, cpu_ir[rb], l1);

    tcg_gen_movi_i64(cpu_ir[rc], 0);

    tcg_gen_br(l2);

    gen_set_label(l1);

    tcg_gen_movi_i64(cpu_ir[rc], 1);

    gen_set_label(l2);

}

static always_inline int translate_one (DisasContext *ctx, uint32_t insn)

{

    uint32_t palcode;

    int32_t disp21, disp16, disp12;

    uint16_t fn11, fn16;

    uint8_t opc, ra, rb, rc, sbz, fpfn, fn7, fn2, islit;

    uint8_t lit;

    int ret;

    /* Decode all instruction fields */

    opc = insn >> 26;

    ra = (insn >> 21) & 0x1F;

    rb = (insn >> 16) & 0x1F;

    rc = insn & 0x1F;

    sbz = (insn >> 13) & 0x07;

    islit = (insn >> 12) & 1;

    if (rb == 31 && !islit) {

        islit = 1;

        lit = 0;

    } else

        lit = (insn >> 13) & 0xFF;

    palcode = insn & 0x03FFFFFF;

    disp21 = ((int32_t)((insn & 0x001FFFFF) << 11)) >> 11;

    disp16 = (int16_t)(insn & 0x0000FFFF);

    disp12 = (int32_t)((insn & 0x00000FFF) << 20) >> 20;

    fn16 = insn & 0x0000FFFF;

    fn11 = (insn >> 5) & 0x000007FF;

    fpfn = fn11 & 0x3F;

    fn7 = (insn >> 5) & 0x0000007F;

    fn2 = (insn >> 5) & 0x00000003;

    ret = 0;

#if defined ALPHA_DEBUG_DISAS

    if (logfile != NULL) {

        fprintf(logfile, "opc %02x ra %d rb %d rc %d disp16 %04x\n",

                opc, ra, rb, rc, disp16);

    }

#endif

    switch (opc) {

    case 0x00:

        /* CALL_PAL */

        if (palcode >= 0x80 && palcode < 0xC0) {

            /* Unprivileged PAL call */

            gen_excp(ctx, EXCP_CALL_PAL + ((palcode & 0x1F) << 6), 0);

#if !defined (CONFIG_USER_ONLY)

        } else if (palcode < 0x40) {

            /* Privileged PAL code */

            if (ctx->mem_idx & 1)

                goto invalid_opc;

            else

                gen_excp(ctx, EXCP_CALL_PALP + ((palcode & 0x1F) << 6), 0);

#endif

        } else {

            /* Invalid PAL call */

            goto invalid_opc;

        }

        ret = 3;

        break;

    case 0x01:

        /* OPC01 */

        goto invalid_opc;

    case 0x02:

        /* OPC02 */

        goto invalid_opc;

    case 0x03:

        /* OPC03 */

        goto invalid_opc;

    case 0x04:

        /* OPC04 */

        goto invalid_opc;

    case 0x05:

        /* OPC05 */

        goto invalid_opc;

    case 0x06:

        /* OPC06 */

        goto invalid_opc;

    case 0x07:

        /* OPC07 */

        goto invalid_opc;

    case 0x08:

        /* LDA */

        if (likely(ra != 31)) {

            if (rb != 31)

                tcg_gen_addi_i64(cpu_ir[ra], cpu_ir[rb], disp16);

            else

                tcg_gen_movi_i64(cpu_ir[ra], disp16);

        }

        break;

    case 0x09:

        /* LDAH */

        if (likely(ra != 31)) {

            if (rb != 31)

                tcg_gen_addi_i64(cpu_ir[ra], cpu_ir[rb], disp16 << 16);

            else

                tcg_gen_movi_i64(cpu_ir[ra], disp16 << 16);

        }

        break;

    case 0x0A:

        /* LDBU */

        if (!(ctx->amask & AMASK_BWX))

            goto invalid_opc;

        gen_load_mem(ctx, &gen_ldbu, ra, rb, disp16, 0);

        break;

    case 0x0B:

        /* LDQ_U */

        gen_load_mem(ctx, &gen_ldq_u, ra, rb, disp16, 1);

        break;

    case 0x0C:

        /* LDWU */

        if (!(ctx->amask & AMASK_BWX))

            goto invalid_opc;

        gen_load_mem(ctx, &gen_ldwu, ra, rb, disp16, 0);

        break;

    case 0x0D:

        /* STW */

        if (!(ctx->amask & AMASK_BWX))

            goto invalid_opc;

        gen_store_mem(ctx, &gen_stw, ra, rb, disp16, 0);

        break;

    case 0x0E:

        /* STB */

        if (!(ctx->amask & AMASK_BWX))

            goto invalid_opc;

        gen_store_mem(ctx, &gen_stb, ra, rb, disp16, 0);

        break;

    case 0x0F:

        /* STQ_U */

        gen_store_mem(ctx, &gen_stq_u, ra, rb, disp16, 1);

        break;

    case 0x10:

        switch (fn7) {

        case 0x00:

            /* ADDL */

            if (likely(rc != 31)) {

                if (ra != 31) {

                    if (islit) {

                        tcg_gen_addi_i64(cpu_ir[rc], cpu_ir[ra], lit);

                        tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);

                    } else {

                        tcg_gen_add_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);

                        tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);

                    }

                } else {

                    if (islit)

                        tcg_gen_movi_i64(cpu_ir[rc], lit);

                    else

                        tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]);

                }

            }

            break;

        case 0x02:

            /* S4ADDL */

            if (likely(rc != 31)) {

                if (ra != 31) {

                    TCGv tmp = tcg_temp_new(TCG_TYPE_I64);

                    tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);

                    if (islit)

                        tcg_gen_addi_i64(tmp, tmp, lit);

                    else

                        tcg_gen_add_i64(tmp, tmp, cpu_ir[rb]);

                    tcg_gen_ext32s_i64(cpu_ir[rc], tmp);

                    tcg_temp_free(tmp);

                } else {

                    if (islit)

                        tcg_gen_movi_i64(cpu_ir[rc], lit);

                    else

                        tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]);

                }

            }

            break;

        case 0x09:

            /* SUBL */

            if (likely(rc != 31)) {

                if (ra != 31) {

                    if (islit)

                        tcg_gen_subi_i64(cpu_ir[rc], cpu_ir[ra], lit);

                    else

                        tcg_gen_sub_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);

                    tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);

                } else {

                    if (islit)

                        tcg_gen_movi_i64(cpu_ir[rc], -lit);

                    else {

                        tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);

                        tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);

                }

            }

            break;

        case 0x0B:

            /* S4SUBL */

            if (likely(rc != 31)) {

                if (ra != 31) {

                    TCGv tmp = tcg_temp_new(TCG_TYPE_I64);

                    tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);

                    if (islit)

                        tcg_gen_subi_i64(tmp, tmp, lit);

                    else

                        tcg_gen_sub_i64(tmp, tmp, cpu_ir[rb]);

                    tcg_gen_ext32s_i64(cpu_ir[rc], tmp);

                    tcg_temp_free(tmp);

                } else {

                    if (islit)

                        tcg_gen_movi_i64(cpu_ir[rc], -lit);

                    else {

                        tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);

                        tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);

                    }

                }

            }

            break;

        case 0x0F:

            /* CMPBGE */

            gen_arith3(ctx, &gen_op_cmpbge, ra, rb, rc, islit, lit);

            break;

        case 0x12:

            /* S8ADDL */

            if (likely(rc != 31)) {

                if (ra != 31) {

                    TCGv tmp = tcg_temp_new(TCG_TYPE_I64);

                    tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);

                    if (islit)

                        tcg_gen_addi_i64(tmp, tmp, lit);

                    else

                        tcg_gen_add_i64(tmp, tmp, cpu_ir[rb]);

                    tcg_gen_ext32s_i64(cpu_ir[rc], tmp);

                    tcg_temp_free(tmp);

                } else {

                    if (islit)

                        tcg_gen_movi_i64(cpu_ir[rc], lit);

                    else

                        tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]);

                }

            }

            break;

        case 0x1B:

            /* S8SUBL */

            if (likely(rc != 31)) {

                if (ra != 31) {

                    TCGv tmp = tcg_temp_new(TCG_TYPE_I64);

                    tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);

                    if (islit)

                        tcg_gen_subi_i64(tmp, tmp, lit);

                    else

                       tcg_gen_sub_i64(tmp, tmp, cpu_ir[rb]);

                    tcg_gen_ext32s_i64(cpu_ir[rc], tmp);

                    tcg_temp_free(tmp);

                } else {

                    if (islit)

                        tcg_gen_movi_i64(cpu_ir[rc], -lit);

                    else

                        tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);

                        tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);

                    }

                }

            }

            break;

        case 0x1D:

            /* CMPULT */

            gen_cmp(TCG_COND_LTU, ra, rb, rc, islit, lit);

            break;

        case 0x20:

            /* ADDQ */

            if (likely(rc != 31)) {

                if (ra != 31) {

                    if (islit)

                        tcg_gen_addi_i64(cpu_ir[rc], cpu_ir[ra], lit);

                    else

                        tcg_gen_add_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);

                } else {

                    if (islit)

                        tcg_gen_movi_i64(cpu_ir[rc], lit);

                    else

                        tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);

                }

            }

            break;

        case 0x22:

            /* S4ADDQ */

            if (likely(rc != 31)) {

                if (ra != 31) {

                    TCGv tmp = tcg_temp_new(TCG_TYPE_I64);

                    tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);

                    if (islit)

                        tcg_gen_addi_i64(cpu_ir[rc], tmp, lit);

                    else

                        tcg_gen_add_i64(cpu_ir[rc], tmp, cpu_ir[rb]);

                    tcg_temp_free(tmp);

                } else {

                    if (islit)

                        tcg_gen_movi_i64(cpu_ir[rc], lit);

                    else

                        tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);

                }

            }

            break;

        case 0x29:

            /* SUBQ */