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Name Size
Makefile.objs 379 Bytes
STATUS 10.6 kB
cpu-models.c 64.1 kB
cpu-models.h 29.4 kB
cpu-qom.h 2.7 kB
cpu.h 87.5 kB
excp_helper.c 34.2 kB
fpu_helper.c 48.5 kB
helper.h 15.9 kB
helper_regs.h 3.4 kB
int_helper.c 52.8 kB
kvm.c 48.2 kB
kvm_ppc.c 1.1 kB
kvm_ppc.h 3.9 kB
machine.c 5.6 kB
mem_helper.c 8.1 kB
mfrom_table.c 3.3 kB
mfrom_table_gen.c 653 Bytes
misc_helper.c 3.5 kB
mmu-hash32.c 16 kB
mmu-hash32.h 3.2 kB
mmu-hash64.c 15.3 kB
mmu-hash64.h 4.5 kB
mmu_helper.c 84.8 kB
timebase_helper.c 4.3 kB
translate.c 364.1 kB
translate_init.c 293.2 kB
user_only_helper.c 1.4 kB

Latest revisions

# Date Author Comment
126a7930 05/06/2013 06:22 pm Alexander Graf

PPC: Add MMU type for 2.06 with AMR but no TB pages

When running -cpu on a POWER7 system with PR KVM, we mask out the 1TB
MMU capability from the MMU type mask, but not the AMR bit.

This leads to us having a new MMU type that we don't check for in our
MMU management functions....
c05541ee 05/06/2013 06:22 pm Anton Blanchard

target-ppc: Fix invalid SPR read/write warnings

Invalid and privileged SPR warnings currently print the wrong
address. While fixing that, also make it clear that we are
printing both the decimal and hexadecimal SPR number.

Before:

Trying to read invalid spr 896 380 at 0000000000000714...
04559d52 05/06/2013 06:22 pm Anton Blanchard

target-ppc: Add read and write of PPR SPR

Recent Linux kernels save and restore the PPR across exceptions
so we need to handle it.

Signed-off-by: Anton Blanchard <>
Signed-off-by: Alexander Graf <>
909eedb7 04/27/2013 01:37 am Aurelien Jarno

target-ppc: slightly optimize lfiwax

Signed-off-by: Aurelien Jarno <>
199f830d 04/27/2013 12:02 am Aurelien Jarno

target-ppc: emulate lfiwax instruction

Needed for Power ISA version 2.05 compliance.

Reviewed-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
[agraf: fix tcg debug error]
Signed-off-by: Alexander Graf <>
05050ee8 04/27/2013 12:02 am Aurelien Jarno

target-ppc: emulate load doubleword pair instructions

Needed for Power ISA version 2.05 compliance. The check for odd register
pairs is done using the invalid bits.

Signed-off-by: Aurelien Jarno <>
Signed-off-by: Alexander Graf <>
44bc0c4d 04/27/2013 12:02 am Aurelien Jarno

target-ppc: emulate store doubleword pair instructions

Needed for Power ISA version 2.05 compliance. The check for odd register
pairs is done using the invalid bits.

Signed-off-by: Aurelien Jarno <>
Signed-off-by: Alexander Graf <>
7d08d856 04/27/2013 12:02 am Aurelien Jarno

target-ppc: add support for extended mtfsf/mtfsfi forms

Power ISA 2.05 adds support for extended mtfsf/mtfsfi form, with a new
W field to select the upper part of the FPCSR register.

For that the helper is changed to handle 64-bit input values and mask with...
725bcec2 04/27/2013 12:02 am Aurelien Jarno

target-ppc: emulate prtyw and prtyd instructions

Needed for Power ISA version 2.05 compliance.

Reviewed-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
[agraf: fix 32-bit host compile, simplify code]
Signed-off-by: Alexander Graf <>
f0332888 04/27/2013 12:02 am Aurelien Jarno

target-ppc: emulate fcpsgn instruction

Needed for Power ISA version 2.05 compliance.

Reviewed-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
Signed-off-by: Alexander Graf <>

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