target-mips: fix TLBR wrt SEGMask
Like r4k_map_address(), r4k_helper_tlbp() should use SEGMask to mask theaddress.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: don't flush extra TLB on permissions upgrade
If the guest uses a TLBWI instruction for upgrading permissions, wedon't need to flush the extra TLBs. This improve boot time performanceby about 10%.
target-mips: don't use local temps for store conditional
Store conditional operations only need local temps in user mode. Fixthe code to use temp local only in user mode, this spares two memorystores in system mode.
At the same time remove a wrong a wrong copied & pasted comment,...
target-mips: implement movn/movz using movcond
Avoid the branches in movn/movz implementation and replace them withmovcond. Also update a wrong command.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: optimize ddiv/ddivu/div/divu with movcond
The result of a division by 0, or a division of INT_MIN by -1 in thesigned case, is unpredictable. Just replace 0 by 1 in that case so thatit doesn't trigger a floating point exception on the host....
target-mips: use deposit instead of hardcoded version
Use the deposit op instead of and hardcoded bit field insertion. Itallows the host to emit the corresponding instruction if available.
At the same time remove the (lsb > msb) test. The MIPS64R2 instruction...
target-mips: cleanup load/store operations
Load/store operations use macros for historical reasons. Now that thereis no point in keeping them, replace them by direct calls to qemu_ld/st.
target-mips: optimize load operations
Only allocate t1 when needed.
target-mips: simplify load/store microMIPS helpers
load/store microMIPS helpers are reinventing the wheel. Call do_lw,do_ll, do_sw and do_sl instead of using a macro calling the cpu_*load/store functions.
Reviewed-by: Richard Henderson <rth@twiddle.net>...
target-mips: implement unaligned loads using TCG
Load/store from helpers should be avoided as they are quiteinefficient. Rewrite unaligned loads instructions using TCG andaligned loads. The number of actual loads operations to implementan unaligned load instruction is reduced from up to 8 to 1....
target-mips: keep softfloat exception set to 0 between instructions
Instead of clearing the softfloat exception flags before each floatingpoint instruction, reset them to 0 in update_fcr31() when an exceptionis detected.
target-mips: fix FPU exceptions
For each FPU instruction that can trigger an FPU exception, to callcall update_fcr31() after.
Remove the manual NaN assignment in case of float to float operation, assoftfloat is already taking care of that. However for float to int...
target-mips: cleanup float to int conversion helpers
Instead of accessing the flags from the floating point controlregister after updating it, read the softfloat flags.
This is just code cleanup and should not change the behaviour.
target-mips: use softfloat constants when possible
softfloat already has a few constants defined, use them instead ofredefining them in target-mips.
Rename FLOAT_SNAN32 and FLOAT_SNAN64 to FP_TO_INT32_OVERFLOW andFP_TO_INT64_OVERFLOW as even if they have the same value, they are...
target-mips: restore CPU state after an FPU exception
Rework raise_exception() functions so that they can be called fromother helpers, passing the return address as an argument.
Use do_raise_exception() function in update_fcr31() to correctly restore...
target-mips: correctly restore btarget upon exception
When the CPU state is restored through retranslation after an exception,btarget should also be restored.
target-mips: do not save CPU state when using retranslation
When the CPU state after a possible retranslation is going to be handledthrough code retranslation, we don't need to save the CPU state before.
target-mips: use the softfloat floatXX_muladd functions
Use the new softfloat floatXX_muladd() functions to implement the madd,msub, nmadd and nmsub instructions. At the same time replace the name ofthe helpers by the name of the instruction, as the only reason for the...
target-mips: remove #if defined(TARGET_MIPS64) in opcode enums
All switch() decoding instruction have a default entry, so it is possibleto have unused enum entries. Remove conditional definitions of MIPS64opcode enums, as it only makes the code less readable....
target-mips: Change TODO file
Change DSP r1 & DSP r2 into microMIPS DSP encodings in TODO file.
Signed-off-by: Jia Liu <proljc@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: Add ASE DSP accumulator instructions
Add MIPS ASE DSP Accumulator and DSPControl Access instructions.
target-mips: Add ASE DSP processors
Add 74kf and mips64dspr2-generic-cpu model for test.
target-mips: Add ASE DSP compare-pick instructions
Add MIPS ASE DSP Compare-Pick instructions.
target-mips: Add ASE DSP multiply instructions
Add MIPS ASE DSP Multiply instructions.
target-mips: Add ASE DSP bit/manipulation instructions
Add MIPS ASE DSP Bit/Manipulation instructions.
target-mips: Add ASE DSP GPR-based shift instructions
Add MIPS ASE DSP GPR-Based Shift instructions.
target-mips: Add ASE DSP arithmetic instructions
Add MIPS ASE DSP Arithmetic instructions.
target-mips: Add ASE DSP load instructions
Add MIPS ASE DSP Load instructions.
target-mips: Add ASE DSP branch instructions
Add MIPS ASE DSP Branch instructions.
Use correct acc value to index cpu_HI/cpu_LO rather than using a fix number
target-mips: Add ASE DSP resources access check
Add MIPS ASE DSP resources access check.
target-mips: Add ASE DSP internal functions
Add internal functions using by MIPS ASE DSP instructions.
target-mips: Use TCG registers for the FPU.
With normal FP, this doesn't have much affect on the generated code,because most of the FP operations are not CONST/PURE, and so we spillregisters in about the same frequency as the explicit load/stores.
But with Loongson multimedia instructions, which are all integral and...
target-mips: rename helper flags
Rename helper flags to the new ones. This is purely a mechanical change,it's possible to use better flags by looking at the helpers.
Rename target_phys_addr_t to hwaddr
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes arereserved) and its purpose doesn't match the name (most target_phys_addr_taddresses are not target specific). Replace it with a finger-friendly,...
target-mips: Pass MIPSCPU to mips_vpe_is_wfi()
Needed for moving halted field to CPUState.The variable name "c" is retained for MIPSCPU to leave "cpu" for CPUState.
Also change return type to bool while at it.
Signed-off-by: Andreas Färber <afaerber@suse.de>...
target-mips: Pass MIPSCPU to mips_tc_sleep()
Needed for changing mips_vpe_sleep() argument type to MIPSCPU.
Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: Pass MIPSCPU to mips_vpe_sleep()
Needed for moving halted field to CPUState.
target-mips: Clean up other_cpu in helper_{d,e}vpe()
Free the variable name "other_cpu" for later use for MIPSCPU.
Fix off-by-one indentation while at it.
target-mips: Pass MIPSCPU to mips_tc_wake()
Needed for changing mips_vpe_is_wfi() argument type to MIPSCPU.
Emit debug_insn for CPU_LOG_TB_OP_OPT as well.
For all targets that currently call tcg_gen_debug_insn_start,add CPU_LOG_TB_OP_OPT to the condition that gates it.
This is useful for comparing optimization dumps, when thepre-optimization dump is merely noise....
target-mips: Implement Loongson Multimedia Instructions
Implements all of the COP2 instructions except for the S<cond>family of comparisons. The documentation is unclear for those.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: Set opn in gen_ldst_multiple.
Used by MIPS_DEBUG, when enabled.
Signed-off-by: Richard Henderson <rth@twiddle.net>Acked-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: Fix MIPS_DEBUG.
The macro uses the DisasContext. Pass it around as needed.
target-mips: Always evaluate debugging macro arguments
this will prevent some of the compilation errors with debuggingenabled from creeping back in.
target-mips: switch to AREG0 free mode
Add an explicit CPUState parameter instead of relying on AREG0and switch to AREG0 free mode.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Acked-by: Aurelien Jarno <aurelien@aurel32.net>
MIPS/user: Fix reset CPU state initialization
This change updates the CPU reset sequence to use a common piece of codethat figures out CPU state flags, fixing the problem with MIPS_HFLAG_COP1Xnot being set where applicable that causes floating-point MADD family...
target-mips: allow microMIPS SWP and SDP to have RD equal to BASE
The microMIPS SWP and SDP instructions do not modify GPRs. So theirbehavior is well defined when RD equals BASE. The MIPS ArchitectureVerification Programs (AVPs) check that they work as expected. This...
target-mips: add privilege level check to several Cop0 instructions
The MIPS Architecture Verification Programs (AVPs) check privilegedinstructions for the required privilege level. These changes are neededto pass the AVP suite.
Signed-off-by: Eric Johnson <ericj@mips.com>...
mips-linux-user: Always support rdhwr.
The kernel will emulate this instruction if it's not supportednatively. This insn is used for TLS, among other things, andso is required by modern glibc.
Signed-off-by: Richard Henderson <rth@twiddle.net>Cc: Riku Voipio <riku.voipio@iki.fi>...
target-mips: Streamline indexed cp1 memory addressing.
We've already eliminated both base and index being zero.
Fix order of CVT.PS.S operands
The FS input to CVT.PS.S is the high half and FT is the low half.tcg_gen_concat_i32_i64 takes the low half first, so the operandswere in the wrong order.
Signed-off-by: Richard Sandiford <rdsandiford@googlemail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Fix operands of RECIP2.S and RECIP2.PS
Read the second input operand of RECIP2.S and RECIP2.PS from FT ratherthan FD. RECIP2.D is already correct.
target-mips: Fix some helper functions (VR54xx multiplication)
Commits b5dc7732e1cc2fb549e48b7b5d664f2c79628e2e andbe24bb4f3007c3e07cbf1934f7e781493d876ab7 optimized the codeand removed the correct setting of t0. Fix this.
gcc-4.7 detected this bug because parameter arg1 was unused...
target-mips: Enable access to required RDHWR hardware registers
While running in the usermode emulator all of the required*MIPS32r2 RDHWR hardware registers should be accessible (theLinux kernel enables access to these same registers). Notethat these registers are still enabled when the MIPS ISA is...
MIPS: Correct FCR0 initialization
This change addresses a problem where QEMU incorrectly traps onfloating-point MADD group instructions with SIGILL, at least whileemulating MIPS32r2 processors. These instructions use the COP1X majoropcode and include ones like:...
build: move other target-*/ objects to nested Makefile.objs
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
build: move libobj-y variable to nested Makefile.objs
build: move obj-TARGET-y variables to nested Makefile.objs
Also drop duplicate occurrence of device-hotplug.o.
Kill off cpu_state_reset()
In commit 1bba0dc932e8826a7d030df3767daf0bc339f9a2 cpu_reset()was renamed to cpu_state_reset(), to allow introducing a new cpu_reset()that would operate on QOM objects.
All callers have been updated except for one in target-mips, so drop all...
target-mips: Use cpu_reset() in cpu_mips_init()
Commit 0f71a7095db6bc055bc5bb520d85ea650cca8a33 (target-mips: QOM'ifyCPU) hooked up cpu_state_reset() to CPUClass::reset(). Dropping theintroduction of subclasses for 1.1, due to mips_def_t the reset code...
target-mips: Use cpu_reset() in do_interrupt()
Signed-off-by: Andreas Färber <afaerber@suse.de>
target-mips: Let cpu_mips_init() return MIPSCPU
Turn cpu_init macro into a static inline function returning CPUMIPSStatefor backwards compatibility.
mips: Fix BC1ANY24F instructions
There's some dodgy application of De Morgan's law in the emulationof the MIPS BC1ANY24F instructions: they end up branching onlyif all CCs are false, rather than if one CC is.
Tested on mips64-linux-gnu, where it fixes the GCC MIPS3D tests....
target-mips: Remove commented-out function declaration
There is no function cpu_mips_get_clock(), so drop it.
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Stefan Weil <sw@weilnetz.de>
target-mips: Remove unused inline function
Function set_HILO is not needed anywhere.
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Merge branch 'qom-cpu-rest.v1' of git://github.com/afaerber/qemu-cpu
target-mips: QOM'ify CPU
Embed CPUMIPSState as first member of QOM MIPSCPU.
Let CPUClass::reset() call cpu_state_reset() for now.
Signed-off-by: Andreas Färber <afaerber@suse.de>Reviewed-by: Richard Henderson <rth@twiddle.net>
target-mips: Start QOM'ifying CPU init
Move code not dependent on mips_def_t from cpu_mips_init() into aQOM initfn, as a start.
target-mips: Move definition of uint_fast{8, 16}_t to osdep.h
osdep.h is included via qemu-common.h.
Prepares for use of [u]int_fast*_t types in softfloat code.
Signed-off-by: Andreas Färber <afaerber@suse.de>Cc: Ben Taylor <bentaylor.solx86@gmail.com>...
target-mips: Fix type cast for w64 (uintptr_t)
This changes nothing for other hosts.
Use uintptr_t for various op related functions
Use uintptr_t instead of void * or unsigned long inseveral op related functions, env->mem_io_pc andGETPC macro.
Reviewed-by: Stefan Weil <sw@weilnetz.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Replace Qemu by QEMU in comments
The official spelling is QEMU.
Signed-off-by: Stefan Weil <sw@weilnetz.de>Reviewed-by: Andreas Färber <afaerber@suse.de>[blauwirbel@gmail.com: fixed comment style in hw/sun4m.c]Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Replace Qemu by QEMU in internal documentation
Signed-off-by: Stefan Weil <sw@weilnetz.de>Reviewed-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-mips: Add compiler attribute to some functions which don't return
helper_raise_exception_err does not return, nor do helper_raise_exceptionand do_unaligned_access.
Cc: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Stefan Weil <sw@weilnetz.de>...
Rename CPUState -> CPUArchState
Scripted conversion: for file in .[hc] hw/.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do sed -i "s/CPUState/CPUArchState/g" $file done...
target-mips: Don't overuse CPUState
Scripted conversion: sed -i "s/CPUState/CPUMIPSState/g" target-mips/*.[hc] sed -i "s/#define CPUMIPSState/#define CPUState/" target-mips/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Anthony Liguori <aliguori@us.ibm.com>
Rename cpu_reset() to cpu_state_reset()
Frees the identifier cpu_reset for QOM CPUs (manual rename).
Don't hide the parameter type behind explicit casts, use staticfunctions with strongly typed argument to indirect.
Spelling fixes in comments (it's -> its)
Reviewed-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Stefan Weil <sw@weilnetz.de>...
target-mips: Clean includes
Remove some include statements which are not needed.
Cc: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Stefan Weil <sw@weilnetz.de>
Fix spelling in comments, documentation and messages
accidently->accidentallyannother->anotherchoosen->chosenconsideres->considersdecriptor->descriptordevelopement->developmentparamter->parameterpreceed->precedepreceeding->precedingpriviledge->privilege...
fix spelling in target sub directory
Cc: Richard Henderson <rth@twiddle.net>Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com>Cc: Aurelien Jarno <aurelien@aurel32.net>Cc: Alexander Graf <agraf@suse.de>Cc: Aurelien Jarno <aurelien@aurel32.net>Cc: Blue Swirl <blauwirbel@gmail.com>...
softmmu_header: pass CPUState to tlb_fill
Pass CPUState pointer to tlb_fill() instead of architecture localcpu_single_env hacks.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
mips: Default to using one VPE and one TC.
Boards can override the setup if needed.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
mips: Initialize MT state at reset
Only TC0 on VPE0 is active after reset. All other VPEs andTCs start in sleep.
mips: Add MT halting and waking of VPEs
+ some partial support for TC's.
mips: Support the MT TCStatus IXMT irq disable flag
mips: Handle TC indexing of other VPEs
Introduce mips_cpu_map_tc() to map a global TC index into a VPE nrand local tc index.
mips: Synchronize CP0 TCSTatus, Status and EntryHi
These registers share some of their fields. Writes to these fieldsshould be visible through the corresponding mirror fields.
mips: Hook in more reg accesses via mttr/mftr
mips: Correct IntCtl write mask for VInt
mips: Correct VInt vector generation
1. The pending need to pass the Status IM gating.2. The priority is from seven (highest prio) down to zero. QEMU was doing the opposite.
mips: Enable VInt interrupt mode for the 34Kf
Use glib memory allocation and free functions
qemu_malloc/qemu_free no longer exist after this commit.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Remove unused is_softmmu parameter from cpu_handle_mmu_fault
Parameter is_softmmu (and its evil mutant twin brother is_softmuu)is not used in cpu_*_handle_mmu_fault() functions, remove themand adjust callers.
Acked-by: Richard Henderson <rth@twiddle.net>...
exec.h cleanup
Move softmmu_exec.h include directives from target-*/exec.h totarget-*/op_helper.c. Move also various other stuff only used inop_helper.c there.
Define global env in dyngen-exec.h.
For i386, move wrappers for segment and FPU helpers from user-exec.c...
Fix unassigned memory access handling
cea5f9a28faa528b6b1b117c9ab2d8828f473fef exposed bugs in unassigned memoryaccess handling. Fix them by always passing CPUState to the handlers.
Reported-by: Hervé Poussineau <hpoussin@reactos.org>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Remove exec-all.h include directives
Most exec-all.h include directives are now useless, remove them.
Move cpu_has_work and cpu_pc_from_tb to cpu.h
Move functions cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h. This isneeded by later patches.
exec.h: fix coding style and change cpu_has_work to return bool
Before the next patch, fix coding style of the areas affected.
Change the type of the return value from cpu_has_work() andqemu_cpu_has_work() to bool.