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Name Size
Makefile.objs 465 Bytes
arm-semi.c 17.2 kB
cpu-qom.h 5.9 kB
cpu.c 32.5 kB
cpu.h 38.4 kB
cpu64.c 3.5 kB
crypto_helper.c 13 kB
gdbstub.c 2.8 kB
gdbstub64.c 1.9 kB
helper-a64.c 1.9 kB
helper-a64.h 1.1 kB
helper.c 139.4 kB
helper.h 17.4 kB
iwmmxt_helper.c 24.8 kB
kvm-consts.h 3.8 kB
kvm-stub.c 437 Bytes
kvm.c 9.4 kB
kvm32.c 15.7 kB
kvm64.c 5.2 kB
kvm_arm.h 3.8 kB
machine.c 7.9 kB
neon_helper.c 52.8 kB
op_addsub.h 1.8 kB
op_helper.c 8.9 kB
translate-a64.c 105.3 kB
translate.c 366 kB
translate.h 1.9 kB

Latest revisions

# Date Author Comment
f6d8a314 01/08/2014 09:07 pm Alexander Graf

target-arm: A64: Add support for dumping AArch64 VFP register state

When dumping the current CPU state, we can also get a request
to dump the FPU state along with the CPU's integer state.

Add support to dump the VFP state when that flag is set, so that
we can properly debug code that modifies floating point registers....
e2f90565 01/08/2014 09:07 pm Peter Maydell

target-arm: A64: Fix vector register access on bigendian hosts

The A64 128 bit vector registers are stored as a pair of
uint64_t values in the register array. This means that if
we're directly loading or storing a value of size less than
64 bits we must adjust the offset appropriately to account...
643dbb07 01/08/2014 09:07 pm Claudio Fontana

target-arm: A64: add support for add/sub with carry

This patch adds support for C3.5.3 Add/subtract (with carry):
instructions ADC, ADCS, SBC, SBCS.

Signed-off-by: Claudio Fontana <>
Signed-off-by: Peter Maydell <>...
750813cf 01/08/2014 09:07 pm Claudio Fontana

target-arm: A64: add support for conditional compare insns

this patch adds support for C3.5.4 - C3.5.5
Conditional compare (both immediate and register)

Signed-off-by: Claudio Fontana <>
Signed-off-by: Peter Maydell <>...
32b64e86 01/08/2014 09:07 pm Alexander Graf

target-arm: aarch64: add support for ld lit

Adds support for Load Register (literal), both normal
and SIMD/FP forms.

Signed-off-by: Alexander Graf <>
Signed-off-by: Alex Bennée <>
Signed-off-by: Peter Maydell <>...
03d05e2d 01/08/2014 09:07 pm Peter Maydell

target-arm: Widen exclusive-access support struct fields to 64 bits

In preparation for adding support for A64 load/store exclusive instructions,
widen the fields in the CPU state struct that deal with address and data values
for exclusives from 32 to 64 bits. Although in practice AArch64 and AArch32...
fa2ef212 01/08/2014 09:07 pm Michael Matz

target-arm: A64: support for ld/st/cl exclusive

This implement exclusive loads/stores for aarch64 along the lines of
arm32 and ppc implementations. The exclusive load remembers the address
and loaded value. The exclusive store throws an an exception which uses...
b0d2b7d0 01/07/2014 09:17 pm Peter Maydell

target-arm: A64: Implement minimal set of EL0-visible sysregs

Implement an initial minimal set of EL0-visible system registers: * NZCV * FPCR * FPSR * CTR_EL0 * DCZID_EL0

Signed-off-by: Peter Maydell <>
Reviewed-by: Richard Henderson <>...
e4fe830b 01/07/2014 09:17 pm Peter Maydell

target-arm: Widen thread-local register state fields to 64 bits

The common pattern for system registers in a 64-bit capable ARM
CPU is that when in AArch32 the cp15 register is a view of the
bottom 32 bits of the 64-bit AArch64 system register; writes in...
fea50522 01/07/2014 09:17 pm Peter Maydell

target-arm: A64: Implement MRS/MSR/SYS/SYSL

The AArch64 equivalent of the traditional AArch32
cp15 coprocessor registers is the set of instructions
MRS/MSR/SYS/SYSL, which cover between them both true
system registers and the "operations with side effects"...

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