root / target-sh4 / cpu.h @ e3b42536
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1 | fdf9b3e8 | bellard | /*
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2 | fdf9b3e8 | bellard | * SH4 emulation
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3 | 5fafdf24 | ths | *
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4 | fdf9b3e8 | bellard | * Copyright (c) 2005 Samuel Tardieu
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5 | fdf9b3e8 | bellard | *
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6 | fdf9b3e8 | bellard | * This library is free software; you can redistribute it and/or
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7 | fdf9b3e8 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | fdf9b3e8 | bellard | * License as published by the Free Software Foundation; either
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9 | fdf9b3e8 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | fdf9b3e8 | bellard | *
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11 | fdf9b3e8 | bellard | * This library is distributed in the hope that it will be useful,
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12 | fdf9b3e8 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | fdf9b3e8 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | fdf9b3e8 | bellard | * Lesser General Public License for more details.
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15 | fdf9b3e8 | bellard | *
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16 | fdf9b3e8 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | fdf9b3e8 | bellard | * License along with this library; if not, write to the Free Software
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18 | fad6cb1a | aurel32 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
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19 | fdf9b3e8 | bellard | */
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20 | fdf9b3e8 | bellard | #ifndef _CPU_SH4_H
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21 | fdf9b3e8 | bellard | #define _CPU_SH4_H
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22 | fdf9b3e8 | bellard | |
23 | fdf9b3e8 | bellard | #include "config.h" |
24 | fdf9b3e8 | bellard | |
25 | fdf9b3e8 | bellard | #define TARGET_LONG_BITS 32 |
26 | fdf9b3e8 | bellard | #define TARGET_HAS_ICE 1 |
27 | fdf9b3e8 | bellard | |
28 | 9042c0e2 | ths | #define ELF_MACHINE EM_SH
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29 | 9042c0e2 | ths | |
30 | 0fd3ca30 | aurel32 | /* CPU Subtypes */
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31 | 0fd3ca30 | aurel32 | #define SH_CPU_SH7750 (1 << 0) |
32 | 0fd3ca30 | aurel32 | #define SH_CPU_SH7750S (1 << 1) |
33 | 0fd3ca30 | aurel32 | #define SH_CPU_SH7750R (1 << 2) |
34 | 0fd3ca30 | aurel32 | #define SH_CPU_SH7751 (1 << 3) |
35 | 0fd3ca30 | aurel32 | #define SH_CPU_SH7751R (1 << 4) |
36 | a9c43f8e | aurel32 | #define SH_CPU_SH7785 (1 << 5) |
37 | 0fd3ca30 | aurel32 | #define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
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38 | 0fd3ca30 | aurel32 | #define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)
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39 | 0fd3ca30 | aurel32 | |
40 | c2764719 | pbrook | #define CPUState struct CPUSH4State |
41 | c2764719 | pbrook | |
42 | fdf9b3e8 | bellard | #include "cpu-defs.h" |
43 | fdf9b3e8 | bellard | |
44 | eda9b09b | bellard | #include "softfloat.h" |
45 | eda9b09b | bellard | |
46 | fdf9b3e8 | bellard | #define TARGET_PAGE_BITS 12 /* 4k XXXXX */ |
47 | fdf9b3e8 | bellard | |
48 | fdf9b3e8 | bellard | #define SR_MD (1 << 30) |
49 | fdf9b3e8 | bellard | #define SR_RB (1 << 29) |
50 | fdf9b3e8 | bellard | #define SR_BL (1 << 28) |
51 | fdf9b3e8 | bellard | #define SR_FD (1 << 15) |
52 | fdf9b3e8 | bellard | #define SR_M (1 << 9) |
53 | fdf9b3e8 | bellard | #define SR_Q (1 << 8) |
54 | 56cd2b96 | aurel32 | #define SR_I3 (1 << 7) |
55 | 56cd2b96 | aurel32 | #define SR_I2 (1 << 6) |
56 | 56cd2b96 | aurel32 | #define SR_I1 (1 << 5) |
57 | 56cd2b96 | aurel32 | #define SR_I0 (1 << 4) |
58 | fdf9b3e8 | bellard | #define SR_S (1 << 1) |
59 | fdf9b3e8 | bellard | #define SR_T (1 << 0) |
60 | fdf9b3e8 | bellard | |
61 | fdf9b3e8 | bellard | #define FPSCR_FR (1 << 21) |
62 | fdf9b3e8 | bellard | #define FPSCR_SZ (1 << 20) |
63 | fdf9b3e8 | bellard | #define FPSCR_PR (1 << 19) |
64 | fdf9b3e8 | bellard | #define FPSCR_DN (1 << 18) |
65 | 823029f9 | ths | #define DELAY_SLOT (1 << 0) |
66 | fdf9b3e8 | bellard | #define DELAY_SLOT_CONDITIONAL (1 << 1) |
67 | 823029f9 | ths | #define DELAY_SLOT_TRUE (1 << 2) |
68 | 823029f9 | ths | #define DELAY_SLOT_CLEARME (1 << 3) |
69 | 823029f9 | ths | /* The dynamic value of the DELAY_SLOT_TRUE flag determines whether the jump
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70 | 823029f9 | ths | * after the delay slot should be taken or not. It is calculated from SR_T.
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71 | 823029f9 | ths | *
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72 | 823029f9 | ths | * It is unclear if it is permitted to modify the SR_T flag in a delay slot.
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73 | 823029f9 | ths | * The use of DELAY_SLOT_TRUE flag makes us accept such SR_T modification.
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74 | 823029f9 | ths | */
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75 | fdf9b3e8 | bellard | |
76 | fdf9b3e8 | bellard | /* XXXXX The structure could be made more compact */
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77 | fdf9b3e8 | bellard | typedef struct tlb_t { |
78 | fdf9b3e8 | bellard | uint8_t asid; /* address space identifier */
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79 | fdf9b3e8 | bellard | uint32_t vpn; /* virtual page number */
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80 | fdf9b3e8 | bellard | uint8_t v; /* validity */
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81 | fdf9b3e8 | bellard | uint32_t ppn; /* physical page number */
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82 | fdf9b3e8 | bellard | uint8_t sz; /* page size */
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83 | fdf9b3e8 | bellard | uint32_t size; /* cached page size in bytes */
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84 | fdf9b3e8 | bellard | uint8_t sh; /* share status */
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85 | fdf9b3e8 | bellard | uint8_t c; /* cacheability */
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86 | fdf9b3e8 | bellard | uint8_t pr; /* protection key */
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87 | fdf9b3e8 | bellard | uint8_t d; /* dirty */
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88 | fdf9b3e8 | bellard | uint8_t wt; /* write through */
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89 | fdf9b3e8 | bellard | uint8_t sa; /* space attribute (PCMCIA) */
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90 | fdf9b3e8 | bellard | uint8_t tc; /* timing control */
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91 | fdf9b3e8 | bellard | } tlb_t; |
92 | fdf9b3e8 | bellard | |
93 | fdf9b3e8 | bellard | #define UTLB_SIZE 64 |
94 | fdf9b3e8 | bellard | #define ITLB_SIZE 4 |
95 | fdf9b3e8 | bellard | |
96 | 6ebbf390 | j_mayer | #define NB_MMU_MODES 2 |
97 | 6ebbf390 | j_mayer | |
98 | 71968fa6 | aurel32 | enum sh_features {
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99 | 71968fa6 | aurel32 | SH_FEATURE_SH4A = 1,
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100 | c2432a42 | aurel32 | SH_FEATURE_BCR3_AND_BCR4 = 2,
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101 | 71968fa6 | aurel32 | }; |
102 | 71968fa6 | aurel32 | |
103 | 852d481f | edgar_igl | typedef struct memory_content { |
104 | 852d481f | edgar_igl | uint32_t address; |
105 | 852d481f | edgar_igl | uint32_t value; |
106 | 852d481f | edgar_igl | struct memory_content *next;
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107 | 852d481f | edgar_igl | } memory_content; |
108 | 852d481f | edgar_igl | |
109 | fdf9b3e8 | bellard | typedef struct CPUSH4State { |
110 | 0fd3ca30 | aurel32 | int id; /* CPU model */ |
111 | 0fd3ca30 | aurel32 | |
112 | fdf9b3e8 | bellard | uint32_t flags; /* general execution flags */
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113 | fdf9b3e8 | bellard | uint32_t gregs[24]; /* general registers */ |
114 | e04ea3dc | ths | float32 fregs[32]; /* floating point registers */ |
115 | fdf9b3e8 | bellard | uint32_t sr; /* status register */
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116 | fdf9b3e8 | bellard | uint32_t ssr; /* saved status register */
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117 | fdf9b3e8 | bellard | uint32_t spc; /* saved program counter */
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118 | fdf9b3e8 | bellard | uint32_t gbr; /* global base register */
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119 | fdf9b3e8 | bellard | uint32_t vbr; /* vector base register */
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120 | fdf9b3e8 | bellard | uint32_t sgr; /* saved global register 15 */
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121 | fdf9b3e8 | bellard | uint32_t dbr; /* debug base register */
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122 | fdf9b3e8 | bellard | uint32_t pc; /* program counter */
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123 | fdf9b3e8 | bellard | uint32_t delayed_pc; /* target of delayed jump */
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124 | fdf9b3e8 | bellard | uint32_t mach; /* multiply and accumulate high */
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125 | fdf9b3e8 | bellard | uint32_t macl; /* multiply and accumulate low */
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126 | fdf9b3e8 | bellard | uint32_t pr; /* procedure register */
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127 | fdf9b3e8 | bellard | uint32_t fpscr; /* floating point status/control register */
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128 | fdf9b3e8 | bellard | uint32_t fpul; /* floating point communication register */
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129 | fdf9b3e8 | bellard | |
130 | 17b086f7 | aurel32 | /* float point status register */
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131 | ea6cf6be | ths | float_status fp_status; |
132 | eda9b09b | bellard | |
133 | 71968fa6 | aurel32 | /* The features that we should emulate. See sh_features above. */
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134 | 71968fa6 | aurel32 | uint32_t features; |
135 | 71968fa6 | aurel32 | |
136 | fdf9b3e8 | bellard | /* Those belong to the specific unit (SH7750) but are handled here */
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137 | fdf9b3e8 | bellard | uint32_t mmucr; /* MMU control register */
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138 | fdf9b3e8 | bellard | uint32_t pteh; /* page table entry high register */
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139 | fdf9b3e8 | bellard | uint32_t ptel; /* page table entry low register */
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140 | fdf9b3e8 | bellard | uint32_t ptea; /* page table entry assistance register */
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141 | fdf9b3e8 | bellard | uint32_t ttb; /* tranlation table base register */
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142 | fdf9b3e8 | bellard | uint32_t tea; /* TLB exception address register */
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143 | fdf9b3e8 | bellard | uint32_t tra; /* TRAPA exception register */
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144 | fdf9b3e8 | bellard | uint32_t expevt; /* exception event register */
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145 | fdf9b3e8 | bellard | uint32_t intevt; /* interrupt event register */
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146 | fdf9b3e8 | bellard | |
147 | 0fd3ca30 | aurel32 | uint32_t pvr; /* Processor Version Register */
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148 | 0fd3ca30 | aurel32 | uint32_t prr; /* Processor Revision Register */
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149 | 0fd3ca30 | aurel32 | uint32_t cvr; /* Cache Version Register */
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150 | 0fd3ca30 | aurel32 | |
151 | 66c7c806 | aurel32 | uint32_t ldst; |
152 | 66c7c806 | aurel32 | |
153 | fdf9b3e8 | bellard | CPU_COMMON tlb_t utlb[UTLB_SIZE]; /* unified translation table */
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154 | fdf9b3e8 | bellard | tlb_t itlb[ITLB_SIZE]; /* instruction translation table */
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155 | e96e2044 | ths | void *intc_handle;
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156 | 833ed386 | aurel32 | int intr_at_halt; /* SR_BL ignored during sleep */ |
157 | 852d481f | edgar_igl | memory_content *movcal_backup; |
158 | 852d481f | edgar_igl | memory_content **movcal_backup_tail; |
159 | fdf9b3e8 | bellard | } CPUSH4State; |
160 | fdf9b3e8 | bellard | |
161 | aaed909a | bellard | CPUSH4State *cpu_sh4_init(const char *cpu_model); |
162 | fdf9b3e8 | bellard | int cpu_sh4_exec(CPUSH4State * s);
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163 | 5fafdf24 | ths | int cpu_sh4_signal_handler(int host_signum, void *pinfo, |
164 | 5a7b542b | ths | void *puc);
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165 | 42083220 | aurel32 | int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw, |
166 | 42083220 | aurel32 | int mmu_idx, int is_softmmu); |
167 | 42083220 | aurel32 | void do_interrupt(CPUSH4State * env);
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168 | 42083220 | aurel32 | |
169 | 0fd3ca30 | aurel32 | void sh4_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
170 | 29e179bc | aurel32 | void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
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171 | 29e179bc | aurel32 | uint32_t mem_value); |
172 | fdf9b3e8 | bellard | |
173 | 852d481f | edgar_igl | int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr);
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174 | 852d481f | edgar_igl | |
175 | 0b6d3ae0 | aurel32 | static inline void cpu_set_tls(CPUSH4State *env, target_ulong newtls) |
176 | 0b6d3ae0 | aurel32 | { |
177 | 0b6d3ae0 | aurel32 | env->gbr = newtls; |
178 | 0b6d3ae0 | aurel32 | } |
179 | 0b6d3ae0 | aurel32 | |
180 | ef7ec1c1 | aurel32 | void cpu_load_tlb(CPUSH4State * env);
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181 | ef7ec1c1 | aurel32 | |
182 | fdf9b3e8 | bellard | #include "softfloat.h" |
183 | fdf9b3e8 | bellard | |
184 | 9467d44c | ths | #define cpu_init cpu_sh4_init
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185 | 9467d44c | ths | #define cpu_exec cpu_sh4_exec
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186 | 9467d44c | ths | #define cpu_gen_code cpu_sh4_gen_code
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187 | 9467d44c | ths | #define cpu_signal_handler cpu_sh4_signal_handler
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188 | 0fd3ca30 | aurel32 | #define cpu_list sh4_cpu_list
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189 | 9467d44c | ths | |
190 | 6ebbf390 | j_mayer | /* MMU modes definitions */
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191 | 6ebbf390 | j_mayer | #define MMU_MODE0_SUFFIX _kernel
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192 | 6ebbf390 | j_mayer | #define MMU_MODE1_SUFFIX _user
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193 | 6ebbf390 | j_mayer | #define MMU_USER_IDX 1 |
194 | 6ebbf390 | j_mayer | static inline int cpu_mmu_index (CPUState *env) |
195 | 6ebbf390 | j_mayer | { |
196 | 6ebbf390 | j_mayer | return (env->sr & SR_MD) == 0 ? 1 : 0; |
197 | 6ebbf390 | j_mayer | } |
198 | 6ebbf390 | j_mayer | |
199 | 6e68e076 | pbrook | #if defined(CONFIG_USER_ONLY)
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200 | 6e68e076 | pbrook | static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) |
201 | 6e68e076 | pbrook | { |
202 | f8ed7070 | pbrook | if (newsp)
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203 | 6e68e076 | pbrook | env->gregs[15] = newsp;
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204 | 6e68e076 | pbrook | env->gregs[0] = 0; |
205 | 6e68e076 | pbrook | } |
206 | 6e68e076 | pbrook | #endif
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207 | 6e68e076 | pbrook | |
208 | fdf9b3e8 | bellard | #include "cpu-all.h" |
209 | 622ed360 | aliguori | #include "exec-all.h" |
210 | fdf9b3e8 | bellard | |
211 | fdf9b3e8 | bellard | /* Memory access type */
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212 | fdf9b3e8 | bellard | enum {
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213 | fdf9b3e8 | bellard | /* Privilege */
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214 | fdf9b3e8 | bellard | ACCESS_PRIV = 0x01,
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215 | fdf9b3e8 | bellard | /* Direction */
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216 | fdf9b3e8 | bellard | ACCESS_WRITE = 0x02,
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217 | fdf9b3e8 | bellard | /* Type of instruction */
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218 | fdf9b3e8 | bellard | ACCESS_CODE = 0x10,
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219 | fdf9b3e8 | bellard | ACCESS_INT = 0x20
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220 | fdf9b3e8 | bellard | }; |
221 | fdf9b3e8 | bellard | |
222 | fdf9b3e8 | bellard | /* MMU control register */
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223 | fdf9b3e8 | bellard | #define MMUCR 0x1F000010 |
224 | fdf9b3e8 | bellard | #define MMUCR_AT (1<<0) |
225 | fdf9b3e8 | bellard | #define MMUCR_SV (1<<8) |
226 | ea2b542a | aurel32 | #define MMUCR_URC_BITS (6) |
227 | ea2b542a | aurel32 | #define MMUCR_URC_OFFSET (10) |
228 | ea2b542a | aurel32 | #define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS) |
229 | ea2b542a | aurel32 | #define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET) |
230 | ea2b542a | aurel32 | static inline int cpu_mmucr_urc (uint32_t mmucr) |
231 | ea2b542a | aurel32 | { |
232 | ea2b542a | aurel32 | return ((mmucr & MMUCR_URC_MASK) >> MMUCR_URC_OFFSET);
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233 | ea2b542a | aurel32 | } |
234 | ea2b542a | aurel32 | |
235 | ea2b542a | aurel32 | /* PTEH : Page Translation Entry High register */
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236 | ea2b542a | aurel32 | #define PTEH_ASID_BITS (8) |
237 | ea2b542a | aurel32 | #define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS) |
238 | ea2b542a | aurel32 | #define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1) |
239 | ea2b542a | aurel32 | #define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK)
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240 | ea2b542a | aurel32 | #define PTEH_VPN_BITS (22) |
241 | ea2b542a | aurel32 | #define PTEH_VPN_OFFSET (10) |
242 | ea2b542a | aurel32 | #define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS) |
243 | ea2b542a | aurel32 | #define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET) |
244 | ea2b542a | aurel32 | static inline int cpu_pteh_vpn (uint32_t pteh) |
245 | ea2b542a | aurel32 | { |
246 | ea2b542a | aurel32 | return ((pteh & PTEH_VPN_MASK) >> PTEH_VPN_OFFSET);
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247 | ea2b542a | aurel32 | } |
248 | ea2b542a | aurel32 | |
249 | ea2b542a | aurel32 | /* PTEL : Page Translation Entry Low register */
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250 | ea2b542a | aurel32 | #define PTEL_V (1 << 8) |
251 | ea2b542a | aurel32 | #define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8) |
252 | ea2b542a | aurel32 | #define PTEL_C (1 << 3) |
253 | ea2b542a | aurel32 | #define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3) |
254 | ea2b542a | aurel32 | #define PTEL_D (1 << 2) |
255 | ea2b542a | aurel32 | #define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2) |
256 | ea2b542a | aurel32 | #define PTEL_SH (1 << 1) |
257 | ea2b542a | aurel32 | #define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1) |
258 | ea2b542a | aurel32 | #define PTEL_WT (1 << 0) |
259 | ea2b542a | aurel32 | #define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT)
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260 | ea2b542a | aurel32 | |
261 | ea2b542a | aurel32 | #define PTEL_SZ_HIGH_OFFSET (7) |
262 | ea2b542a | aurel32 | #define PTEL_SZ_HIGH (1 << PTEL_SZ_HIGH_OFFSET) |
263 | ea2b542a | aurel32 | #define PTEL_SZ_LOW_OFFSET (4) |
264 | ea2b542a | aurel32 | #define PTEL_SZ_LOW (1 << PTEL_SZ_LOW_OFFSET) |
265 | ea2b542a | aurel32 | static inline int cpu_ptel_sz (uint32_t ptel) |
266 | ea2b542a | aurel32 | { |
267 | ea2b542a | aurel32 | int sz;
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268 | ea2b542a | aurel32 | sz = (ptel & PTEL_SZ_HIGH) >> PTEL_SZ_HIGH_OFFSET; |
269 | ea2b542a | aurel32 | sz <<= 1;
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270 | ea2b542a | aurel32 | sz |= (ptel & PTEL_SZ_LOW) >> PTEL_SZ_LOW_OFFSET; |
271 | ea2b542a | aurel32 | return sz;
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272 | ea2b542a | aurel32 | } |
273 | ea2b542a | aurel32 | |
274 | ea2b542a | aurel32 | #define PTEL_PPN_BITS (19) |
275 | ea2b542a | aurel32 | #define PTEL_PPN_OFFSET (10) |
276 | ea2b542a | aurel32 | #define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS) |
277 | ea2b542a | aurel32 | #define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET) |
278 | ea2b542a | aurel32 | static inline int cpu_ptel_ppn (uint32_t ptel) |
279 | ea2b542a | aurel32 | { |
280 | ea2b542a | aurel32 | return ((ptel & PTEL_PPN_MASK) >> PTEL_PPN_OFFSET);
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281 | ea2b542a | aurel32 | } |
282 | ea2b542a | aurel32 | |
283 | ea2b542a | aurel32 | #define PTEL_PR_BITS (2) |
284 | ea2b542a | aurel32 | #define PTEL_PR_OFFSET (5) |
285 | ea2b542a | aurel32 | #define PTEL_PR_SIZE (1 << PTEL_PR_BITS) |
286 | ea2b542a | aurel32 | #define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET) |
287 | ea2b542a | aurel32 | static inline int cpu_ptel_pr (uint32_t ptel) |
288 | ea2b542a | aurel32 | { |
289 | ea2b542a | aurel32 | return ((ptel & PTEL_PR_MASK) >> PTEL_PR_OFFSET);
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290 | ea2b542a | aurel32 | } |
291 | ea2b542a | aurel32 | |
292 | ea2b542a | aurel32 | /* PTEA : Page Translation Entry Assistance register */
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293 | ea2b542a | aurel32 | #define PTEA_SA_BITS (3) |
294 | ea2b542a | aurel32 | #define PTEA_SA_SIZE (1 << PTEA_SA_BITS) |
295 | ea2b542a | aurel32 | #define PTEA_SA_MASK (PTEA_SA_SIZE - 1) |
296 | ea2b542a | aurel32 | #define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK)
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297 | ea2b542a | aurel32 | #define PTEA_TC (1 << 3) |
298 | ea2b542a | aurel32 | #define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3) |
299 | fdf9b3e8 | bellard | |
300 | 622ed360 | aliguori | static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) |
301 | 622ed360 | aliguori | { |
302 | 622ed360 | aliguori | env->pc = tb->pc; |
303 | 622ed360 | aliguori | env->flags = tb->flags; |
304 | 622ed360 | aliguori | } |
305 | 622ed360 | aliguori | |
306 | 852d481f | edgar_igl | #define TB_FLAG_PENDING_MOVCA (1 << 4) |
307 | 852d481f | edgar_igl | |
308 | 6b917547 | aliguori | static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
309 | 6b917547 | aliguori | target_ulong *cs_base, int *flags)
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310 | 6b917547 | aliguori | { |
311 | 6b917547 | aliguori | *pc = env->pc; |
312 | 6b917547 | aliguori | *cs_base = 0;
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313 | 6b917547 | aliguori | *flags = (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL |
314 | 6b917547 | aliguori | | DELAY_SLOT_TRUE | DELAY_SLOT_CLEARME)) /* Bits 0- 3 */
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315 | 6b917547 | aliguori | | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR)) /* Bits 19-21 */
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316 | d8299bcc | aurel32 | | (env->sr & (SR_MD | SR_RB)) /* Bits 29-30 */
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317 | 852d481f | edgar_igl | | (env->sr & SR_FD) /* Bit 15 */
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318 | 852d481f | edgar_igl | | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 4 */ |
319 | 6b917547 | aliguori | } |
320 | 6b917547 | aliguori | |
321 | fdf9b3e8 | bellard | #endif /* _CPU_SH4_H */ |