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1 | d4e8164f | bellard | /*
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2 | d4e8164f | bellard | * internal execution defines for qemu
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3 | 5fafdf24 | ths | *
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4 | d4e8164f | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | d4e8164f | bellard | *
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6 | d4e8164f | bellard | * This library is free software; you can redistribute it and/or
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7 | d4e8164f | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | d4e8164f | bellard | * License as published by the Free Software Foundation; either
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9 | d4e8164f | bellard | * version 2 of the License, or (at your option) any later version.
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10 | d4e8164f | bellard | *
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11 | d4e8164f | bellard | * This library is distributed in the hope that it will be useful,
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12 | d4e8164f | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | d4e8164f | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | d4e8164f | bellard | * Lesser General Public License for more details.
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15 | d4e8164f | bellard | *
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16 | d4e8164f | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | d4e8164f | bellard | */
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19 | d4e8164f | bellard | |
20 | 875cdcf6 | aliguori | #ifndef _EXEC_ALL_H_
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21 | 875cdcf6 | aliguori | #define _EXEC_ALL_H_
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22 | 7d99a001 | blueswir1 | |
23 | 7d99a001 | blueswir1 | #include "qemu-common.h" |
24 | 7d99a001 | blueswir1 | |
25 | b346ff46 | bellard | /* allow to see translation results - the slowdown should be negligible, so we leave it */
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26 | de9a95f0 | aurel32 | #define DEBUG_DISAS
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27 | b346ff46 | bellard | |
28 | 41c1b1c9 | Paul Brook | /* Page tracking code uses ram addresses in system mode, and virtual
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29 | 41c1b1c9 | Paul Brook | addresses in userspace mode. Define tb_page_addr_t to be an appropriate
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30 | 41c1b1c9 | Paul Brook | type. */
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31 | 41c1b1c9 | Paul Brook | #if defined(CONFIG_USER_ONLY)
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32 | b480d9b7 | Paul Brook | typedef abi_ulong tb_page_addr_t;
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33 | 41c1b1c9 | Paul Brook | #else
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34 | 41c1b1c9 | Paul Brook | typedef ram_addr_t tb_page_addr_t;
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35 | 41c1b1c9 | Paul Brook | #endif
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36 | 41c1b1c9 | Paul Brook | |
37 | b346ff46 | bellard | /* is_jmp field values */
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38 | b346ff46 | bellard | #define DISAS_NEXT 0 /* next instruction can be analyzed */ |
39 | b346ff46 | bellard | #define DISAS_JUMP 1 /* only pc was modified dynamically */ |
40 | b346ff46 | bellard | #define DISAS_UPDATE 2 /* cpu state was modified dynamically */ |
41 | b346ff46 | bellard | #define DISAS_TB_JUMP 3 /* only pc was modified statically */ |
42 | b346ff46 | bellard | |
43 | f081c76c | Blue Swirl | struct TranslationBlock;
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44 | 2e70f6ef | pbrook | typedef struct TranslationBlock TranslationBlock; |
45 | b346ff46 | bellard | |
46 | b346ff46 | bellard | /* XXX: make safe guess about sizes */
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47 | 5b620fb6 | Peter Maydell | #define MAX_OP_PER_INSTR 208 |
48 | 4d0e4ac7 | Stuart Brady | |
49 | 4d0e4ac7 | Stuart Brady | #if HOST_LONG_BITS == 32 |
50 | 4d0e4ac7 | Stuart Brady | #define MAX_OPC_PARAM_PER_ARG 2 |
51 | 4d0e4ac7 | Stuart Brady | #else
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52 | 4d0e4ac7 | Stuart Brady | #define MAX_OPC_PARAM_PER_ARG 1 |
53 | 4d0e4ac7 | Stuart Brady | #endif
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54 | 4d0e4ac7 | Stuart Brady | #define MAX_OPC_PARAM_IARGS 4 |
55 | 4d0e4ac7 | Stuart Brady | #define MAX_OPC_PARAM_OARGS 1 |
56 | 4d0e4ac7 | Stuart Brady | #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
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57 | 4d0e4ac7 | Stuart Brady | |
58 | 4d0e4ac7 | Stuart Brady | /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
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59 | 4d0e4ac7 | Stuart Brady | * and up to 4 + N parameters on 64-bit archs
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60 | 4d0e4ac7 | Stuart Brady | * (N = number of input arguments + output arguments). */
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61 | 4d0e4ac7 | Stuart Brady | #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS)) |
62 | 6db73509 | Aurelien Jarno | #define OPC_BUF_SIZE 640 |
63 | b346ff46 | bellard | #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
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64 | b346ff46 | bellard | |
65 | a208e54a | pbrook | /* Maximum size a TCG op can expand to. This is complicated because a
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66 | 0cbfcd2b | Aurelien Jarno | single op may require several host instructions and register reloads.
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67 | 0cbfcd2b | Aurelien Jarno | For now take a wild guess at 192 bytes, which should allow at least
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68 | a208e54a | pbrook | a couple of fixup instructions per argument. */
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69 | 0cbfcd2b | Aurelien Jarno | #define TCG_MAX_OP_SIZE 192 |
70 | a208e54a | pbrook | |
71 | 0115be31 | pbrook | #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
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72 | b346ff46 | bellard | |
73 | c27004ec | bellard | extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
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74 | b346ff46 | bellard | extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
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75 | 2e70f6ef | pbrook | extern uint16_t gen_opc_icount[OPC_BUF_SIZE];
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76 | b346ff46 | bellard | |
77 | 79383c9c | blueswir1 | #include "qemu-log.h" |
78 | b346ff46 | bellard | |
79 | 9349b4f9 | Andreas Färber | void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb); |
80 | 9349b4f9 | Andreas Färber | void gen_intermediate_code_pc(CPUArchState *env, struct TranslationBlock *tb); |
81 | 9349b4f9 | Andreas Färber | void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb, |
82 | e87b7cb0 | Stefan Weil | int pc_pos);
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83 | d2856f1a | aurel32 | |
84 | 57fec1fe | bellard | void cpu_gen_init(void); |
85 | 9349b4f9 | Andreas Färber | int cpu_gen_code(CPUArchState *env, struct TranslationBlock *tb, |
86 | d07bde88 | blueswir1 | int *gen_code_size_ptr);
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87 | 5fafdf24 | ths | int cpu_restore_state(struct TranslationBlock *tb, |
88 | 6375e09e | Stefan Weil | CPUArchState *env, uintptr_t searched_pc); |
89 | 38c30fb7 | Stefan Weil | void QEMU_NORETURN cpu_resume_from_signal(CPUArchState *env1, void *puc); |
90 | 20503968 | Blue Swirl | void QEMU_NORETURN cpu_io_recompile(CPUArchState *env, uintptr_t retaddr);
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91 | 9349b4f9 | Andreas Färber | TranslationBlock *tb_gen_code(CPUArchState *env, |
92 | 2e70f6ef | pbrook | target_ulong pc, target_ulong cs_base, int flags,
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93 | 2e70f6ef | pbrook | int cflags);
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94 | 9349b4f9 | Andreas Färber | void cpu_exec_init(CPUArchState *env);
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95 | 9349b4f9 | Andreas Färber | void QEMU_NORETURN cpu_loop_exit(CPUArchState *env1);
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96 | 6375e09e | Stefan Weil | int page_unprotect(target_ulong address, uintptr_t pc, void *puc); |
97 | 41c1b1c9 | Paul Brook | void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
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98 | 2e12669a | bellard | int is_cpu_write_access);
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99 | 77a8f1a5 | Alexander Graf | void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end,
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100 | 77a8f1a5 | Alexander Graf | int is_cpu_write_access);
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101 | 0cac1b66 | Blue Swirl | #if !defined(CONFIG_USER_ONLY)
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102 | 0cac1b66 | Blue Swirl | /* cputlb.c */
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103 | 9349b4f9 | Andreas Färber | void tlb_flush_page(CPUArchState *env, target_ulong addr);
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104 | 9349b4f9 | Andreas Färber | void tlb_flush(CPUArchState *env, int flush_global); |
105 | 9349b4f9 | Andreas Färber | void tlb_set_page(CPUArchState *env, target_ulong vaddr,
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106 | d4c430a8 | Paul Brook | target_phys_addr_t paddr, int prot,
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107 | d4c430a8 | Paul Brook | int mmu_idx, target_ulong size);
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108 | 1e7855a5 | Max Filippov | void tb_invalidate_phys_addr(target_phys_addr_t addr);
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109 | 0cac1b66 | Blue Swirl | #else
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110 | 0cac1b66 | Blue Swirl | static inline void tlb_flush_page(CPUArchState *env, target_ulong addr) |
111 | 0cac1b66 | Blue Swirl | { |
112 | 0cac1b66 | Blue Swirl | } |
113 | 0cac1b66 | Blue Swirl | |
114 | 0cac1b66 | Blue Swirl | static inline void tlb_flush(CPUArchState *env, int flush_global) |
115 | 0cac1b66 | Blue Swirl | { |
116 | 0cac1b66 | Blue Swirl | } |
117 | c527ee8f | Paul Brook | #endif
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118 | d4e8164f | bellard | |
119 | d4e8164f | bellard | #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ |
120 | d4e8164f | bellard | |
121 | 4390df51 | bellard | #define CODE_GEN_PHYS_HASH_BITS 15 |
122 | 4390df51 | bellard | #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS) |
123 | 4390df51 | bellard | |
124 | 26a5f13b | bellard | #define MIN_CODE_GEN_BUFFER_SIZE (1024 * 1024) |
125 | d4e8164f | bellard | |
126 | 4390df51 | bellard | /* estimated block size for TB allocation */
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127 | 4390df51 | bellard | /* XXX: use a per code average code fragment size and modulate it
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128 | 4390df51 | bellard | according to the host CPU */
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129 | 4390df51 | bellard | #if defined(CONFIG_SOFTMMU)
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130 | 4390df51 | bellard | #define CODE_GEN_AVG_BLOCK_SIZE 128 |
131 | 4390df51 | bellard | #else
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132 | 4390df51 | bellard | #define CODE_GEN_AVG_BLOCK_SIZE 64 |
133 | 4390df51 | bellard | #endif
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134 | 4390df51 | bellard | |
135 | a8cd70fc | Filip Navara | #if defined(_ARCH_PPC) || defined(__x86_64__) || defined(__arm__) || defined(__i386__)
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136 | d4e8164f | bellard | #define USE_DIRECT_JUMP
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137 | 7316329a | Stefan Weil | #elif defined(CONFIG_TCG_INTERPRETER)
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138 | 7316329a | Stefan Weil | #define USE_DIRECT_JUMP
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139 | d4e8164f | bellard | #endif
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140 | d4e8164f | bellard | |
141 | 2e70f6ef | pbrook | struct TranslationBlock {
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142 | 2e12669a | bellard | target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
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143 | 2e12669a | bellard | target_ulong cs_base; /* CS base for this block */
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144 | c068688b | j_mayer | uint64_t flags; /* flags defining in which context the code was generated */
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145 | d4e8164f | bellard | uint16_t size; /* size of target code for this block (1 <=
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146 | d4e8164f | bellard | size <= TARGET_PAGE_SIZE) */
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147 | 58fe2f10 | bellard | uint16_t cflags; /* compile flags */
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148 | 2e70f6ef | pbrook | #define CF_COUNT_MASK 0x7fff |
149 | 2e70f6ef | pbrook | #define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */ |
150 | 58fe2f10 | bellard | |
151 | d4e8164f | bellard | uint8_t *tc_ptr; /* pointer to the translated code */
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152 | 4390df51 | bellard | /* next matching tb for physical address. */
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153 | 5fafdf24 | ths | struct TranslationBlock *phys_hash_next;
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154 | 4390df51 | bellard | /* first and second physical page containing code. The lower bit
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155 | 4390df51 | bellard | of the pointer tells the index in page_next[] */
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156 | 5fafdf24 | ths | struct TranslationBlock *page_next[2]; |
157 | 41c1b1c9 | Paul Brook | tb_page_addr_t page_addr[2];
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158 | 4390df51 | bellard | |
159 | d4e8164f | bellard | /* the following data are used to directly call another TB from
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160 | d4e8164f | bellard | the code of this one. */
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161 | d4e8164f | bellard | uint16_t tb_next_offset[2]; /* offset of original jump target */ |
162 | d4e8164f | bellard | #ifdef USE_DIRECT_JUMP
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163 | efc0a514 | Filip Navara | uint16_t tb_jmp_offset[2]; /* offset of jump instruction */ |
164 | d4e8164f | bellard | #else
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165 | 6375e09e | Stefan Weil | uintptr_t tb_next[2]; /* address of jump generated code */ |
166 | d4e8164f | bellard | #endif
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167 | d4e8164f | bellard | /* list of TBs jumping to this one. This is a circular list using
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168 | d4e8164f | bellard | the two least significant bits of the pointers to tell what is
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169 | d4e8164f | bellard | the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
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170 | d4e8164f | bellard | jmp_first */
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171 | 5fafdf24 | ths | struct TranslationBlock *jmp_next[2]; |
172 | d4e8164f | bellard | struct TranslationBlock *jmp_first;
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173 | 2e70f6ef | pbrook | uint32_t icount; |
174 | 2e70f6ef | pbrook | }; |
175 | d4e8164f | bellard | |
176 | b362e5e0 | pbrook | static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc) |
177 | b362e5e0 | pbrook | { |
178 | b362e5e0 | pbrook | target_ulong tmp; |
179 | b362e5e0 | pbrook | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); |
180 | b5e19d4c | edgar_igl | return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
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181 | b362e5e0 | pbrook | } |
182 | b362e5e0 | pbrook | |
183 | 8a40a180 | bellard | static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc) |
184 | d4e8164f | bellard | { |
185 | b362e5e0 | pbrook | target_ulong tmp; |
186 | b362e5e0 | pbrook | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); |
187 | b5e19d4c | edgar_igl | return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
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188 | b5e19d4c | edgar_igl | | (tmp & TB_JMP_ADDR_MASK)); |
189 | d4e8164f | bellard | } |
190 | d4e8164f | bellard | |
191 | 41c1b1c9 | Paul Brook | static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc) |
192 | 4390df51 | bellard | { |
193 | f96a3834 | Aurelien Jarno | return (pc >> 2) & (CODE_GEN_PHYS_HASH_SIZE - 1); |
194 | 4390df51 | bellard | } |
195 | 4390df51 | bellard | |
196 | 2e70f6ef | pbrook | void tb_free(TranslationBlock *tb);
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197 | 9349b4f9 | Andreas Färber | void tb_flush(CPUArchState *env);
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198 | 41c1b1c9 | Paul Brook | void tb_link_page(TranslationBlock *tb,
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199 | 41c1b1c9 | Paul Brook | tb_page_addr_t phys_pc, tb_page_addr_t phys_page2); |
200 | 41c1b1c9 | Paul Brook | void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
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201 | d4e8164f | bellard | |
202 | 4390df51 | bellard | extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
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203 | d4e8164f | bellard | |
204 | 4390df51 | bellard | #if defined(USE_DIRECT_JUMP)
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205 | 4390df51 | bellard | |
206 | 7316329a | Stefan Weil | #if defined(CONFIG_TCG_INTERPRETER)
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207 | 7316329a | Stefan Weil | static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) |
208 | 7316329a | Stefan Weil | { |
209 | 7316329a | Stefan Weil | /* patch the branch destination */
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210 | 7316329a | Stefan Weil | *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
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211 | 7316329a | Stefan Weil | /* no need to flush icache explicitly */
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212 | 7316329a | Stefan Weil | } |
213 | 7316329a | Stefan Weil | #elif defined(_ARCH_PPC)
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214 | 64b85a8f | Blue Swirl | void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr); |
215 | 810260a8 | malc | #define tb_set_jmp_target1 ppc_tb_set_jmp_target
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216 | 57fec1fe | bellard | #elif defined(__i386__) || defined(__x86_64__)
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217 | 6375e09e | Stefan Weil | static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) |
218 | 4390df51 | bellard | { |
219 | 4390df51 | bellard | /* patch the branch destination */
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220 | 4390df51 | bellard | *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
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221 | 1235fc06 | ths | /* no need to flush icache explicitly */
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222 | 4390df51 | bellard | } |
223 | 811d4cf4 | balrog | #elif defined(__arm__)
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224 | 6375e09e | Stefan Weil | static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) |
225 | 811d4cf4 | balrog | { |
226 | 4a1e19ae | Aurelien Jarno | #if !QEMU_GNUC_PREREQ(4, 1) |
227 | 811d4cf4 | balrog | register unsigned long _beg __asm ("a1"); |
228 | 811d4cf4 | balrog | register unsigned long _end __asm ("a2"); |
229 | 811d4cf4 | balrog | register unsigned long _flg __asm ("a3"); |
230 | 3233f0d4 | balrog | #endif
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231 | 811d4cf4 | balrog | |
232 | 811d4cf4 | balrog | /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
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233 | 87b78ad1 | Laurent Desnogues | *(uint32_t *)jmp_addr = |
234 | 87b78ad1 | Laurent Desnogues | (*(uint32_t *)jmp_addr & ~0xffffff)
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235 | 87b78ad1 | Laurent Desnogues | | (((addr - (jmp_addr + 8)) >> 2) & 0xffffff); |
236 | 811d4cf4 | balrog | |
237 | 3233f0d4 | balrog | #if QEMU_GNUC_PREREQ(4, 1) |
238 | 4a1e19ae | Aurelien Jarno | __builtin___clear_cache((char *) jmp_addr, (char *) jmp_addr + 4); |
239 | 3233f0d4 | balrog | #else
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240 | 811d4cf4 | balrog | /* flush icache */
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241 | 811d4cf4 | balrog | _beg = jmp_addr; |
242 | 811d4cf4 | balrog | _end = jmp_addr + 4;
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243 | 811d4cf4 | balrog | _flg = 0;
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244 | 811d4cf4 | balrog | __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg)); |
245 | 3233f0d4 | balrog | #endif
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246 | 811d4cf4 | balrog | } |
247 | 7316329a | Stefan Weil | #else
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248 | 7316329a | Stefan Weil | #error tb_set_jmp_target1 is missing
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249 | 4390df51 | bellard | #endif
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250 | d4e8164f | bellard | |
251 | 5fafdf24 | ths | static inline void tb_set_jmp_target(TranslationBlock *tb, |
252 | 6375e09e | Stefan Weil | int n, uintptr_t addr)
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253 | 4cbb86e1 | bellard | { |
254 | 6375e09e | Stefan Weil | uint16_t offset = tb->tb_jmp_offset[n]; |
255 | 6375e09e | Stefan Weil | tb_set_jmp_target1((uintptr_t)(tb->tc_ptr + offset), addr); |
256 | 4cbb86e1 | bellard | } |
257 | 4cbb86e1 | bellard | |
258 | d4e8164f | bellard | #else
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259 | d4e8164f | bellard | |
260 | d4e8164f | bellard | /* set the jump target */
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261 | 5fafdf24 | ths | static inline void tb_set_jmp_target(TranslationBlock *tb, |
262 | 6375e09e | Stefan Weil | int n, uintptr_t addr)
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263 | d4e8164f | bellard | { |
264 | 95f7652d | bellard | tb->tb_next[n] = addr; |
265 | d4e8164f | bellard | } |
266 | d4e8164f | bellard | |
267 | d4e8164f | bellard | #endif
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268 | d4e8164f | bellard | |
269 | 5fafdf24 | ths | static inline void tb_add_jump(TranslationBlock *tb, int n, |
270 | d4e8164f | bellard | TranslationBlock *tb_next) |
271 | d4e8164f | bellard | { |
272 | cf25629d | bellard | /* NOTE: this test is only needed for thread safety */
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273 | cf25629d | bellard | if (!tb->jmp_next[n]) {
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274 | cf25629d | bellard | /* patch the native jump address */
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275 | 6375e09e | Stefan Weil | tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr); |
276 | 3b46e624 | ths | |
277 | cf25629d | bellard | /* add in TB jmp circular list */
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278 | cf25629d | bellard | tb->jmp_next[n] = tb_next->jmp_first; |
279 | 6375e09e | Stefan Weil | tb_next->jmp_first = (TranslationBlock *)((uintptr_t)(tb) | (n)); |
280 | cf25629d | bellard | } |
281 | d4e8164f | bellard | } |
282 | d4e8164f | bellard | |
283 | 6375e09e | Stefan Weil | TranslationBlock *tb_find_pc(uintptr_t pc_ptr); |
284 | a513fe19 | bellard | |
285 | d5975363 | pbrook | #include "qemu-lock.h" |
286 | d4e8164f | bellard | |
287 | c227f099 | Anthony Liguori | extern spinlock_t tb_lock;
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288 | d4e8164f | bellard | |
289 | 36bdbe54 | bellard | extern int tb_invalidated_flag; |
290 | 6e59c1db | bellard | |
291 | 3917149d | Blue Swirl | /* The return address may point to the start of the next instruction.
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292 | 3917149d | Blue Swirl | Subtracting one gets us the call instruction itself. */
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293 | 7316329a | Stefan Weil | #if defined(CONFIG_TCG_INTERPRETER)
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294 | 7316329a | Stefan Weil | /* Alpha and SH4 user mode emulations and Softmmu call GETPC().
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295 | 7316329a | Stefan Weil | For all others, GETPC remains undefined (which makes TCI a little faster. */
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296 | 7316329a | Stefan Weil | # if defined(CONFIG_SOFTMMU) || defined(TARGET_ALPHA) || defined(TARGET_SH4)
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297 | c3ca0467 | Stefan Weil | extern uintptr_t tci_tb_ptr;
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298 | 7316329a | Stefan Weil | # define GETPC() tci_tb_ptr
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299 | 7316329a | Stefan Weil | # endif
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300 | 7316329a | Stefan Weil | #elif defined(__s390__) && !defined(__s390x__)
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301 | 6375e09e | Stefan Weil | # define GETPC() \
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302 | 20503968 | Blue Swirl | (((uintptr_t)__builtin_return_address(0) & 0x7fffffffUL) - 1) |
303 | 3917149d | Blue Swirl | #elif defined(__arm__)
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304 | 3917149d | Blue Swirl | /* Thumb return addresses have the low bit set, so we need to subtract two.
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305 | 3917149d | Blue Swirl | This is still safe in ARM mode because instructions are 4 bytes. */
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306 | 20503968 | Blue Swirl | # define GETPC() ((uintptr_t)__builtin_return_address(0) - 2) |
307 | 3917149d | Blue Swirl | #else
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308 | 20503968 | Blue Swirl | # define GETPC() ((uintptr_t)__builtin_return_address(0) - 1) |
309 | 3917149d | Blue Swirl | #endif
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310 | 3917149d | Blue Swirl | |
311 | e95c8d51 | bellard | #if !defined(CONFIG_USER_ONLY)
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312 | 6e59c1db | bellard | |
313 | 37ec01d4 | Avi Kivity | struct MemoryRegion *iotlb_to_region(target_phys_addr_t index);
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314 | 37ec01d4 | Avi Kivity | uint64_t io_mem_read(struct MemoryRegion *mr, target_phys_addr_t addr,
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315 | 37ec01d4 | Avi Kivity | unsigned size);
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316 | 37ec01d4 | Avi Kivity | void io_mem_write(struct MemoryRegion *mr, target_phys_addr_t addr, |
317 | 37ec01d4 | Avi Kivity | uint64_t value, unsigned size);
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318 | b3755a91 | Paul Brook | |
319 | 9349b4f9 | Andreas Färber | void tlb_fill(CPUArchState *env1, target_ulong addr, int is_write, int mmu_idx, |
320 | 20503968 | Blue Swirl | uintptr_t retaddr); |
321 | 6e59c1db | bellard | |
322 | 79383c9c | blueswir1 | #include "softmmu_defs.h" |
323 | 79383c9c | blueswir1 | |
324 | 6ebbf390 | j_mayer | #define ACCESS_TYPE (NB_MMU_MODES + 1) |
325 | 6e59c1db | bellard | #define MEMSUFFIX _code
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326 | e141ab52 | Blue Swirl | #ifndef CONFIG_TCG_PASS_AREG0
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327 | 6e59c1db | bellard | #define env cpu_single_env
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328 | e141ab52 | Blue Swirl | #endif
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329 | 6e59c1db | bellard | |
330 | 6e59c1db | bellard | #define DATA_SIZE 1 |
331 | 6e59c1db | bellard | #include "softmmu_header.h" |
332 | 6e59c1db | bellard | |
333 | 6e59c1db | bellard | #define DATA_SIZE 2 |
334 | 6e59c1db | bellard | #include "softmmu_header.h" |
335 | 6e59c1db | bellard | |
336 | 6e59c1db | bellard | #define DATA_SIZE 4 |
337 | 6e59c1db | bellard | #include "softmmu_header.h" |
338 | 6e59c1db | bellard | |
339 | c27004ec | bellard | #define DATA_SIZE 8 |
340 | c27004ec | bellard | #include "softmmu_header.h" |
341 | c27004ec | bellard | |
342 | 6e59c1db | bellard | #undef ACCESS_TYPE
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343 | 6e59c1db | bellard | #undef MEMSUFFIX
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344 | 6e59c1db | bellard | #undef env
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345 | 6e59c1db | bellard | |
346 | 6e59c1db | bellard | #endif
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347 | 4390df51 | bellard | |
348 | 4390df51 | bellard | #if defined(CONFIG_USER_ONLY)
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349 | 9349b4f9 | Andreas Färber | static inline tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr) |
350 | 4390df51 | bellard | { |
351 | 4390df51 | bellard | return addr;
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352 | 4390df51 | bellard | } |
353 | 4390df51 | bellard | #else
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354 | 0cac1b66 | Blue Swirl | /* cputlb.c */
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355 | 9349b4f9 | Andreas Färber | tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr); |
356 | 4390df51 | bellard | #endif
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357 | 9df217a3 | bellard | |
358 | 9349b4f9 | Andreas Färber | typedef void (CPUDebugExcpHandler)(CPUArchState *env); |
359 | dde2367e | aliguori | |
360 | dde2367e | aliguori | CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler); |
361 | 1b530a6d | aurel32 | |
362 | 1b530a6d | aurel32 | /* vl.c */
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363 | 1b530a6d | aurel32 | extern int singlestep; |
364 | 1b530a6d | aurel32 | |
365 | 1a28cac3 | Marcelo Tosatti | /* cpu-exec.c */
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366 | 1a28cac3 | Marcelo Tosatti | extern volatile sig_atomic_t exit_request; |
367 | 1a28cac3 | Marcelo Tosatti | |
368 | 946fb27c | Paolo Bonzini | /* Deterministic execution requires that IO only be performed on the last
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369 | 946fb27c | Paolo Bonzini | instruction of a TB so that interrupts take effect immediately. */
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370 | 9349b4f9 | Andreas Färber | static inline int can_do_io(CPUArchState *env) |
371 | 946fb27c | Paolo Bonzini | { |
372 | 946fb27c | Paolo Bonzini | if (!use_icount) {
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373 | 946fb27c | Paolo Bonzini | return 1; |
374 | 946fb27c | Paolo Bonzini | } |
375 | 946fb27c | Paolo Bonzini | /* If not executing code then assume we are ok. */
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376 | 946fb27c | Paolo Bonzini | if (!env->current_tb) {
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377 | 946fb27c | Paolo Bonzini | return 1; |
378 | 946fb27c | Paolo Bonzini | } |
379 | 946fb27c | Paolo Bonzini | return env->can_do_io != 0; |
380 | 946fb27c | Paolo Bonzini | } |
381 | 946fb27c | Paolo Bonzini | |
382 | 875cdcf6 | aliguori | #endif |