root / hw / omap_dma.c @ e94bbefe
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1 | b4e3104b | balrog | /*
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2 | b4e3104b | balrog | * TI OMAP DMA gigacell.
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3 | b4e3104b | balrog | *
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4 | b4e3104b | balrog | * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
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5 | b4e3104b | balrog | * Copyright (C) 2007-2008 Lauro Ramos Venancio <lauro.venancio@indt.org.br>
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6 | b4e3104b | balrog | *
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7 | b4e3104b | balrog | * This program is free software; you can redistribute it and/or
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8 | b4e3104b | balrog | * modify it under the terms of the GNU General Public License as
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9 | b4e3104b | balrog | * published by the Free Software Foundation; either version 2 of
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10 | b4e3104b | balrog | * the License, or (at your option) any later version.
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11 | b4e3104b | balrog | *
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12 | b4e3104b | balrog | * This program is distributed in the hope that it will be useful,
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13 | b4e3104b | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | b4e3104b | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 | b4e3104b | balrog | * GNU General Public License for more details.
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16 | b4e3104b | balrog | *
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17 | b4e3104b | balrog | * You should have received a copy of the GNU General Public License
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18 | b4e3104b | balrog | * along with this program; if not, write to the Free Software
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19 | b4e3104b | balrog | * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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20 | b4e3104b | balrog | * MA 02111-1307 USA
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21 | b4e3104b | balrog | */
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22 | b4e3104b | balrog | #include "qemu-common.h" |
23 | b4e3104b | balrog | #include "qemu-timer.h" |
24 | b4e3104b | balrog | #include "omap.h" |
25 | b4e3104b | balrog | #include "irq.h" |
26 | b4e3104b | balrog | |
27 | b4e3104b | balrog | struct omap_dma_channel_s {
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28 | b4e3104b | balrog | /* transfer data */
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29 | b4e3104b | balrog | int burst[2]; |
30 | b4e3104b | balrog | int pack[2]; |
31 | b4e3104b | balrog | enum omap_dma_port port[2]; |
32 | b4e3104b | balrog | target_phys_addr_t addr[2];
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33 | b4e3104b | balrog | omap_dma_addressing_t mode[2];
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34 | b4e3104b | balrog | uint16_t elements; |
35 | b4e3104b | balrog | uint16_t frames; |
36 | b4e3104b | balrog | int16_t frame_index[2];
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37 | b4e3104b | balrog | int16_t element_index[2];
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38 | b4e3104b | balrog | int data_type;
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39 | b4e3104b | balrog | |
40 | b4e3104b | balrog | /* transfer type */
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41 | b4e3104b | balrog | int transparent_copy;
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42 | b4e3104b | balrog | int constant_fill;
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43 | b4e3104b | balrog | uint32_t color; |
44 | b4e3104b | balrog | |
45 | b4e3104b | balrog | /* auto init and linked channel data */
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46 | b4e3104b | balrog | int end_prog;
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47 | b4e3104b | balrog | int repeat;
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48 | b4e3104b | balrog | int auto_init;
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49 | b4e3104b | balrog | int link_enabled;
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50 | b4e3104b | balrog | int link_next_ch;
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51 | b4e3104b | balrog | |
52 | b4e3104b | balrog | /* interruption data */
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53 | b4e3104b | balrog | int interrupts;
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54 | b4e3104b | balrog | int status;
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55 | b4e3104b | balrog | |
56 | b4e3104b | balrog | /* state data */
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57 | b4e3104b | balrog | int active;
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58 | b4e3104b | balrog | int enable;
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59 | b4e3104b | balrog | int sync;
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60 | b4e3104b | balrog | int pending_request;
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61 | b4e3104b | balrog | int waiting_end_prog;
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62 | b4e3104b | balrog | uint16_t cpc; |
63 | b4e3104b | balrog | |
64 | b4e3104b | balrog | /* sync type */
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65 | b4e3104b | balrog | int fs;
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66 | b4e3104b | balrog | int bs;
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67 | b4e3104b | balrog | |
68 | b4e3104b | balrog | /* compatibility */
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69 | b4e3104b | balrog | int omap_3_1_compatible_disable;
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70 | b4e3104b | balrog | |
71 | b4e3104b | balrog | qemu_irq irq; |
72 | b4e3104b | balrog | struct omap_dma_channel_s *sibling;
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73 | b4e3104b | balrog | |
74 | b4e3104b | balrog | struct omap_dma_reg_set_s {
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75 | b4e3104b | balrog | target_phys_addr_t src, dest; |
76 | b4e3104b | balrog | int frame;
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77 | b4e3104b | balrog | int element;
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78 | b4e3104b | balrog | int frame_delta[2]; |
79 | b4e3104b | balrog | int elem_delta[2]; |
80 | b4e3104b | balrog | int frames;
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81 | b4e3104b | balrog | int elements;
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82 | b4e3104b | balrog | } active_set; |
83 | b4e3104b | balrog | |
84 | b4e3104b | balrog | /* unused parameters */
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85 | b4e3104b | balrog | int priority;
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86 | b4e3104b | balrog | int interleave_disabled;
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87 | b4e3104b | balrog | int type;
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88 | b4e3104b | balrog | }; |
89 | b4e3104b | balrog | |
90 | b4e3104b | balrog | struct omap_dma_s {
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91 | b4e3104b | balrog | QEMUTimer *tm; |
92 | b4e3104b | balrog | struct omap_mpu_state_s *mpu;
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93 | b4e3104b | balrog | target_phys_addr_t base; |
94 | b4e3104b | balrog | omap_clk clk; |
95 | b4e3104b | balrog | int64_t delay; |
96 | b4e3104b | balrog | uint32_t drq; |
97 | b4e3104b | balrog | enum omap_dma_model model;
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98 | b4e3104b | balrog | int omap_3_1_mapping_disabled;
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99 | b4e3104b | balrog | |
100 | b4e3104b | balrog | uint16_t gcr; |
101 | b4e3104b | balrog | int run_count;
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102 | b4e3104b | balrog | |
103 | b4e3104b | balrog | int chans;
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104 | b4e3104b | balrog | struct omap_dma_channel_s ch[16]; |
105 | b4e3104b | balrog | struct omap_dma_lcd_channel_s lcd_ch;
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106 | b4e3104b | balrog | }; |
107 | b4e3104b | balrog | |
108 | b4e3104b | balrog | /* Interrupts */
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109 | b4e3104b | balrog | #define TIMEOUT_INTR (1 << 0) |
110 | b4e3104b | balrog | #define EVENT_DROP_INTR (1 << 1) |
111 | b4e3104b | balrog | #define HALF_FRAME_INTR (1 << 2) |
112 | b4e3104b | balrog | #define END_FRAME_INTR (1 << 3) |
113 | b4e3104b | balrog | #define LAST_FRAME_INTR (1 << 4) |
114 | b4e3104b | balrog | #define END_BLOCK_INTR (1 << 5) |
115 | b4e3104b | balrog | #define SYNC (1 << 6) |
116 | b4e3104b | balrog | |
117 | b4e3104b | balrog | static void omap_dma_interrupts_update(struct omap_dma_s *s) |
118 | b4e3104b | balrog | { |
119 | b4e3104b | balrog | struct omap_dma_channel_s *ch = s->ch;
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120 | b4e3104b | balrog | int i;
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121 | b4e3104b | balrog | |
122 | b4e3104b | balrog | if (s->omap_3_1_mapping_disabled) {
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123 | b4e3104b | balrog | for (i = 0; i < s->chans; i ++, ch ++) |
124 | b4e3104b | balrog | if (ch->status)
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125 | b4e3104b | balrog | qemu_irq_raise(ch->irq); |
126 | b4e3104b | balrog | } else {
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127 | b4e3104b | balrog | /* First three interrupts are shared between two channels each. */
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128 | b4e3104b | balrog | for (i = 0; i < 6; i ++, ch ++) { |
129 | b4e3104b | balrog | if (ch->status || (ch->sibling && ch->sibling->status))
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130 | b4e3104b | balrog | qemu_irq_raise(ch->irq); |
131 | b4e3104b | balrog | } |
132 | b4e3104b | balrog | } |
133 | b4e3104b | balrog | } |
134 | b4e3104b | balrog | |
135 | b4e3104b | balrog | static void omap_dma_channel_load(struct omap_dma_s *s, |
136 | b4e3104b | balrog | struct omap_dma_channel_s *ch)
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137 | b4e3104b | balrog | { |
138 | b4e3104b | balrog | struct omap_dma_reg_set_s *a = &ch->active_set;
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139 | b4e3104b | balrog | int i;
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140 | b4e3104b | balrog | int omap_3_1 = !ch->omap_3_1_compatible_disable;
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141 | b4e3104b | balrog | |
142 | b4e3104b | balrog | /*
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143 | b4e3104b | balrog | * TODO: verify address ranges and alignment
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144 | b4e3104b | balrog | * TODO: port endianness
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145 | b4e3104b | balrog | */
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146 | b4e3104b | balrog | |
147 | b4e3104b | balrog | a->src = ch->addr[0];
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148 | b4e3104b | balrog | a->dest = ch->addr[1];
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149 | b4e3104b | balrog | a->frames = ch->frames; |
150 | b4e3104b | balrog | a->elements = ch->elements; |
151 | b4e3104b | balrog | a->frame = 0;
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152 | b4e3104b | balrog | a->element = 0;
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153 | b4e3104b | balrog | |
154 | b4e3104b | balrog | if (unlikely(!ch->elements || !ch->frames)) {
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155 | b4e3104b | balrog | printf("%s: bad DMA request\n", __FUNCTION__);
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156 | b4e3104b | balrog | return;
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157 | b4e3104b | balrog | } |
158 | b4e3104b | balrog | |
159 | b4e3104b | balrog | for (i = 0; i < 2; i ++) |
160 | b4e3104b | balrog | switch (ch->mode[i]) {
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161 | b4e3104b | balrog | case constant:
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162 | b4e3104b | balrog | a->elem_delta[i] = 0;
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163 | b4e3104b | balrog | a->frame_delta[i] = 0;
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164 | b4e3104b | balrog | break;
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165 | b4e3104b | balrog | case post_incremented:
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166 | b4e3104b | balrog | a->elem_delta[i] = ch->data_type; |
167 | b4e3104b | balrog | a->frame_delta[i] = 0;
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168 | b4e3104b | balrog | break;
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169 | b4e3104b | balrog | case single_index:
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170 | b4e3104b | balrog | a->elem_delta[i] = ch->data_type + |
171 | b4e3104b | balrog | ch->element_index[omap_3_1 ? 0 : i] - 1; |
172 | b4e3104b | balrog | a->frame_delta[i] = 0;
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173 | b4e3104b | balrog | break;
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174 | b4e3104b | balrog | case double_index:
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175 | b4e3104b | balrog | a->elem_delta[i] = ch->data_type + |
176 | b4e3104b | balrog | ch->element_index[omap_3_1 ? 0 : i] - 1; |
177 | b4e3104b | balrog | a->frame_delta[i] = ch->frame_index[omap_3_1 ? 0 : i] -
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178 | b4e3104b | balrog | ch->element_index[omap_3_1 ? 0 : i];
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179 | b4e3104b | balrog | break;
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180 | b4e3104b | balrog | default:
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181 | b4e3104b | balrog | break;
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182 | b4e3104b | balrog | } |
183 | b4e3104b | balrog | } |
184 | b4e3104b | balrog | |
185 | b4e3104b | balrog | static void omap_dma_activate_channel(struct omap_dma_s *s, |
186 | b4e3104b | balrog | struct omap_dma_channel_s *ch)
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187 | b4e3104b | balrog | { |
188 | b4e3104b | balrog | if (!ch->active) {
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189 | b4e3104b | balrog | ch->active = 1;
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190 | b4e3104b | balrog | if (ch->sync)
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191 | b4e3104b | balrog | ch->status |= SYNC; |
192 | b4e3104b | balrog | s->run_count ++; |
193 | b4e3104b | balrog | } |
194 | b4e3104b | balrog | |
195 | b4e3104b | balrog | if (s->delay && !qemu_timer_pending(s->tm))
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196 | b4e3104b | balrog | qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay); |
197 | b4e3104b | balrog | } |
198 | b4e3104b | balrog | |
199 | b4e3104b | balrog | static void omap_dma_deactivate_channel(struct omap_dma_s *s, |
200 | b4e3104b | balrog | struct omap_dma_channel_s *ch)
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201 | b4e3104b | balrog | { |
202 | b4e3104b | balrog | /* Update cpc */
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203 | b4e3104b | balrog | ch->cpc = ch->active_set.dest & 0xffff;
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204 | b4e3104b | balrog | |
205 | b4e3104b | balrog | if (ch->pending_request && !ch->waiting_end_prog) {
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206 | b4e3104b | balrog | /* Don't deactivate the channel */
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207 | b4e3104b | balrog | ch->pending_request = 0;
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208 | b4e3104b | balrog | if (ch->enable)
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209 | b4e3104b | balrog | return;
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210 | b4e3104b | balrog | } |
211 | b4e3104b | balrog | |
212 | b4e3104b | balrog | /* Don't deactive the channel if it is synchronized and the DMA request is
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213 | b4e3104b | balrog | active */
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214 | b4e3104b | balrog | if (ch->sync && (s->drq & (1 << ch->sync)) && ch->enable) |
215 | b4e3104b | balrog | return;
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216 | b4e3104b | balrog | |
217 | b4e3104b | balrog | if (ch->active) {
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218 | b4e3104b | balrog | ch->active = 0;
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219 | b4e3104b | balrog | ch->status &= ~SYNC; |
220 | b4e3104b | balrog | s->run_count --; |
221 | b4e3104b | balrog | } |
222 | b4e3104b | balrog | |
223 | b4e3104b | balrog | if (!s->run_count)
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224 | b4e3104b | balrog | qemu_del_timer(s->tm); |
225 | b4e3104b | balrog | } |
226 | b4e3104b | balrog | |
227 | b4e3104b | balrog | static void omap_dma_enable_channel(struct omap_dma_s *s, |
228 | b4e3104b | balrog | struct omap_dma_channel_s *ch)
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229 | b4e3104b | balrog | { |
230 | b4e3104b | balrog | if (!ch->enable) {
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231 | b4e3104b | balrog | ch->enable = 1;
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232 | b4e3104b | balrog | ch->waiting_end_prog = 0;
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233 | b4e3104b | balrog | omap_dma_channel_load(s, ch); |
234 | b4e3104b | balrog | if ((!ch->sync) || (s->drq & (1 << ch->sync))) |
235 | b4e3104b | balrog | omap_dma_activate_channel(s, ch); |
236 | b4e3104b | balrog | } |
237 | b4e3104b | balrog | } |
238 | b4e3104b | balrog | |
239 | b4e3104b | balrog | static void omap_dma_disable_channel(struct omap_dma_s *s, |
240 | b4e3104b | balrog | struct omap_dma_channel_s *ch)
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241 | b4e3104b | balrog | { |
242 | b4e3104b | balrog | if (ch->enable) {
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243 | b4e3104b | balrog | ch->enable = 0;
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244 | b4e3104b | balrog | /* Discard any pending request */
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245 | b4e3104b | balrog | ch->pending_request = 0;
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246 | b4e3104b | balrog | omap_dma_deactivate_channel(s, ch); |
247 | b4e3104b | balrog | } |
248 | b4e3104b | balrog | } |
249 | b4e3104b | balrog | |
250 | b4e3104b | balrog | static void omap_dma_channel_end_prog(struct omap_dma_s *s, |
251 | b4e3104b | balrog | struct omap_dma_channel_s *ch)
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252 | b4e3104b | balrog | { |
253 | b4e3104b | balrog | if (ch->waiting_end_prog) {
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254 | b4e3104b | balrog | ch->waiting_end_prog = 0;
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255 | b4e3104b | balrog | if (!ch->sync || ch->pending_request) {
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256 | b4e3104b | balrog | ch->pending_request = 0;
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257 | b4e3104b | balrog | omap_dma_activate_channel(s, ch); |
258 | b4e3104b | balrog | } |
259 | b4e3104b | balrog | } |
260 | b4e3104b | balrog | } |
261 | b4e3104b | balrog | |
262 | b4e3104b | balrog | static void omap_dma_enable_3_1_mapping(struct omap_dma_s *s) |
263 | b4e3104b | balrog | { |
264 | b4e3104b | balrog | s->omap_3_1_mapping_disabled = 0;
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265 | b4e3104b | balrog | s->chans = 9;
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266 | b4e3104b | balrog | } |
267 | b4e3104b | balrog | |
268 | b4e3104b | balrog | static void omap_dma_disable_3_1_mapping(struct omap_dma_s *s) |
269 | b4e3104b | balrog | { |
270 | b4e3104b | balrog | s->omap_3_1_mapping_disabled = 1;
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271 | b4e3104b | balrog | s->chans = 16;
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272 | b4e3104b | balrog | } |
273 | b4e3104b | balrog | |
274 | b4e3104b | balrog | static void omap_dma_process_request(struct omap_dma_s *s, int request) |
275 | b4e3104b | balrog | { |
276 | b4e3104b | balrog | int channel;
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277 | b4e3104b | balrog | int drop_event = 0; |
278 | b4e3104b | balrog | struct omap_dma_channel_s *ch = s->ch;
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279 | b4e3104b | balrog | |
280 | b4e3104b | balrog | for (channel = 0; channel < s->chans; channel ++, ch ++) { |
281 | b4e3104b | balrog | if (ch->enable && ch->sync == request) {
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282 | b4e3104b | balrog | if (!ch->active)
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283 | b4e3104b | balrog | omap_dma_activate_channel(s, ch); |
284 | b4e3104b | balrog | else if (!ch->pending_request) |
285 | b4e3104b | balrog | ch->pending_request = 1;
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286 | b4e3104b | balrog | else {
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287 | b4e3104b | balrog | /* Request collision */
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288 | b4e3104b | balrog | /* Second request received while processing other request */
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289 | b4e3104b | balrog | ch->status |= EVENT_DROP_INTR; |
290 | b4e3104b | balrog | drop_event = 1;
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291 | b4e3104b | balrog | } |
292 | b4e3104b | balrog | } |
293 | b4e3104b | balrog | } |
294 | b4e3104b | balrog | |
295 | b4e3104b | balrog | if (drop_event)
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296 | b4e3104b | balrog | omap_dma_interrupts_update(s); |
297 | b4e3104b | balrog | } |
298 | b4e3104b | balrog | |
299 | b4e3104b | balrog | static void omap_dma_channel_run(struct omap_dma_s *s) |
300 | b4e3104b | balrog | { |
301 | b4e3104b | balrog | int n = s->chans;
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302 | b4e3104b | balrog | uint16_t status; |
303 | b4e3104b | balrog | uint8_t value[4];
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304 | b4e3104b | balrog | struct omap_dma_port_if_s *src_p, *dest_p;
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305 | b4e3104b | balrog | struct omap_dma_reg_set_s *a;
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306 | b4e3104b | balrog | struct omap_dma_channel_s *ch;
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307 | b4e3104b | balrog | |
308 | b4e3104b | balrog | for (ch = s->ch; n; n --, ch ++) {
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309 | b4e3104b | balrog | if (!ch->active)
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310 | b4e3104b | balrog | continue;
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311 | b4e3104b | balrog | |
312 | b4e3104b | balrog | a = &ch->active_set; |
313 | b4e3104b | balrog | |
314 | b4e3104b | balrog | src_p = &s->mpu->port[ch->port[0]];
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315 | b4e3104b | balrog | dest_p = &s->mpu->port[ch->port[1]];
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316 | b4e3104b | balrog | if ((!ch->constant_fill && !src_p->addr_valid(s->mpu, a->src)) ||
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317 | b4e3104b | balrog | (!dest_p->addr_valid(s->mpu, a->dest))) { |
318 | b4e3104b | balrog | #if 0
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319 | b4e3104b | balrog | /* Bus time-out */
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320 | b4e3104b | balrog | if (ch->interrupts & TIMEOUT_INTR)
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321 | b4e3104b | balrog | ch->status |= TIMEOUT_INTR;
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322 | b4e3104b | balrog | omap_dma_deactivate_channel(s, ch);
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323 | b4e3104b | balrog | continue;
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324 | b4e3104b | balrog | #endif
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325 | b4e3104b | balrog | printf("%s: Bus time-out in DMA%i operation\n",
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326 | b4e3104b | balrog | __FUNCTION__, s->chans - n); |
327 | b4e3104b | balrog | } |
328 | b4e3104b | balrog | |
329 | b4e3104b | balrog | status = ch->status; |
330 | b4e3104b | balrog | while (status == ch->status && ch->active) {
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331 | b4e3104b | balrog | /* Transfer a single element */
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332 | b4e3104b | balrog | /* FIXME: check the endianness */
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333 | b4e3104b | balrog | if (!ch->constant_fill)
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334 | b4e3104b | balrog | cpu_physical_memory_read(a->src, value, ch->data_type); |
335 | b4e3104b | balrog | else
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336 | b4e3104b | balrog | *(uint32_t *) value = ch->color; |
337 | b4e3104b | balrog | |
338 | b4e3104b | balrog | if (!ch->transparent_copy ||
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339 | b4e3104b | balrog | *(uint32_t *) value != ch->color) |
340 | b4e3104b | balrog | cpu_physical_memory_write(a->dest, value, ch->data_type); |
341 | b4e3104b | balrog | |
342 | b4e3104b | balrog | a->src += a->elem_delta[0];
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343 | b4e3104b | balrog | a->dest += a->elem_delta[1];
|
344 | b4e3104b | balrog | a->element ++; |
345 | b4e3104b | balrog | |
346 | b4e3104b | balrog | /* If the channel is element synchronized, deactivate it */
|
347 | b4e3104b | balrog | if (ch->sync && !ch->fs && !ch->bs)
|
348 | b4e3104b | balrog | omap_dma_deactivate_channel(s, ch); |
349 | b4e3104b | balrog | |
350 | b4e3104b | balrog | /* If it is the last frame, set the LAST_FRAME interrupt */
|
351 | b4e3104b | balrog | if (a->element == 1 && a->frame == a->frames - 1) |
352 | b4e3104b | balrog | if (ch->interrupts & LAST_FRAME_INTR)
|
353 | b4e3104b | balrog | ch->status |= LAST_FRAME_INTR; |
354 | b4e3104b | balrog | |
355 | b4e3104b | balrog | /* If the half of the frame was reached, set the HALF_FRAME
|
356 | b4e3104b | balrog | interrupt */
|
357 | b4e3104b | balrog | if (a->element == (a->elements >> 1)) |
358 | b4e3104b | balrog | if (ch->interrupts & HALF_FRAME_INTR)
|
359 | b4e3104b | balrog | ch->status |= HALF_FRAME_INTR; |
360 | b4e3104b | balrog | |
361 | b4e3104b | balrog | if (a->element == a->elements) {
|
362 | b4e3104b | balrog | /* End of Frame */
|
363 | b4e3104b | balrog | a->element = 0;
|
364 | b4e3104b | balrog | a->src += a->frame_delta[0];
|
365 | b4e3104b | balrog | a->dest += a->frame_delta[1];
|
366 | b4e3104b | balrog | a->frame ++; |
367 | b4e3104b | balrog | |
368 | b4e3104b | balrog | /* If the channel is frame synchronized, deactivate it */
|
369 | b4e3104b | balrog | if (ch->sync && ch->fs)
|
370 | b4e3104b | balrog | omap_dma_deactivate_channel(s, ch); |
371 | b4e3104b | balrog | |
372 | b4e3104b | balrog | /* If the channel is async, update cpc */
|
373 | b4e3104b | balrog | if (!ch->sync)
|
374 | b4e3104b | balrog | ch->cpc = a->dest & 0xffff;
|
375 | b4e3104b | balrog | |
376 | b4e3104b | balrog | /* Set the END_FRAME interrupt */
|
377 | b4e3104b | balrog | if (ch->interrupts & END_FRAME_INTR)
|
378 | b4e3104b | balrog | ch->status |= END_FRAME_INTR; |
379 | b4e3104b | balrog | |
380 | b4e3104b | balrog | if (a->frame == a->frames) {
|
381 | b4e3104b | balrog | /* End of Block */
|
382 | b4e3104b | balrog | /* Disable the channel */
|
383 | b4e3104b | balrog | |
384 | b4e3104b | balrog | if (ch->omap_3_1_compatible_disable) {
|
385 | b4e3104b | balrog | omap_dma_disable_channel(s, ch); |
386 | b4e3104b | balrog | if (ch->link_enabled)
|
387 | b4e3104b | balrog | omap_dma_enable_channel(s, |
388 | b4e3104b | balrog | &s->ch[ch->link_next_ch]); |
389 | b4e3104b | balrog | } else {
|
390 | b4e3104b | balrog | if (!ch->auto_init)
|
391 | b4e3104b | balrog | omap_dma_disable_channel(s, ch); |
392 | b4e3104b | balrog | else if (ch->repeat || ch->end_prog) |
393 | b4e3104b | balrog | omap_dma_channel_load(s, ch); |
394 | b4e3104b | balrog | else {
|
395 | b4e3104b | balrog | ch->waiting_end_prog = 1;
|
396 | b4e3104b | balrog | omap_dma_deactivate_channel(s, ch); |
397 | b4e3104b | balrog | } |
398 | b4e3104b | balrog | } |
399 | b4e3104b | balrog | |
400 | b4e3104b | balrog | if (ch->interrupts & END_BLOCK_INTR)
|
401 | b4e3104b | balrog | ch->status |= END_BLOCK_INTR; |
402 | b4e3104b | balrog | } |
403 | b4e3104b | balrog | } |
404 | b4e3104b | balrog | } |
405 | b4e3104b | balrog | } |
406 | b4e3104b | balrog | |
407 | b4e3104b | balrog | omap_dma_interrupts_update(s); |
408 | b4e3104b | balrog | if (s->run_count && s->delay)
|
409 | b4e3104b | balrog | qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay); |
410 | b4e3104b | balrog | } |
411 | b4e3104b | balrog | |
412 | b4e3104b | balrog | void omap_dma_reset(struct omap_dma_s *s) |
413 | b4e3104b | balrog | { |
414 | b4e3104b | balrog | int i;
|
415 | b4e3104b | balrog | |
416 | b4e3104b | balrog | qemu_del_timer(s->tm); |
417 | b4e3104b | balrog | s->gcr = 0x0004;
|
418 | b4e3104b | balrog | s->drq = 0x00000000;
|
419 | b4e3104b | balrog | s->run_count = 0;
|
420 | b4e3104b | balrog | s->lcd_ch.src = emiff; |
421 | b4e3104b | balrog | s->lcd_ch.condition = 0;
|
422 | b4e3104b | balrog | s->lcd_ch.interrupts = 0;
|
423 | b4e3104b | balrog | s->lcd_ch.dual = 0;
|
424 | b4e3104b | balrog | omap_dma_enable_3_1_mapping(s); |
425 | b4e3104b | balrog | for (i = 0; i < s->chans; i ++) { |
426 | b4e3104b | balrog | memset(&s->ch[i].burst, 0, sizeof(s->ch[i].burst)); |
427 | b4e3104b | balrog | memset(&s->ch[i].port, 0, sizeof(s->ch[i].port)); |
428 | b4e3104b | balrog | memset(&s->ch[i].mode, 0, sizeof(s->ch[i].mode)); |
429 | b4e3104b | balrog | memset(&s->ch[i].elements, 0, sizeof(s->ch[i].elements)); |
430 | b4e3104b | balrog | memset(&s->ch[i].frames, 0, sizeof(s->ch[i].frames)); |
431 | b4e3104b | balrog | memset(&s->ch[i].frame_index, 0, sizeof(s->ch[i].frame_index)); |
432 | b4e3104b | balrog | memset(&s->ch[i].element_index, 0, sizeof(s->ch[i].element_index)); |
433 | b4e3104b | balrog | memset(&s->ch[i].data_type, 0, sizeof(s->ch[i].data_type)); |
434 | b4e3104b | balrog | memset(&s->ch[i].transparent_copy, 0,
|
435 | b4e3104b | balrog | sizeof(s->ch[i].transparent_copy));
|
436 | b4e3104b | balrog | memset(&s->ch[i].constant_fill, 0, sizeof(s->ch[i].constant_fill)); |
437 | b4e3104b | balrog | memset(&s->ch[i].color, 0, sizeof(s->ch[i].color)); |
438 | b4e3104b | balrog | memset(&s->ch[i].end_prog, 0, sizeof(s->ch[i].end_prog)); |
439 | b4e3104b | balrog | memset(&s->ch[i].repeat, 0, sizeof(s->ch[i].repeat)); |
440 | b4e3104b | balrog | memset(&s->ch[i].auto_init, 0, sizeof(s->ch[i].auto_init)); |
441 | b4e3104b | balrog | memset(&s->ch[i].link_enabled, 0, sizeof(s->ch[i].link_enabled)); |
442 | b4e3104b | balrog | memset(&s->ch[i].link_next_ch, 0, sizeof(s->ch[i].link_next_ch)); |
443 | b4e3104b | balrog | s->ch[i].interrupts = 0x0003;
|
444 | b4e3104b | balrog | memset(&s->ch[i].status, 0, sizeof(s->ch[i].status)); |
445 | b4e3104b | balrog | memset(&s->ch[i].active, 0, sizeof(s->ch[i].active)); |
446 | b4e3104b | balrog | memset(&s->ch[i].enable, 0, sizeof(s->ch[i].enable)); |
447 | b4e3104b | balrog | memset(&s->ch[i].sync, 0, sizeof(s->ch[i].sync)); |
448 | b4e3104b | balrog | memset(&s->ch[i].pending_request, 0, sizeof(s->ch[i].pending_request)); |
449 | b4e3104b | balrog | memset(&s->ch[i].waiting_end_prog, 0,
|
450 | b4e3104b | balrog | sizeof(s->ch[i].waiting_end_prog));
|
451 | b4e3104b | balrog | memset(&s->ch[i].cpc, 0, sizeof(s->ch[i].cpc)); |
452 | b4e3104b | balrog | memset(&s->ch[i].fs, 0, sizeof(s->ch[i].fs)); |
453 | b4e3104b | balrog | memset(&s->ch[i].bs, 0, sizeof(s->ch[i].bs)); |
454 | b4e3104b | balrog | memset(&s->ch[i].omap_3_1_compatible_disable, 0,
|
455 | b4e3104b | balrog | sizeof(s->ch[i].omap_3_1_compatible_disable));
|
456 | b4e3104b | balrog | memset(&s->ch[i].active_set, 0, sizeof(s->ch[i].active_set)); |
457 | b4e3104b | balrog | memset(&s->ch[i].priority, 0, sizeof(s->ch[i].priority)); |
458 | b4e3104b | balrog | memset(&s->ch[i].interleave_disabled, 0,
|
459 | b4e3104b | balrog | sizeof(s->ch[i].interleave_disabled));
|
460 | b4e3104b | balrog | memset(&s->ch[i].type, 0, sizeof(s->ch[i].type)); |
461 | b4e3104b | balrog | } |
462 | b4e3104b | balrog | } |
463 | b4e3104b | balrog | |
464 | b4e3104b | balrog | static int omap_dma_ch_reg_read(struct omap_dma_s *s, |
465 | b4e3104b | balrog | struct omap_dma_channel_s *ch, int reg, uint16_t *value) |
466 | b4e3104b | balrog | { |
467 | b4e3104b | balrog | switch (reg) {
|
468 | b4e3104b | balrog | case 0x00: /* SYS_DMA_CSDP_CH0 */ |
469 | b4e3104b | balrog | *value = (ch->burst[1] << 14) | |
470 | b4e3104b | balrog | (ch->pack[1] << 13) | |
471 | b4e3104b | balrog | (ch->port[1] << 9) | |
472 | b4e3104b | balrog | (ch->burst[0] << 7) | |
473 | b4e3104b | balrog | (ch->pack[0] << 6) | |
474 | b4e3104b | balrog | (ch->port[0] << 2) | |
475 | b4e3104b | balrog | (ch->data_type >> 1);
|
476 | b4e3104b | balrog | break;
|
477 | b4e3104b | balrog | |
478 | b4e3104b | balrog | case 0x02: /* SYS_DMA_CCR_CH0 */ |
479 | b4e3104b | balrog | if (s->model == omap_dma_3_1)
|
480 | b4e3104b | balrog | *value = 0 << 10; /* FIFO_FLUSH reads as 0 */ |
481 | b4e3104b | balrog | else
|
482 | b4e3104b | balrog | *value = ch->omap_3_1_compatible_disable << 10;
|
483 | b4e3104b | balrog | *value |= (ch->mode[1] << 14) | |
484 | b4e3104b | balrog | (ch->mode[0] << 12) | |
485 | b4e3104b | balrog | (ch->end_prog << 11) |
|
486 | b4e3104b | balrog | (ch->repeat << 9) |
|
487 | b4e3104b | balrog | (ch->auto_init << 8) |
|
488 | b4e3104b | balrog | (ch->enable << 7) |
|
489 | b4e3104b | balrog | (ch->priority << 6) |
|
490 | b4e3104b | balrog | (ch->fs << 5) | ch->sync;
|
491 | b4e3104b | balrog | break;
|
492 | b4e3104b | balrog | |
493 | b4e3104b | balrog | case 0x04: /* SYS_DMA_CICR_CH0 */ |
494 | b4e3104b | balrog | *value = ch->interrupts; |
495 | b4e3104b | balrog | break;
|
496 | b4e3104b | balrog | |
497 | b4e3104b | balrog | case 0x06: /* SYS_DMA_CSR_CH0 */ |
498 | b4e3104b | balrog | *value = ch->status; |
499 | b4e3104b | balrog | ch->status &= SYNC; |
500 | b4e3104b | balrog | if (!ch->omap_3_1_compatible_disable && ch->sibling) {
|
501 | b4e3104b | balrog | *value |= (ch->sibling->status & 0x3f) << 6; |
502 | b4e3104b | balrog | ch->sibling->status &= SYNC; |
503 | b4e3104b | balrog | } |
504 | b4e3104b | balrog | qemu_irq_lower(ch->irq); |
505 | b4e3104b | balrog | break;
|
506 | b4e3104b | balrog | |
507 | b4e3104b | balrog | case 0x08: /* SYS_DMA_CSSA_L_CH0 */ |
508 | b4e3104b | balrog | *value = ch->addr[0] & 0x0000ffff; |
509 | b4e3104b | balrog | break;
|
510 | b4e3104b | balrog | |
511 | b4e3104b | balrog | case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ |
512 | b4e3104b | balrog | *value = ch->addr[0] >> 16; |
513 | b4e3104b | balrog | break;
|
514 | b4e3104b | balrog | |
515 | b4e3104b | balrog | case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ |
516 | b4e3104b | balrog | *value = ch->addr[1] & 0x0000ffff; |
517 | b4e3104b | balrog | break;
|
518 | b4e3104b | balrog | |
519 | b4e3104b | balrog | case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ |
520 | b4e3104b | balrog | *value = ch->addr[1] >> 16; |
521 | b4e3104b | balrog | break;
|
522 | b4e3104b | balrog | |
523 | b4e3104b | balrog | case 0x10: /* SYS_DMA_CEN_CH0 */ |
524 | b4e3104b | balrog | *value = ch->elements; |
525 | b4e3104b | balrog | break;
|
526 | b4e3104b | balrog | |
527 | b4e3104b | balrog | case 0x12: /* SYS_DMA_CFN_CH0 */ |
528 | b4e3104b | balrog | *value = ch->frames; |
529 | b4e3104b | balrog | break;
|
530 | b4e3104b | balrog | |
531 | b4e3104b | balrog | case 0x14: /* SYS_DMA_CFI_CH0 */ |
532 | b4e3104b | balrog | *value = ch->frame_index[0];
|
533 | b4e3104b | balrog | break;
|
534 | b4e3104b | balrog | |
535 | b4e3104b | balrog | case 0x16: /* SYS_DMA_CEI_CH0 */ |
536 | b4e3104b | balrog | *value = ch->element_index[0];
|
537 | b4e3104b | balrog | break;
|
538 | b4e3104b | balrog | |
539 | b4e3104b | balrog | case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */ |
540 | b4e3104b | balrog | if (ch->omap_3_1_compatible_disable)
|
541 | b4e3104b | balrog | *value = ch->active_set.src & 0xffff; /* CSAC */ |
542 | b4e3104b | balrog | else
|
543 | b4e3104b | balrog | *value = ch->cpc; |
544 | b4e3104b | balrog | break;
|
545 | b4e3104b | balrog | |
546 | b4e3104b | balrog | case 0x1a: /* DMA_CDAC */ |
547 | b4e3104b | balrog | *value = ch->active_set.dest & 0xffff; /* CDAC */ |
548 | b4e3104b | balrog | break;
|
549 | b4e3104b | balrog | |
550 | b4e3104b | balrog | case 0x1c: /* DMA_CDEI */ |
551 | b4e3104b | balrog | *value = ch->element_index[1];
|
552 | b4e3104b | balrog | break;
|
553 | b4e3104b | balrog | |
554 | b4e3104b | balrog | case 0x1e: /* DMA_CDFI */ |
555 | b4e3104b | balrog | *value = ch->frame_index[1];
|
556 | b4e3104b | balrog | break;
|
557 | b4e3104b | balrog | |
558 | b4e3104b | balrog | case 0x20: /* DMA_COLOR_L */ |
559 | b4e3104b | balrog | *value = ch->color & 0xffff;
|
560 | b4e3104b | balrog | break;
|
561 | b4e3104b | balrog | |
562 | b4e3104b | balrog | case 0x22: /* DMA_COLOR_U */ |
563 | b4e3104b | balrog | *value = ch->color >> 16;
|
564 | b4e3104b | balrog | break;
|
565 | b4e3104b | balrog | |
566 | b4e3104b | balrog | case 0x24: /* DMA_CCR2 */ |
567 | b4e3104b | balrog | *value = (ch->bs << 2) |
|
568 | b4e3104b | balrog | (ch->transparent_copy << 1) |
|
569 | b4e3104b | balrog | ch->constant_fill; |
570 | b4e3104b | balrog | break;
|
571 | b4e3104b | balrog | |
572 | b4e3104b | balrog | case 0x28: /* DMA_CLNK_CTRL */ |
573 | b4e3104b | balrog | *value = (ch->link_enabled << 15) |
|
574 | b4e3104b | balrog | (ch->link_next_ch & 0xf);
|
575 | b4e3104b | balrog | break;
|
576 | b4e3104b | balrog | |
577 | b4e3104b | balrog | case 0x2a: /* DMA_LCH_CTRL */ |
578 | b4e3104b | balrog | *value = (ch->interleave_disabled << 15) |
|
579 | b4e3104b | balrog | ch->type; |
580 | b4e3104b | balrog | break;
|
581 | b4e3104b | balrog | |
582 | b4e3104b | balrog | default:
|
583 | b4e3104b | balrog | return 1; |
584 | b4e3104b | balrog | } |
585 | b4e3104b | balrog | return 0; |
586 | b4e3104b | balrog | } |
587 | b4e3104b | balrog | |
588 | b4e3104b | balrog | static int omap_dma_ch_reg_write(struct omap_dma_s *s, |
589 | b4e3104b | balrog | struct omap_dma_channel_s *ch, int reg, uint16_t value) |
590 | b4e3104b | balrog | { |
591 | b4e3104b | balrog | switch (reg) {
|
592 | b4e3104b | balrog | case 0x00: /* SYS_DMA_CSDP_CH0 */ |
593 | b4e3104b | balrog | ch->burst[1] = (value & 0xc000) >> 14; |
594 | b4e3104b | balrog | ch->pack[1] = (value & 0x2000) >> 13; |
595 | b4e3104b | balrog | ch->port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9); |
596 | b4e3104b | balrog | ch->burst[0] = (value & 0x0180) >> 7; |
597 | b4e3104b | balrog | ch->pack[0] = (value & 0x0040) >> 6; |
598 | b4e3104b | balrog | ch->port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2); |
599 | b4e3104b | balrog | ch->data_type = (1 << (value & 3)); |
600 | b4e3104b | balrog | if (ch->port[0] >= omap_dma_port_last) |
601 | b4e3104b | balrog | printf("%s: invalid DMA port %i\n", __FUNCTION__,
|
602 | b4e3104b | balrog | ch->port[0]);
|
603 | b4e3104b | balrog | if (ch->port[1] >= omap_dma_port_last) |
604 | b4e3104b | balrog | printf("%s: invalid DMA port %i\n", __FUNCTION__,
|
605 | b4e3104b | balrog | ch->port[1]);
|
606 | b4e3104b | balrog | if ((value & 3) == 3) |
607 | b4e3104b | balrog | printf("%s: bad data_type for DMA channel\n", __FUNCTION__);
|
608 | b4e3104b | balrog | break;
|
609 | b4e3104b | balrog | |
610 | b4e3104b | balrog | case 0x02: /* SYS_DMA_CCR_CH0 */ |
611 | b4e3104b | balrog | ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14); |
612 | b4e3104b | balrog | ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12); |
613 | b4e3104b | balrog | ch->end_prog = (value & 0x0800) >> 11; |
614 | b4e3104b | balrog | if (s->model > omap_dma_3_1)
|
615 | b4e3104b | balrog | ch->omap_3_1_compatible_disable = (value >> 10) & 0x1; |
616 | b4e3104b | balrog | ch->repeat = (value & 0x0200) >> 9; |
617 | b4e3104b | balrog | ch->auto_init = (value & 0x0100) >> 8; |
618 | b4e3104b | balrog | ch->priority = (value & 0x0040) >> 6; |
619 | b4e3104b | balrog | ch->fs = (value & 0x0020) >> 5; |
620 | b4e3104b | balrog | ch->sync = value & 0x001f;
|
621 | b4e3104b | balrog | |
622 | b4e3104b | balrog | if (value & 0x0080) |
623 | b4e3104b | balrog | omap_dma_enable_channel(s, ch); |
624 | b4e3104b | balrog | else
|
625 | b4e3104b | balrog | omap_dma_disable_channel(s, ch); |
626 | b4e3104b | balrog | |
627 | b4e3104b | balrog | if (ch->end_prog)
|
628 | b4e3104b | balrog | omap_dma_channel_end_prog(s, ch); |
629 | b4e3104b | balrog | |
630 | b4e3104b | balrog | break;
|
631 | b4e3104b | balrog | |
632 | b4e3104b | balrog | case 0x04: /* SYS_DMA_CICR_CH0 */ |
633 | b4e3104b | balrog | ch->interrupts = value; |
634 | b4e3104b | balrog | break;
|
635 | b4e3104b | balrog | |
636 | b4e3104b | balrog | case 0x06: /* SYS_DMA_CSR_CH0 */ |
637 | b4e3104b | balrog | OMAP_RO_REG((target_phys_addr_t) reg); |
638 | b4e3104b | balrog | break;
|
639 | b4e3104b | balrog | |
640 | b4e3104b | balrog | case 0x08: /* SYS_DMA_CSSA_L_CH0 */ |
641 | b4e3104b | balrog | ch->addr[0] &= 0xffff0000; |
642 | b4e3104b | balrog | ch->addr[0] |= value;
|
643 | b4e3104b | balrog | break;
|
644 | b4e3104b | balrog | |
645 | b4e3104b | balrog | case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ |
646 | b4e3104b | balrog | ch->addr[0] &= 0x0000ffff; |
647 | b4e3104b | balrog | ch->addr[0] |= (uint32_t) value << 16; |
648 | b4e3104b | balrog | break;
|
649 | b4e3104b | balrog | |
650 | b4e3104b | balrog | case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ |
651 | b4e3104b | balrog | ch->addr[1] &= 0xffff0000; |
652 | b4e3104b | balrog | ch->addr[1] |= value;
|
653 | b4e3104b | balrog | break;
|
654 | b4e3104b | balrog | |
655 | b4e3104b | balrog | case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ |
656 | b4e3104b | balrog | ch->addr[1] &= 0x0000ffff; |
657 | b4e3104b | balrog | ch->addr[1] |= (uint32_t) value << 16; |
658 | b4e3104b | balrog | break;
|
659 | b4e3104b | balrog | |
660 | b4e3104b | balrog | case 0x10: /* SYS_DMA_CEN_CH0 */ |
661 | b4e3104b | balrog | ch->elements = value; |
662 | b4e3104b | balrog | break;
|
663 | b4e3104b | balrog | |
664 | b4e3104b | balrog | case 0x12: /* SYS_DMA_CFN_CH0 */ |
665 | b4e3104b | balrog | ch->frames = value; |
666 | b4e3104b | balrog | break;
|
667 | b4e3104b | balrog | |
668 | b4e3104b | balrog | case 0x14: /* SYS_DMA_CFI_CH0 */ |
669 | b4e3104b | balrog | ch->frame_index[0] = (int16_t) value;
|
670 | b4e3104b | balrog | break;
|
671 | b4e3104b | balrog | |
672 | b4e3104b | balrog | case 0x16: /* SYS_DMA_CEI_CH0 */ |
673 | b4e3104b | balrog | ch->element_index[0] = (int16_t) value;
|
674 | b4e3104b | balrog | break;
|
675 | b4e3104b | balrog | |
676 | b4e3104b | balrog | case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */ |
677 | b4e3104b | balrog | OMAP_RO_REG((target_phys_addr_t) reg); |
678 | b4e3104b | balrog | break;
|
679 | b4e3104b | balrog | |
680 | b4e3104b | balrog | case 0x1c: /* DMA_CDEI */ |
681 | b4e3104b | balrog | ch->element_index[1] = (int16_t) value;
|
682 | b4e3104b | balrog | break;
|
683 | b4e3104b | balrog | |
684 | b4e3104b | balrog | case 0x1e: /* DMA_CDFI */ |
685 | b4e3104b | balrog | ch->frame_index[1] = (int16_t) value;
|
686 | b4e3104b | balrog | break;
|
687 | b4e3104b | balrog | |
688 | b4e3104b | balrog | case 0x20: /* DMA_COLOR_L */ |
689 | b4e3104b | balrog | ch->color &= 0xffff0000;
|
690 | b4e3104b | balrog | ch->color |= value; |
691 | b4e3104b | balrog | break;
|
692 | b4e3104b | balrog | |
693 | b4e3104b | balrog | case 0x22: /* DMA_COLOR_U */ |
694 | b4e3104b | balrog | ch->color &= 0xffff;
|
695 | b4e3104b | balrog | ch->color |= value << 16;
|
696 | b4e3104b | balrog | break;
|
697 | b4e3104b | balrog | |
698 | b4e3104b | balrog | case 0x24: /* DMA_CCR2 */ |
699 | b4e3104b | balrog | ch->bs = (value >> 2) & 0x1; |
700 | b4e3104b | balrog | ch->transparent_copy = (value >> 1) & 0x1; |
701 | b4e3104b | balrog | ch->constant_fill = value & 0x1;
|
702 | b4e3104b | balrog | break;
|
703 | b4e3104b | balrog | |
704 | b4e3104b | balrog | case 0x28: /* DMA_CLNK_CTRL */ |
705 | b4e3104b | balrog | ch->link_enabled = (value >> 15) & 0x1; |
706 | b4e3104b | balrog | if (value & (1 << 14)) { /* Stop_Lnk */ |
707 | b4e3104b | balrog | ch->link_enabled = 0;
|
708 | b4e3104b | balrog | omap_dma_disable_channel(s, ch); |
709 | b4e3104b | balrog | } |
710 | b4e3104b | balrog | ch->link_next_ch = value & 0x1f;
|
711 | b4e3104b | balrog | break;
|
712 | b4e3104b | balrog | |
713 | b4e3104b | balrog | case 0x2a: /* DMA_LCH_CTRL */ |
714 | b4e3104b | balrog | ch->interleave_disabled = (value >> 15) & 0x1; |
715 | b4e3104b | balrog | ch->type = value & 0xf;
|
716 | b4e3104b | balrog | break;
|
717 | b4e3104b | balrog | |
718 | b4e3104b | balrog | default:
|
719 | b4e3104b | balrog | return 1; |
720 | b4e3104b | balrog | } |
721 | b4e3104b | balrog | return 0; |
722 | b4e3104b | balrog | } |
723 | b4e3104b | balrog | |
724 | b4e3104b | balrog | static int omap_dma_3_2_lcd_write(struct omap_dma_lcd_channel_s *s, int offset, |
725 | b4e3104b | balrog | uint16_t value) |
726 | b4e3104b | balrog | { |
727 | b4e3104b | balrog | switch (offset) {
|
728 | b4e3104b | balrog | case 0xbc0: /* DMA_LCD_CSDP */ |
729 | b4e3104b | balrog | s->brust_f2 = (value >> 14) & 0x3; |
730 | b4e3104b | balrog | s->pack_f2 = (value >> 13) & 0x1; |
731 | b4e3104b | balrog | s->data_type_f2 = (1 << ((value >> 11) & 0x3)); |
732 | b4e3104b | balrog | s->brust_f1 = (value >> 7) & 0x3; |
733 | b4e3104b | balrog | s->pack_f1 = (value >> 6) & 0x1; |
734 | b4e3104b | balrog | s->data_type_f1 = (1 << ((value >> 0) & 0x3)); |
735 | b4e3104b | balrog | break;
|
736 | b4e3104b | balrog | |
737 | b4e3104b | balrog | case 0xbc2: /* DMA_LCD_CCR */ |
738 | b4e3104b | balrog | s->mode_f2 = (value >> 14) & 0x3; |
739 | b4e3104b | balrog | s->mode_f1 = (value >> 12) & 0x3; |
740 | b4e3104b | balrog | s->end_prog = (value >> 11) & 0x1; |
741 | b4e3104b | balrog | s->omap_3_1_compatible_disable = (value >> 10) & 0x1; |
742 | b4e3104b | balrog | s->repeat = (value >> 9) & 0x1; |
743 | b4e3104b | balrog | s->auto_init = (value >> 8) & 0x1; |
744 | b4e3104b | balrog | s->running = (value >> 7) & 0x1; |
745 | b4e3104b | balrog | s->priority = (value >> 6) & 0x1; |
746 | b4e3104b | balrog | s->bs = (value >> 4) & 0x1; |
747 | b4e3104b | balrog | break;
|
748 | b4e3104b | balrog | |
749 | b4e3104b | balrog | case 0xbc4: /* DMA_LCD_CTRL */ |
750 | b4e3104b | balrog | s->dst = (value >> 8) & 0x1; |
751 | b4e3104b | balrog | s->src = ((value >> 6) & 0x3) << 1; |
752 | b4e3104b | balrog | s->condition = 0;
|
753 | b4e3104b | balrog | /* Assume no bus errors and thus no BUS_ERROR irq bits. */
|
754 | b4e3104b | balrog | s->interrupts = (value >> 1) & 1; |
755 | b4e3104b | balrog | s->dual = value & 1;
|
756 | b4e3104b | balrog | break;
|
757 | b4e3104b | balrog | |
758 | b4e3104b | balrog | case 0xbc8: /* TOP_B1_L */ |
759 | b4e3104b | balrog | s->src_f1_top &= 0xffff0000;
|
760 | b4e3104b | balrog | s->src_f1_top |= 0x0000ffff & value;
|
761 | b4e3104b | balrog | break;
|
762 | b4e3104b | balrog | |
763 | b4e3104b | balrog | case 0xbca: /* TOP_B1_U */ |
764 | b4e3104b | balrog | s->src_f1_top &= 0x0000ffff;
|
765 | b4e3104b | balrog | s->src_f1_top |= value << 16;
|
766 | b4e3104b | balrog | break;
|
767 | b4e3104b | balrog | |
768 | b4e3104b | balrog | case 0xbcc: /* BOT_B1_L */ |
769 | b4e3104b | balrog | s->src_f1_bottom &= 0xffff0000;
|
770 | b4e3104b | balrog | s->src_f1_bottom |= 0x0000ffff & value;
|
771 | b4e3104b | balrog | break;
|
772 | b4e3104b | balrog | |
773 | b4e3104b | balrog | case 0xbce: /* BOT_B1_U */ |
774 | b4e3104b | balrog | s->src_f1_bottom &= 0x0000ffff;
|
775 | b4e3104b | balrog | s->src_f1_bottom |= (uint32_t) value << 16;
|
776 | b4e3104b | balrog | break;
|
777 | b4e3104b | balrog | |
778 | b4e3104b | balrog | case 0xbd0: /* TOP_B2_L */ |
779 | b4e3104b | balrog | s->src_f2_top &= 0xffff0000;
|
780 | b4e3104b | balrog | s->src_f2_top |= 0x0000ffff & value;
|
781 | b4e3104b | balrog | break;
|
782 | b4e3104b | balrog | |
783 | b4e3104b | balrog | case 0xbd2: /* TOP_B2_U */ |
784 | b4e3104b | balrog | s->src_f2_top &= 0x0000ffff;
|
785 | b4e3104b | balrog | s->src_f2_top |= (uint32_t) value << 16;
|
786 | b4e3104b | balrog | break;
|
787 | b4e3104b | balrog | |
788 | b4e3104b | balrog | case 0xbd4: /* BOT_B2_L */ |
789 | b4e3104b | balrog | s->src_f2_bottom &= 0xffff0000;
|
790 | b4e3104b | balrog | s->src_f2_bottom |= 0x0000ffff & value;
|
791 | b4e3104b | balrog | break;
|
792 | b4e3104b | balrog | |
793 | b4e3104b | balrog | case 0xbd6: /* BOT_B2_U */ |
794 | b4e3104b | balrog | s->src_f2_bottom &= 0x0000ffff;
|
795 | b4e3104b | balrog | s->src_f2_bottom |= (uint32_t) value << 16;
|
796 | b4e3104b | balrog | break;
|
797 | b4e3104b | balrog | |
798 | b4e3104b | balrog | case 0xbd8: /* DMA_LCD_SRC_EI_B1 */ |
799 | b4e3104b | balrog | s->element_index_f1 = value; |
800 | b4e3104b | balrog | break;
|
801 | b4e3104b | balrog | |
802 | b4e3104b | balrog | case 0xbda: /* DMA_LCD_SRC_FI_B1_L */ |
803 | b4e3104b | balrog | s->frame_index_f1 &= 0xffff0000;
|
804 | b4e3104b | balrog | s->frame_index_f1 |= 0x0000ffff & value;
|
805 | b4e3104b | balrog | break;
|
806 | b4e3104b | balrog | |
807 | b4e3104b | balrog | case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */ |
808 | b4e3104b | balrog | s->frame_index_f1 &= 0x0000ffff;
|
809 | b4e3104b | balrog | s->frame_index_f1 |= (uint32_t) value << 16;
|
810 | b4e3104b | balrog | break;
|
811 | b4e3104b | balrog | |
812 | b4e3104b | balrog | case 0xbdc: /* DMA_LCD_SRC_EI_B2 */ |
813 | b4e3104b | balrog | s->element_index_f2 = value; |
814 | b4e3104b | balrog | break;
|
815 | b4e3104b | balrog | |
816 | b4e3104b | balrog | case 0xbde: /* DMA_LCD_SRC_FI_B2_L */ |
817 | b4e3104b | balrog | s->frame_index_f2 &= 0xffff0000;
|
818 | b4e3104b | balrog | s->frame_index_f2 |= 0x0000ffff & value;
|
819 | b4e3104b | balrog | break;
|
820 | b4e3104b | balrog | |
821 | b4e3104b | balrog | case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */ |
822 | b4e3104b | balrog | s->frame_index_f2 &= 0x0000ffff;
|
823 | b4e3104b | balrog | s->frame_index_f2 |= (uint32_t) value << 16;
|
824 | b4e3104b | balrog | break;
|
825 | b4e3104b | balrog | |
826 | b4e3104b | balrog | case 0xbe0: /* DMA_LCD_SRC_EN_B1 */ |
827 | b4e3104b | balrog | s->elements_f1 = value; |
828 | b4e3104b | balrog | break;
|
829 | b4e3104b | balrog | |
830 | b4e3104b | balrog | case 0xbe4: /* DMA_LCD_SRC_FN_B1 */ |
831 | b4e3104b | balrog | s->frames_f1 = value; |
832 | b4e3104b | balrog | break;
|
833 | b4e3104b | balrog | |
834 | b4e3104b | balrog | case 0xbe2: /* DMA_LCD_SRC_EN_B2 */ |
835 | b4e3104b | balrog | s->elements_f2 = value; |
836 | b4e3104b | balrog | break;
|
837 | b4e3104b | balrog | |
838 | b4e3104b | balrog | case 0xbe6: /* DMA_LCD_SRC_FN_B2 */ |
839 | b4e3104b | balrog | s->frames_f2 = value; |
840 | b4e3104b | balrog | break;
|
841 | b4e3104b | balrog | |
842 | b4e3104b | balrog | case 0xbea: /* DMA_LCD_LCH_CTRL */ |
843 | b4e3104b | balrog | s->lch_type = value & 0xf;
|
844 | b4e3104b | balrog | break;
|
845 | b4e3104b | balrog | |
846 | b4e3104b | balrog | default:
|
847 | b4e3104b | balrog | return 1; |
848 | b4e3104b | balrog | } |
849 | b4e3104b | balrog | return 0; |
850 | b4e3104b | balrog | } |
851 | b4e3104b | balrog | |
852 | b4e3104b | balrog | static int omap_dma_3_2_lcd_read(struct omap_dma_lcd_channel_s *s, int offset, |
853 | b4e3104b | balrog | uint16_t *ret) |
854 | b4e3104b | balrog | { |
855 | b4e3104b | balrog | switch (offset) {
|
856 | b4e3104b | balrog | case 0xbc0: /* DMA_LCD_CSDP */ |
857 | b4e3104b | balrog | *ret = (s->brust_f2 << 14) |
|
858 | b4e3104b | balrog | (s->pack_f2 << 13) |
|
859 | b4e3104b | balrog | ((s->data_type_f2 >> 1) << 11) | |
860 | b4e3104b | balrog | (s->brust_f1 << 7) |
|
861 | b4e3104b | balrog | (s->pack_f1 << 6) |
|
862 | b4e3104b | balrog | ((s->data_type_f1 >> 1) << 0); |
863 | b4e3104b | balrog | break;
|
864 | b4e3104b | balrog | |
865 | b4e3104b | balrog | case 0xbc2: /* DMA_LCD_CCR */ |
866 | b4e3104b | balrog | *ret = (s->mode_f2 << 14) |
|
867 | b4e3104b | balrog | (s->mode_f1 << 12) |
|
868 | b4e3104b | balrog | (s->end_prog << 11) |
|
869 | b4e3104b | balrog | (s->omap_3_1_compatible_disable << 10) |
|
870 | b4e3104b | balrog | (s->repeat << 9) |
|
871 | b4e3104b | balrog | (s->auto_init << 8) |
|
872 | b4e3104b | balrog | (s->running << 7) |
|
873 | b4e3104b | balrog | (s->priority << 6) |
|
874 | b4e3104b | balrog | (s->bs << 4);
|
875 | b4e3104b | balrog | break;
|
876 | b4e3104b | balrog | |
877 | b4e3104b | balrog | case 0xbc4: /* DMA_LCD_CTRL */ |
878 | b4e3104b | balrog | qemu_irq_lower(s->irq); |
879 | b4e3104b | balrog | *ret = (s->dst << 8) |
|
880 | b4e3104b | balrog | ((s->src & 0x6) << 5) | |
881 | b4e3104b | balrog | (s->condition << 3) |
|
882 | b4e3104b | balrog | (s->interrupts << 1) |
|
883 | b4e3104b | balrog | s->dual; |
884 | b4e3104b | balrog | break;
|
885 | b4e3104b | balrog | |
886 | b4e3104b | balrog | case 0xbc8: /* TOP_B1_L */ |
887 | b4e3104b | balrog | *ret = s->src_f1_top & 0xffff;
|
888 | b4e3104b | balrog | break;
|
889 | b4e3104b | balrog | |
890 | b4e3104b | balrog | case 0xbca: /* TOP_B1_U */ |
891 | b4e3104b | balrog | *ret = s->src_f1_top >> 16;
|
892 | b4e3104b | balrog | break;
|
893 | b4e3104b | balrog | |
894 | b4e3104b | balrog | case 0xbcc: /* BOT_B1_L */ |
895 | b4e3104b | balrog | *ret = s->src_f1_bottom & 0xffff;
|
896 | b4e3104b | balrog | break;
|
897 | b4e3104b | balrog | |
898 | b4e3104b | balrog | case 0xbce: /* BOT_B1_U */ |
899 | b4e3104b | balrog | *ret = s->src_f1_bottom >> 16;
|
900 | b4e3104b | balrog | break;
|
901 | b4e3104b | balrog | |
902 | b4e3104b | balrog | case 0xbd0: /* TOP_B2_L */ |
903 | b4e3104b | balrog | *ret = s->src_f2_top & 0xffff;
|
904 | b4e3104b | balrog | break;
|
905 | b4e3104b | balrog | |
906 | b4e3104b | balrog | case 0xbd2: /* TOP_B2_U */ |
907 | b4e3104b | balrog | *ret = s->src_f2_top >> 16;
|
908 | b4e3104b | balrog | break;
|
909 | b4e3104b | balrog | |
910 | b4e3104b | balrog | case 0xbd4: /* BOT_B2_L */ |
911 | b4e3104b | balrog | *ret = s->src_f2_bottom & 0xffff;
|
912 | b4e3104b | balrog | break;
|
913 | b4e3104b | balrog | |
914 | b4e3104b | balrog | case 0xbd6: /* BOT_B2_U */ |
915 | b4e3104b | balrog | *ret = s->src_f2_bottom >> 16;
|
916 | b4e3104b | balrog | break;
|
917 | b4e3104b | balrog | |
918 | b4e3104b | balrog | case 0xbd8: /* DMA_LCD_SRC_EI_B1 */ |
919 | b4e3104b | balrog | *ret = s->element_index_f1; |
920 | b4e3104b | balrog | break;
|
921 | b4e3104b | balrog | |
922 | b4e3104b | balrog | case 0xbda: /* DMA_LCD_SRC_FI_B1_L */ |
923 | b4e3104b | balrog | *ret = s->frame_index_f1 & 0xffff;
|
924 | b4e3104b | balrog | break;
|
925 | b4e3104b | balrog | |
926 | b4e3104b | balrog | case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */ |
927 | b4e3104b | balrog | *ret = s->frame_index_f1 >> 16;
|
928 | b4e3104b | balrog | break;
|
929 | b4e3104b | balrog | |
930 | b4e3104b | balrog | case 0xbdc: /* DMA_LCD_SRC_EI_B2 */ |
931 | b4e3104b | balrog | *ret = s->element_index_f2; |
932 | b4e3104b | balrog | break;
|
933 | b4e3104b | balrog | |
934 | b4e3104b | balrog | case 0xbde: /* DMA_LCD_SRC_FI_B2_L */ |
935 | b4e3104b | balrog | *ret = s->frame_index_f2 & 0xffff;
|
936 | b4e3104b | balrog | break;
|
937 | b4e3104b | balrog | |
938 | b4e3104b | balrog | case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */ |
939 | b4e3104b | balrog | *ret = s->frame_index_f2 >> 16;
|
940 | b4e3104b | balrog | break;
|
941 | b4e3104b | balrog | |
942 | b4e3104b | balrog | case 0xbe0: /* DMA_LCD_SRC_EN_B1 */ |
943 | b4e3104b | balrog | *ret = s->elements_f1; |
944 | b4e3104b | balrog | break;
|
945 | b4e3104b | balrog | |
946 | b4e3104b | balrog | case 0xbe4: /* DMA_LCD_SRC_FN_B1 */ |
947 | b4e3104b | balrog | *ret = s->frames_f1; |
948 | b4e3104b | balrog | break;
|
949 | b4e3104b | balrog | |
950 | b4e3104b | balrog | case 0xbe2: /* DMA_LCD_SRC_EN_B2 */ |
951 | b4e3104b | balrog | *ret = s->elements_f2; |
952 | b4e3104b | balrog | break;
|
953 | b4e3104b | balrog | |
954 | b4e3104b | balrog | case 0xbe6: /* DMA_LCD_SRC_FN_B2 */ |
955 | b4e3104b | balrog | *ret = s->frames_f2; |
956 | b4e3104b | balrog | break;
|
957 | b4e3104b | balrog | |
958 | b4e3104b | balrog | case 0xbea: /* DMA_LCD_LCH_CTRL */ |
959 | b4e3104b | balrog | *ret = s->lch_type; |
960 | b4e3104b | balrog | break;
|
961 | b4e3104b | balrog | |
962 | b4e3104b | balrog | default:
|
963 | b4e3104b | balrog | return 1; |
964 | b4e3104b | balrog | } |
965 | b4e3104b | balrog | return 0; |
966 | b4e3104b | balrog | } |
967 | b4e3104b | balrog | |
968 | b4e3104b | balrog | static int omap_dma_3_1_lcd_write(struct omap_dma_lcd_channel_s *s, int offset, |
969 | b4e3104b | balrog | uint16_t value) |
970 | b4e3104b | balrog | { |
971 | b4e3104b | balrog | switch (offset) {
|
972 | b4e3104b | balrog | case 0x300: /* SYS_DMA_LCD_CTRL */ |
973 | b4e3104b | balrog | s->src = (value & 0x40) ? imif : emiff;
|
974 | b4e3104b | balrog | s->condition = 0;
|
975 | b4e3104b | balrog | /* Assume no bus errors and thus no BUS_ERROR irq bits. */
|
976 | b4e3104b | balrog | s->interrupts = (value >> 1) & 1; |
977 | b4e3104b | balrog | s->dual = value & 1;
|
978 | b4e3104b | balrog | break;
|
979 | b4e3104b | balrog | |
980 | b4e3104b | balrog | case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ |
981 | b4e3104b | balrog | s->src_f1_top &= 0xffff0000;
|
982 | b4e3104b | balrog | s->src_f1_top |= 0x0000ffff & value;
|
983 | b4e3104b | balrog | break;
|
984 | b4e3104b | balrog | |
985 | b4e3104b | balrog | case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ |
986 | b4e3104b | balrog | s->src_f1_top &= 0x0000ffff;
|
987 | b4e3104b | balrog | s->src_f1_top |= value << 16;
|
988 | b4e3104b | balrog | break;
|
989 | b4e3104b | balrog | |
990 | b4e3104b | balrog | case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ |
991 | b4e3104b | balrog | s->src_f1_bottom &= 0xffff0000;
|
992 | b4e3104b | balrog | s->src_f1_bottom |= 0x0000ffff & value;
|
993 | b4e3104b | balrog | break;
|
994 | b4e3104b | balrog | |
995 | b4e3104b | balrog | case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ |
996 | b4e3104b | balrog | s->src_f1_bottom &= 0x0000ffff;
|
997 | b4e3104b | balrog | s->src_f1_bottom |= value << 16;
|
998 | b4e3104b | balrog | break;
|
999 | b4e3104b | balrog | |
1000 | b4e3104b | balrog | case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ |
1001 | b4e3104b | balrog | s->src_f2_top &= 0xffff0000;
|
1002 | b4e3104b | balrog | s->src_f2_top |= 0x0000ffff & value;
|
1003 | b4e3104b | balrog | break;
|
1004 | b4e3104b | balrog | |
1005 | b4e3104b | balrog | case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ |
1006 | b4e3104b | balrog | s->src_f2_top &= 0x0000ffff;
|
1007 | b4e3104b | balrog | s->src_f2_top |= value << 16;
|
1008 | b4e3104b | balrog | break;
|
1009 | b4e3104b | balrog | |
1010 | b4e3104b | balrog | case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ |
1011 | b4e3104b | balrog | s->src_f2_bottom &= 0xffff0000;
|
1012 | b4e3104b | balrog | s->src_f2_bottom |= 0x0000ffff & value;
|
1013 | b4e3104b | balrog | break;
|
1014 | b4e3104b | balrog | |
1015 | b4e3104b | balrog | case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ |
1016 | b4e3104b | balrog | s->src_f2_bottom &= 0x0000ffff;
|
1017 | b4e3104b | balrog | s->src_f2_bottom |= value << 16;
|
1018 | b4e3104b | balrog | break;
|
1019 | b4e3104b | balrog | |
1020 | b4e3104b | balrog | default:
|
1021 | b4e3104b | balrog | return 1; |
1022 | b4e3104b | balrog | } |
1023 | b4e3104b | balrog | return 0; |
1024 | b4e3104b | balrog | } |
1025 | b4e3104b | balrog | |
1026 | b4e3104b | balrog | static int omap_dma_3_1_lcd_read(struct omap_dma_lcd_channel_s *s, int offset, |
1027 | b4e3104b | balrog | uint16_t *ret) |
1028 | b4e3104b | balrog | { |
1029 | b4e3104b | balrog | int i;
|
1030 | b4e3104b | balrog | |
1031 | b4e3104b | balrog | switch (offset) {
|
1032 | b4e3104b | balrog | case 0x300: /* SYS_DMA_LCD_CTRL */ |
1033 | b4e3104b | balrog | i = s->condition; |
1034 | b4e3104b | balrog | s->condition = 0;
|
1035 | b4e3104b | balrog | qemu_irq_lower(s->irq); |
1036 | b4e3104b | balrog | *ret = ((s->src == imif) << 6) | (i << 3) | |
1037 | b4e3104b | balrog | (s->interrupts << 1) | s->dual;
|
1038 | b4e3104b | balrog | break;
|
1039 | b4e3104b | balrog | |
1040 | b4e3104b | balrog | case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ |
1041 | b4e3104b | balrog | *ret = s->src_f1_top & 0xffff;
|
1042 | b4e3104b | balrog | break;
|
1043 | b4e3104b | balrog | |
1044 | b4e3104b | balrog | case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ |
1045 | b4e3104b | balrog | *ret = s->src_f1_top >> 16;
|
1046 | b4e3104b | balrog | break;
|
1047 | b4e3104b | balrog | |
1048 | b4e3104b | balrog | case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ |
1049 | b4e3104b | balrog | *ret = s->src_f1_bottom & 0xffff;
|
1050 | b4e3104b | balrog | break;
|
1051 | b4e3104b | balrog | |
1052 | b4e3104b | balrog | case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ |
1053 | b4e3104b | balrog | *ret = s->src_f1_bottom >> 16;
|
1054 | b4e3104b | balrog | break;
|
1055 | b4e3104b | balrog | |
1056 | b4e3104b | balrog | case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ |
1057 | b4e3104b | balrog | *ret = s->src_f2_top & 0xffff;
|
1058 | b4e3104b | balrog | break;
|
1059 | b4e3104b | balrog | |
1060 | b4e3104b | balrog | case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ |
1061 | b4e3104b | balrog | *ret = s->src_f2_top >> 16;
|
1062 | b4e3104b | balrog | break;
|
1063 | b4e3104b | balrog | |
1064 | b4e3104b | balrog | case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ |
1065 | b4e3104b | balrog | *ret = s->src_f2_bottom & 0xffff;
|
1066 | b4e3104b | balrog | break;
|
1067 | b4e3104b | balrog | |
1068 | b4e3104b | balrog | case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ |
1069 | b4e3104b | balrog | *ret = s->src_f2_bottom >> 16;
|
1070 | b4e3104b | balrog | break;
|
1071 | b4e3104b | balrog | |
1072 | b4e3104b | balrog | default:
|
1073 | b4e3104b | balrog | return 1; |
1074 | b4e3104b | balrog | } |
1075 | b4e3104b | balrog | return 0; |
1076 | b4e3104b | balrog | } |
1077 | b4e3104b | balrog | |
1078 | b4e3104b | balrog | static int omap_dma_sys_write(struct omap_dma_s *s, int offset, uint16_t value) |
1079 | b4e3104b | balrog | { |
1080 | b4e3104b | balrog | switch (offset) {
|
1081 | b4e3104b | balrog | case 0x400: /* SYS_DMA_GCR */ |
1082 | b4e3104b | balrog | s->gcr = value; |
1083 | b4e3104b | balrog | break;
|
1084 | b4e3104b | balrog | |
1085 | b4e3104b | balrog | case 0x404: /* DMA_GSCR */ |
1086 | b4e3104b | balrog | if (value & 0x8) |
1087 | b4e3104b | balrog | omap_dma_disable_3_1_mapping(s); |
1088 | b4e3104b | balrog | else
|
1089 | b4e3104b | balrog | omap_dma_enable_3_1_mapping(s); |
1090 | b4e3104b | balrog | break;
|
1091 | b4e3104b | balrog | |
1092 | b4e3104b | balrog | case 0x408: /* DMA_GRST */ |
1093 | b4e3104b | balrog | if (value & 0x1) |
1094 | b4e3104b | balrog | omap_dma_reset(s); |
1095 | b4e3104b | balrog | break;
|
1096 | b4e3104b | balrog | |
1097 | b4e3104b | balrog | default:
|
1098 | b4e3104b | balrog | return 1; |
1099 | b4e3104b | balrog | } |
1100 | b4e3104b | balrog | return 0; |
1101 | b4e3104b | balrog | } |
1102 | b4e3104b | balrog | |
1103 | b4e3104b | balrog | static int omap_dma_sys_read(struct omap_dma_s *s, int offset, |
1104 | b4e3104b | balrog | uint16_t *ret) |
1105 | b4e3104b | balrog | { |
1106 | b4e3104b | balrog | switch (offset) {
|
1107 | b4e3104b | balrog | case 0x400: /* SYS_DMA_GCR */ |
1108 | b4e3104b | balrog | *ret = s->gcr; |
1109 | b4e3104b | balrog | break;
|
1110 | b4e3104b | balrog | |
1111 | b4e3104b | balrog | case 0x404: /* DMA_GSCR */ |
1112 | b4e3104b | balrog | *ret = s->omap_3_1_mapping_disabled << 3;
|
1113 | b4e3104b | balrog | break;
|
1114 | b4e3104b | balrog | |
1115 | b4e3104b | balrog | case 0x408: /* DMA_GRST */ |
1116 | b4e3104b | balrog | *ret = 0;
|
1117 | b4e3104b | balrog | break;
|
1118 | b4e3104b | balrog | |
1119 | b4e3104b | balrog | case 0x442: /* DMA_HW_ID */ |
1120 | b4e3104b | balrog | case 0x444: /* DMA_PCh2_ID */ |
1121 | b4e3104b | balrog | case 0x446: /* DMA_PCh0_ID */ |
1122 | b4e3104b | balrog | case 0x448: /* DMA_PCh1_ID */ |
1123 | b4e3104b | balrog | case 0x44a: /* DMA_PChG_ID */ |
1124 | b4e3104b | balrog | case 0x44c: /* DMA_PChD_ID */ |
1125 | b4e3104b | balrog | *ret = 1;
|
1126 | b4e3104b | balrog | break;
|
1127 | b4e3104b | balrog | |
1128 | b4e3104b | balrog | case 0x44e: /* DMA_CAPS_0_U */ |
1129 | b4e3104b | balrog | *ret = (1 << 3) | /* Constant Fill Capacity */ |
1130 | b4e3104b | balrog | (1 << 2); /* Transparent BLT Capacity */ |
1131 | b4e3104b | balrog | break;
|
1132 | b4e3104b | balrog | |
1133 | b4e3104b | balrog | case 0x450: /* DMA_CAPS_0_L */ |
1134 | b4e3104b | balrog | case 0x452: /* DMA_CAPS_1_U */ |
1135 | b4e3104b | balrog | *ret = 0;
|
1136 | b4e3104b | balrog | break;
|
1137 | b4e3104b | balrog | |
1138 | b4e3104b | balrog | case 0x454: /* DMA_CAPS_1_L */ |
1139 | b4e3104b | balrog | *ret = (1 << 1); /* 1-bit palletized capability */ |
1140 | b4e3104b | balrog | break;
|
1141 | b4e3104b | balrog | |
1142 | b4e3104b | balrog | case 0x456: /* DMA_CAPS_2 */ |
1143 | b4e3104b | balrog | *ret = (1 << 8) | /* SSDIC */ |
1144 | b4e3104b | balrog | (1 << 7) | /* DDIAC */ |
1145 | b4e3104b | balrog | (1 << 6) | /* DSIAC */ |
1146 | b4e3104b | balrog | (1 << 5) | /* DPIAC */ |
1147 | b4e3104b | balrog | (1 << 4) | /* DCAC */ |
1148 | b4e3104b | balrog | (1 << 3) | /* SDIAC */ |
1149 | b4e3104b | balrog | (1 << 2) | /* SSIAC */ |
1150 | b4e3104b | balrog | (1 << 1) | /* SPIAC */ |
1151 | b4e3104b | balrog | 1; /* SCAC */ |
1152 | b4e3104b | balrog | break;
|
1153 | b4e3104b | balrog | |
1154 | b4e3104b | balrog | case 0x458: /* DMA_CAPS_3 */ |
1155 | b4e3104b | balrog | *ret = (1 << 5) | /* CCC */ |
1156 | b4e3104b | balrog | (1 << 4) | /* IC */ |
1157 | b4e3104b | balrog | (1 << 3) | /* ARC */ |
1158 | b4e3104b | balrog | (1 << 2) | /* AEC */ |
1159 | b4e3104b | balrog | (1 << 1) | /* FSC */ |
1160 | b4e3104b | balrog | 1; /* ESC */ |
1161 | b4e3104b | balrog | break;
|
1162 | b4e3104b | balrog | |
1163 | b4e3104b | balrog | case 0x45a: /* DMA_CAPS_4 */ |
1164 | b4e3104b | balrog | *ret = (1 << 6) | /* SSC */ |
1165 | b4e3104b | balrog | (1 << 5) | /* BIC */ |
1166 | b4e3104b | balrog | (1 << 4) | /* LFIC */ |
1167 | b4e3104b | balrog | (1 << 3) | /* FIC */ |
1168 | b4e3104b | balrog | (1 << 2) | /* HFIC */ |
1169 | b4e3104b | balrog | (1 << 1) | /* EDIC */ |
1170 | b4e3104b | balrog | 1; /* TOIC */ |
1171 | b4e3104b | balrog | break;
|
1172 | b4e3104b | balrog | |
1173 | b4e3104b | balrog | case 0x460: /* DMA_PCh2_SR */ |
1174 | b4e3104b | balrog | case 0x480: /* DMA_PCh0_SR */ |
1175 | b4e3104b | balrog | case 0x482: /* DMA_PCh1_SR */ |
1176 | b4e3104b | balrog | case 0x4c0: /* DMA_PChD_SR_0 */ |
1177 | b4e3104b | balrog | printf("%s: Physical Channel Status Registers not implemented.\n",
|
1178 | b4e3104b | balrog | __FUNCTION__); |
1179 | b4e3104b | balrog | *ret = 0xff;
|
1180 | b4e3104b | balrog | break;
|
1181 | b4e3104b | balrog | |
1182 | b4e3104b | balrog | default:
|
1183 | b4e3104b | balrog | return 1; |
1184 | b4e3104b | balrog | } |
1185 | b4e3104b | balrog | return 0; |
1186 | b4e3104b | balrog | } |
1187 | b4e3104b | balrog | |
1188 | b4e3104b | balrog | static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr) |
1189 | b4e3104b | balrog | { |
1190 | b4e3104b | balrog | struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
1191 | b4e3104b | balrog | int reg, ch, offset = addr - s->base;
|
1192 | b4e3104b | balrog | uint16_t ret; |
1193 | b4e3104b | balrog | |
1194 | b4e3104b | balrog | switch (offset) {
|
1195 | b4e3104b | balrog | case 0x300 ... 0x3fe: |
1196 | b4e3104b | balrog | if (s->model == omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
|
1197 | b4e3104b | balrog | if (omap_dma_3_1_lcd_read(&s->lcd_ch, offset, &ret))
|
1198 | b4e3104b | balrog | break;
|
1199 | b4e3104b | balrog | return ret;
|
1200 | b4e3104b | balrog | } |
1201 | b4e3104b | balrog | /* Fall through. */
|
1202 | b4e3104b | balrog | case 0x000 ... 0x2fe: |
1203 | b4e3104b | balrog | reg = offset & 0x3f;
|
1204 | b4e3104b | balrog | ch = (offset >> 6) & 0x0f; |
1205 | b4e3104b | balrog | if (omap_dma_ch_reg_read(s, &s->ch[ch], reg, &ret))
|
1206 | b4e3104b | balrog | break;
|
1207 | b4e3104b | balrog | return ret;
|
1208 | b4e3104b | balrog | |
1209 | b4e3104b | balrog | case 0x404 ... 0x4fe: |
1210 | b4e3104b | balrog | if (s->model == omap_dma_3_1)
|
1211 | b4e3104b | balrog | break;
|
1212 | b4e3104b | balrog | /* Fall through. */
|
1213 | b4e3104b | balrog | case 0x400: |
1214 | b4e3104b | balrog | if (omap_dma_sys_read(s, offset, &ret))
|
1215 | b4e3104b | balrog | break;
|
1216 | b4e3104b | balrog | return ret;
|
1217 | b4e3104b | balrog | |
1218 | b4e3104b | balrog | case 0xb00 ... 0xbfe: |
1219 | b4e3104b | balrog | if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
|
1220 | b4e3104b | balrog | if (omap_dma_3_2_lcd_read(&s->lcd_ch, offset, &ret))
|
1221 | b4e3104b | balrog | break;
|
1222 | b4e3104b | balrog | return ret;
|
1223 | b4e3104b | balrog | } |
1224 | b4e3104b | balrog | break;
|
1225 | b4e3104b | balrog | } |
1226 | b4e3104b | balrog | |
1227 | b4e3104b | balrog | OMAP_BAD_REG(addr); |
1228 | b4e3104b | balrog | return 0; |
1229 | b4e3104b | balrog | } |
1230 | b4e3104b | balrog | |
1231 | b4e3104b | balrog | static void omap_dma_write(void *opaque, target_phys_addr_t addr, |
1232 | b4e3104b | balrog | uint32_t value) |
1233 | b4e3104b | balrog | { |
1234 | b4e3104b | balrog | struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
1235 | b4e3104b | balrog | int reg, ch, offset = addr - s->base;
|
1236 | b4e3104b | balrog | |
1237 | b4e3104b | balrog | switch (offset) {
|
1238 | b4e3104b | balrog | case 0x300 ... 0x3fe: |
1239 | b4e3104b | balrog | if (s->model == omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
|
1240 | b4e3104b | balrog | if (omap_dma_3_1_lcd_write(&s->lcd_ch, offset, value))
|
1241 | b4e3104b | balrog | break;
|
1242 | b4e3104b | balrog | return;
|
1243 | b4e3104b | balrog | } |
1244 | b4e3104b | balrog | /* Fall through. */
|
1245 | b4e3104b | balrog | case 0x000 ... 0x2fe: |
1246 | b4e3104b | balrog | reg = offset & 0x3f;
|
1247 | b4e3104b | balrog | ch = (offset >> 6) & 0x0f; |
1248 | b4e3104b | balrog | if (omap_dma_ch_reg_write(s, &s->ch[ch], reg, value))
|
1249 | b4e3104b | balrog | break;
|
1250 | b4e3104b | balrog | return;
|
1251 | b4e3104b | balrog | |
1252 | b4e3104b | balrog | case 0x404 ... 0x4fe: |
1253 | b4e3104b | balrog | if (s->model == omap_dma_3_1)
|
1254 | b4e3104b | balrog | break;
|
1255 | b4e3104b | balrog | case 0x400: |
1256 | b4e3104b | balrog | /* Fall through. */
|
1257 | b4e3104b | balrog | if (omap_dma_sys_write(s, offset, value))
|
1258 | b4e3104b | balrog | break;
|
1259 | b4e3104b | balrog | return;
|
1260 | b4e3104b | balrog | |
1261 | b4e3104b | balrog | case 0xb00 ... 0xbfe: |
1262 | b4e3104b | balrog | if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
|
1263 | b4e3104b | balrog | if (omap_dma_3_2_lcd_write(&s->lcd_ch, offset, value))
|
1264 | b4e3104b | balrog | break;
|
1265 | b4e3104b | balrog | return;
|
1266 | b4e3104b | balrog | } |
1267 | b4e3104b | balrog | break;
|
1268 | b4e3104b | balrog | } |
1269 | b4e3104b | balrog | |
1270 | b4e3104b | balrog | OMAP_BAD_REG(addr); |
1271 | b4e3104b | balrog | } |
1272 | b4e3104b | balrog | |
1273 | b4e3104b | balrog | static CPUReadMemoryFunc *omap_dma_readfn[] = {
|
1274 | b4e3104b | balrog | omap_badwidth_read16, |
1275 | b4e3104b | balrog | omap_dma_read, |
1276 | b4e3104b | balrog | omap_badwidth_read16, |
1277 | b4e3104b | balrog | }; |
1278 | b4e3104b | balrog | |
1279 | b4e3104b | balrog | static CPUWriteMemoryFunc *omap_dma_writefn[] = {
|
1280 | b4e3104b | balrog | omap_badwidth_write16, |
1281 | b4e3104b | balrog | omap_dma_write, |
1282 | b4e3104b | balrog | omap_badwidth_write16, |
1283 | b4e3104b | balrog | }; |
1284 | b4e3104b | balrog | |
1285 | b4e3104b | balrog | static void omap_dma_request(void *opaque, int drq, int req) |
1286 | b4e3104b | balrog | { |
1287 | b4e3104b | balrog | struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
1288 | b4e3104b | balrog | /* The request pins are level triggered. */
|
1289 | b4e3104b | balrog | if (req) {
|
1290 | b4e3104b | balrog | if (~s->drq & (1 << drq)) { |
1291 | b4e3104b | balrog | s->drq |= 1 << drq;
|
1292 | b4e3104b | balrog | omap_dma_process_request(s, drq); |
1293 | b4e3104b | balrog | } |
1294 | b4e3104b | balrog | } else
|
1295 | b4e3104b | balrog | s->drq &= ~(1 << drq);
|
1296 | b4e3104b | balrog | } |
1297 | b4e3104b | balrog | |
1298 | b4e3104b | balrog | static void omap_dma_clk_update(void *opaque, int line, int on) |
1299 | b4e3104b | balrog | { |
1300 | b4e3104b | balrog | struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
1301 | b4e3104b | balrog | |
1302 | b4e3104b | balrog | if (on) {
|
1303 | b4e3104b | balrog | /* TODO: make a clever calculation */
|
1304 | b4e3104b | balrog | s->delay = ticks_per_sec >> 8;
|
1305 | b4e3104b | balrog | if (s->run_count)
|
1306 | b4e3104b | balrog | qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay); |
1307 | b4e3104b | balrog | } else {
|
1308 | b4e3104b | balrog | s->delay = 0;
|
1309 | b4e3104b | balrog | qemu_del_timer(s->tm); |
1310 | b4e3104b | balrog | } |
1311 | b4e3104b | balrog | } |
1312 | b4e3104b | balrog | |
1313 | b4e3104b | balrog | struct omap_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
|
1314 | b4e3104b | balrog | qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
|
1315 | b4e3104b | balrog | enum omap_dma_model model)
|
1316 | b4e3104b | balrog | { |
1317 | b4e3104b | balrog | int iomemtype, num_irqs, memsize, i;
|
1318 | b4e3104b | balrog | struct omap_dma_s *s = (struct omap_dma_s *) |
1319 | b4e3104b | balrog | qemu_mallocz(sizeof(struct omap_dma_s)); |
1320 | b4e3104b | balrog | |
1321 | b4e3104b | balrog | if (model == omap_dma_3_1) {
|
1322 | b4e3104b | balrog | num_irqs = 6;
|
1323 | b4e3104b | balrog | memsize = 0x800;
|
1324 | b4e3104b | balrog | } else {
|
1325 | b4e3104b | balrog | num_irqs = 16;
|
1326 | b4e3104b | balrog | memsize = 0xc00;
|
1327 | b4e3104b | balrog | } |
1328 | b4e3104b | balrog | s->base = base; |
1329 | b4e3104b | balrog | s->model = model; |
1330 | b4e3104b | balrog | s->mpu = mpu; |
1331 | b4e3104b | balrog | s->clk = clk; |
1332 | b4e3104b | balrog | s->lcd_ch.irq = lcd_irq; |
1333 | b4e3104b | balrog | s->lcd_ch.mpu = mpu; |
1334 | b4e3104b | balrog | while (num_irqs --)
|
1335 | b4e3104b | balrog | s->ch[num_irqs].irq = irqs[num_irqs]; |
1336 | b4e3104b | balrog | for (i = 0; i < 3; i ++) { |
1337 | b4e3104b | balrog | s->ch[i].sibling = &s->ch[i + 6];
|
1338 | b4e3104b | balrog | s->ch[i + 6].sibling = &s->ch[i];
|
1339 | b4e3104b | balrog | } |
1340 | b4e3104b | balrog | s->tm = qemu_new_timer(vm_clock, (QEMUTimerCB *) omap_dma_channel_run, s); |
1341 | b4e3104b | balrog | omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]); |
1342 | b4e3104b | balrog | mpu->drq = qemu_allocate_irqs(omap_dma_request, s, 32);
|
1343 | b4e3104b | balrog | omap_dma_reset(s); |
1344 | b4e3104b | balrog | omap_dma_clk_update(s, 0, 1); |
1345 | b4e3104b | balrog | |
1346 | b4e3104b | balrog | iomemtype = cpu_register_io_memory(0, omap_dma_readfn,
|
1347 | b4e3104b | balrog | omap_dma_writefn, s); |
1348 | b4e3104b | balrog | cpu_register_physical_memory(s->base, memsize, iomemtype); |
1349 | b4e3104b | balrog | |
1350 | b4e3104b | balrog | return s;
|
1351 | b4e3104b | balrog | } |
1352 | b4e3104b | balrog | |
1353 | b4e3104b | balrog | struct omap_dma_lcd_channel_s *omap_dma_get_lcdch(struct omap_dma_s *s) |
1354 | b4e3104b | balrog | { |
1355 | b4e3104b | balrog | return &s->lcd_ch;
|
1356 | b4e3104b | balrog | } |