root / hw / omap_dma.c @ e94bbefe
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/*
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* TI OMAP DMA gigacell.
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*
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* Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
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* Copyright (C) 2007-2008 Lauro Ramos Venancio <lauro.venancio@indt.org.br>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include "qemu-common.h" |
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#include "qemu-timer.h" |
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#include "omap.h" |
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#include "irq.h" |
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struct omap_dma_channel_s {
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/* transfer data */
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int burst[2]; |
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int pack[2]; |
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enum omap_dma_port port[2]; |
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target_phys_addr_t addr[2];
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omap_dma_addressing_t mode[2];
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uint16_t elements; |
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uint16_t frames; |
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int16_t frame_index[2];
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int16_t element_index[2];
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int data_type;
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|
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/* transfer type */
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int transparent_copy;
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int constant_fill;
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uint32_t color; |
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|
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/* auto init and linked channel data */
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int end_prog;
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int repeat;
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int auto_init;
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int link_enabled;
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int link_next_ch;
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|
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/* interruption data */
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int interrupts;
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int status;
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|
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/* state data */
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int active;
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int enable;
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int sync;
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int pending_request;
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int waiting_end_prog;
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uint16_t cpc; |
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|
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/* sync type */
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int fs;
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int bs;
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|
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/* compatibility */
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int omap_3_1_compatible_disable;
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|
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qemu_irq irq; |
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struct omap_dma_channel_s *sibling;
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struct omap_dma_reg_set_s {
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target_phys_addr_t src, dest; |
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int frame;
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int element;
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int frame_delta[2]; |
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int elem_delta[2]; |
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int frames;
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int elements;
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} active_set; |
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|
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/* unused parameters */
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int priority;
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int interleave_disabled;
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int type;
|
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}; |
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|
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struct omap_dma_s {
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QEMUTimer *tm; |
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struct omap_mpu_state_s *mpu;
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target_phys_addr_t base; |
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omap_clk clk; |
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int64_t delay; |
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uint32_t drq; |
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enum omap_dma_model model;
|
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int omap_3_1_mapping_disabled;
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|
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uint16_t gcr; |
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int run_count;
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|
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int chans;
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struct omap_dma_channel_s ch[16]; |
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struct omap_dma_lcd_channel_s lcd_ch;
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}; |
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|
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/* Interrupts */
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#define TIMEOUT_INTR (1 << 0) |
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#define EVENT_DROP_INTR (1 << 1) |
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#define HALF_FRAME_INTR (1 << 2) |
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#define END_FRAME_INTR (1 << 3) |
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#define LAST_FRAME_INTR (1 << 4) |
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#define END_BLOCK_INTR (1 << 5) |
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#define SYNC (1 << 6) |
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|
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static void omap_dma_interrupts_update(struct omap_dma_s *s) |
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{
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struct omap_dma_channel_s *ch = s->ch;
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int i;
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if (s->omap_3_1_mapping_disabled) {
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for (i = 0; i < s->chans; i ++, ch ++) |
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if (ch->status)
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qemu_irq_raise(ch->irq); |
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} else {
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/* First three interrupts are shared between two channels each. */
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for (i = 0; i < 6; i ++, ch ++) { |
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if (ch->status || (ch->sibling && ch->sibling->status))
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qemu_irq_raise(ch->irq); |
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} |
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} |
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} |
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static void omap_dma_channel_load(struct omap_dma_s *s, |
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struct omap_dma_channel_s *ch)
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{
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struct omap_dma_reg_set_s *a = &ch->active_set;
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int i;
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int omap_3_1 = !ch->omap_3_1_compatible_disable;
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/*
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* TODO: verify address ranges and alignment
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* TODO: port endianness
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*/
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a->src = ch->addr[0];
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a->dest = ch->addr[1];
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a->frames = ch->frames; |
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a->elements = ch->elements; |
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a->frame = 0;
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a->element = 0;
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if (unlikely(!ch->elements || !ch->frames)) {
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printf("%s: bad DMA request\n", __FUNCTION__);
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return;
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} |
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for (i = 0; i < 2; i ++) |
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switch (ch->mode[i]) {
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case constant:
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a->elem_delta[i] = 0;
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a->frame_delta[i] = 0;
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break;
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case post_incremented:
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a->elem_delta[i] = ch->data_type; |
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a->frame_delta[i] = 0;
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break;
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case single_index:
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a->elem_delta[i] = ch->data_type + |
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ch->element_index[omap_3_1 ? 0 : i] - 1; |
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a->frame_delta[i] = 0;
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break;
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case double_index:
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a->elem_delta[i] = ch->data_type + |
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ch->element_index[omap_3_1 ? 0 : i] - 1; |
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a->frame_delta[i] = ch->frame_index[omap_3_1 ? 0 : i] -
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ch->element_index[omap_3_1 ? 0 : i];
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break;
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default:
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break;
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} |
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} |
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|
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static void omap_dma_activate_channel(struct omap_dma_s *s, |
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struct omap_dma_channel_s *ch)
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{
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if (!ch->active) {
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ch->active = 1;
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if (ch->sync)
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ch->status |= SYNC; |
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s->run_count ++; |
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} |
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if (s->delay && !qemu_timer_pending(s->tm))
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qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay); |
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} |
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static void omap_dma_deactivate_channel(struct omap_dma_s *s, |
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struct omap_dma_channel_s *ch)
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{
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/* Update cpc */
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ch->cpc = ch->active_set.dest & 0xffff;
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if (ch->pending_request && !ch->waiting_end_prog) {
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/* Don't deactivate the channel */
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ch->pending_request = 0;
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if (ch->enable)
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return;
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} |
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/* Don't deactive the channel if it is synchronized and the DMA request is
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active */
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if (ch->sync && (s->drq & (1 << ch->sync)) && ch->enable) |
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return;
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if (ch->active) {
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ch->active = 0;
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ch->status &= ~SYNC; |
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s->run_count --; |
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} |
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if (!s->run_count)
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qemu_del_timer(s->tm); |
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} |
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static void omap_dma_enable_channel(struct omap_dma_s *s, |
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struct omap_dma_channel_s *ch)
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{
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if (!ch->enable) {
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ch->enable = 1;
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ch->waiting_end_prog = 0;
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omap_dma_channel_load(s, ch); |
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if ((!ch->sync) || (s->drq & (1 << ch->sync))) |
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omap_dma_activate_channel(s, ch); |
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} |
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} |
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|
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static void omap_dma_disable_channel(struct omap_dma_s *s, |
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struct omap_dma_channel_s *ch)
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{
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if (ch->enable) {
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ch->enable = 0;
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/* Discard any pending request */
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ch->pending_request = 0;
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omap_dma_deactivate_channel(s, ch); |
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} |
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} |
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|
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static void omap_dma_channel_end_prog(struct omap_dma_s *s, |
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struct omap_dma_channel_s *ch)
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{
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if (ch->waiting_end_prog) {
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ch->waiting_end_prog = 0;
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if (!ch->sync || ch->pending_request) {
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ch->pending_request = 0;
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omap_dma_activate_channel(s, ch); |
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} |
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} |
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} |
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|
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static void omap_dma_enable_3_1_mapping(struct omap_dma_s *s) |
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{
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s->omap_3_1_mapping_disabled = 0;
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s->chans = 9;
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} |
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|
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static void omap_dma_disable_3_1_mapping(struct omap_dma_s *s) |
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{
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s->omap_3_1_mapping_disabled = 1;
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s->chans = 16;
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} |
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|
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static void omap_dma_process_request(struct omap_dma_s *s, int request) |
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{
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int channel;
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int drop_event = 0; |
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struct omap_dma_channel_s *ch = s->ch;
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for (channel = 0; channel < s->chans; channel ++, ch ++) { |
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if (ch->enable && ch->sync == request) {
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if (!ch->active)
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omap_dma_activate_channel(s, ch); |
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else if (!ch->pending_request) |
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ch->pending_request = 1;
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else {
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/* Request collision */
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/* Second request received while processing other request */
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ch->status |= EVENT_DROP_INTR; |
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drop_event = 1;
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} |
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} |
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} |
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if (drop_event)
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omap_dma_interrupts_update(s); |
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} |
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|
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static void omap_dma_channel_run(struct omap_dma_s *s) |
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{
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int n = s->chans;
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uint16_t status; |
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uint8_t value[4];
|
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struct omap_dma_port_if_s *src_p, *dest_p;
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struct omap_dma_reg_set_s *a;
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struct omap_dma_channel_s *ch;
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for (ch = s->ch; n; n --, ch ++) {
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if (!ch->active)
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continue;
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a = &ch->active_set; |
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src_p = &s->mpu->port[ch->port[0]];
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dest_p = &s->mpu->port[ch->port[1]];
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if ((!ch->constant_fill && !src_p->addr_valid(s->mpu, a->src)) ||
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(!dest_p->addr_valid(s->mpu, a->dest))) {
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#if 0
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/* Bus time-out */
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if (ch->interrupts & TIMEOUT_INTR)
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ch->status |= TIMEOUT_INTR;
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omap_dma_deactivate_channel(s, ch);
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continue;
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#endif
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printf("%s: Bus time-out in DMA%i operation\n",
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__FUNCTION__, s->chans - n); |
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} |
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|
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status = ch->status; |
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while (status == ch->status && ch->active) {
|
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/* Transfer a single element */
|
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/* FIXME: check the endianness */
|
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if (!ch->constant_fill)
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cpu_physical_memory_read(a->src, value, ch->data_type); |
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else
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*(uint32_t *) value = ch->color; |
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|
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if (!ch->transparent_copy ||
|
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*(uint32_t *) value != ch->color) |
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cpu_physical_memory_write(a->dest, value, ch->data_type); |
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|
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a->src += a->elem_delta[0];
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a->dest += a->elem_delta[1];
|
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a->element ++; |
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|
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/* If the channel is element synchronized, deactivate it */
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if (ch->sync && !ch->fs && !ch->bs)
|
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omap_dma_deactivate_channel(s, ch); |
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|
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/* If it is the last frame, set the LAST_FRAME interrupt */
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if (a->element == 1 && a->frame == a->frames - 1) |
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if (ch->interrupts & LAST_FRAME_INTR)
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ch->status |= LAST_FRAME_INTR; |
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|
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/* If the half of the frame was reached, set the HALF_FRAME
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interrupt */
|
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if (a->element == (a->elements >> 1)) |
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if (ch->interrupts & HALF_FRAME_INTR)
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ch->status |= HALF_FRAME_INTR; |
| 360 |
|
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if (a->element == a->elements) {
|
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/* End of Frame */
|
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a->element = 0;
|
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a->src += a->frame_delta[0];
|
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a->dest += a->frame_delta[1];
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a->frame ++; |
| 367 |
|
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/* If the channel is frame synchronized, deactivate it */
|
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if (ch->sync && ch->fs)
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omap_dma_deactivate_channel(s, ch); |
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|
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/* If the channel is async, update cpc */
|
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if (!ch->sync)
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ch->cpc = a->dest & 0xffff;
|
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|
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/* Set the END_FRAME interrupt */
|
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if (ch->interrupts & END_FRAME_INTR)
|
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ch->status |= END_FRAME_INTR; |
| 379 |
|
| 380 |
if (a->frame == a->frames) {
|
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/* End of Block */
|
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/* Disable the channel */
|
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|
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if (ch->omap_3_1_compatible_disable) {
|
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omap_dma_disable_channel(s, ch); |
| 386 |
if (ch->link_enabled)
|
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omap_dma_enable_channel(s, |
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&s->ch[ch->link_next_ch]); |
| 389 |
} else {
|
| 390 |
if (!ch->auto_init)
|
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omap_dma_disable_channel(s, ch); |
| 392 |
else if (ch->repeat || ch->end_prog) |
| 393 |
omap_dma_channel_load(s, ch); |
| 394 |
else {
|
| 395 |
ch->waiting_end_prog = 1;
|
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omap_dma_deactivate_channel(s, ch); |
| 397 |
} |
| 398 |
} |
| 399 |
|
| 400 |
if (ch->interrupts & END_BLOCK_INTR)
|
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ch->status |= END_BLOCK_INTR; |
| 402 |
} |
| 403 |
} |
| 404 |
} |
| 405 |
} |
| 406 |
|
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omap_dma_interrupts_update(s); |
| 408 |
if (s->run_count && s->delay)
|
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qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay); |
| 410 |
} |
| 411 |
|
| 412 |
void omap_dma_reset(struct omap_dma_s *s) |
| 413 |
{
|
| 414 |
int i;
|
| 415 |
|
| 416 |
qemu_del_timer(s->tm); |
| 417 |
s->gcr = 0x0004;
|
| 418 |
s->drq = 0x00000000;
|
| 419 |
s->run_count = 0;
|
| 420 |
s->lcd_ch.src = emiff; |
| 421 |
s->lcd_ch.condition = 0;
|
| 422 |
s->lcd_ch.interrupts = 0;
|
| 423 |
s->lcd_ch.dual = 0;
|
| 424 |
omap_dma_enable_3_1_mapping(s); |
| 425 |
for (i = 0; i < s->chans; i ++) { |
| 426 |
memset(&s->ch[i].burst, 0, sizeof(s->ch[i].burst)); |
| 427 |
memset(&s->ch[i].port, 0, sizeof(s->ch[i].port)); |
| 428 |
memset(&s->ch[i].mode, 0, sizeof(s->ch[i].mode)); |
| 429 |
memset(&s->ch[i].elements, 0, sizeof(s->ch[i].elements)); |
| 430 |
memset(&s->ch[i].frames, 0, sizeof(s->ch[i].frames)); |
| 431 |
memset(&s->ch[i].frame_index, 0, sizeof(s->ch[i].frame_index)); |
| 432 |
memset(&s->ch[i].element_index, 0, sizeof(s->ch[i].element_index)); |
| 433 |
memset(&s->ch[i].data_type, 0, sizeof(s->ch[i].data_type)); |
| 434 |
memset(&s->ch[i].transparent_copy, 0,
|
| 435 |
sizeof(s->ch[i].transparent_copy));
|
| 436 |
memset(&s->ch[i].constant_fill, 0, sizeof(s->ch[i].constant_fill)); |
| 437 |
memset(&s->ch[i].color, 0, sizeof(s->ch[i].color)); |
| 438 |
memset(&s->ch[i].end_prog, 0, sizeof(s->ch[i].end_prog)); |
| 439 |
memset(&s->ch[i].repeat, 0, sizeof(s->ch[i].repeat)); |
| 440 |
memset(&s->ch[i].auto_init, 0, sizeof(s->ch[i].auto_init)); |
| 441 |
memset(&s->ch[i].link_enabled, 0, sizeof(s->ch[i].link_enabled)); |
| 442 |
memset(&s->ch[i].link_next_ch, 0, sizeof(s->ch[i].link_next_ch)); |
| 443 |
s->ch[i].interrupts = 0x0003;
|
| 444 |
memset(&s->ch[i].status, 0, sizeof(s->ch[i].status)); |
| 445 |
memset(&s->ch[i].active, 0, sizeof(s->ch[i].active)); |
| 446 |
memset(&s->ch[i].enable, 0, sizeof(s->ch[i].enable)); |
| 447 |
memset(&s->ch[i].sync, 0, sizeof(s->ch[i].sync)); |
| 448 |
memset(&s->ch[i].pending_request, 0, sizeof(s->ch[i].pending_request)); |
| 449 |
memset(&s->ch[i].waiting_end_prog, 0,
|
| 450 |
sizeof(s->ch[i].waiting_end_prog));
|
| 451 |
memset(&s->ch[i].cpc, 0, sizeof(s->ch[i].cpc)); |
| 452 |
memset(&s->ch[i].fs, 0, sizeof(s->ch[i].fs)); |
| 453 |
memset(&s->ch[i].bs, 0, sizeof(s->ch[i].bs)); |
| 454 |
memset(&s->ch[i].omap_3_1_compatible_disable, 0,
|
| 455 |
sizeof(s->ch[i].omap_3_1_compatible_disable));
|
| 456 |
memset(&s->ch[i].active_set, 0, sizeof(s->ch[i].active_set)); |
| 457 |
memset(&s->ch[i].priority, 0, sizeof(s->ch[i].priority)); |
| 458 |
memset(&s->ch[i].interleave_disabled, 0,
|
| 459 |
sizeof(s->ch[i].interleave_disabled));
|
| 460 |
memset(&s->ch[i].type, 0, sizeof(s->ch[i].type)); |
| 461 |
} |
| 462 |
} |
| 463 |
|
| 464 |
static int omap_dma_ch_reg_read(struct omap_dma_s *s, |
| 465 |
struct omap_dma_channel_s *ch, int reg, uint16_t *value) |
| 466 |
{
|
| 467 |
switch (reg) {
|
| 468 |
case 0x00: /* SYS_DMA_CSDP_CH0 */ |
| 469 |
*value = (ch->burst[1] << 14) | |
| 470 |
(ch->pack[1] << 13) | |
| 471 |
(ch->port[1] << 9) | |
| 472 |
(ch->burst[0] << 7) | |
| 473 |
(ch->pack[0] << 6) | |
| 474 |
(ch->port[0] << 2) | |
| 475 |
(ch->data_type >> 1);
|
| 476 |
break;
|
| 477 |
|
| 478 |
case 0x02: /* SYS_DMA_CCR_CH0 */ |
| 479 |
if (s->model == omap_dma_3_1)
|
| 480 |
*value = 0 << 10; /* FIFO_FLUSH reads as 0 */ |
| 481 |
else
|
| 482 |
*value = ch->omap_3_1_compatible_disable << 10;
|
| 483 |
*value |= (ch->mode[1] << 14) | |
| 484 |
(ch->mode[0] << 12) | |
| 485 |
(ch->end_prog << 11) |
|
| 486 |
(ch->repeat << 9) |
|
| 487 |
(ch->auto_init << 8) |
|
| 488 |
(ch->enable << 7) |
|
| 489 |
(ch->priority << 6) |
|
| 490 |
(ch->fs << 5) | ch->sync;
|
| 491 |
break;
|
| 492 |
|
| 493 |
case 0x04: /* SYS_DMA_CICR_CH0 */ |
| 494 |
*value = ch->interrupts; |
| 495 |
break;
|
| 496 |
|
| 497 |
case 0x06: /* SYS_DMA_CSR_CH0 */ |
| 498 |
*value = ch->status; |
| 499 |
ch->status &= SYNC; |
| 500 |
if (!ch->omap_3_1_compatible_disable && ch->sibling) {
|
| 501 |
*value |= (ch->sibling->status & 0x3f) << 6; |
| 502 |
ch->sibling->status &= SYNC; |
| 503 |
} |
| 504 |
qemu_irq_lower(ch->irq); |
| 505 |
break;
|
| 506 |
|
| 507 |
case 0x08: /* SYS_DMA_CSSA_L_CH0 */ |
| 508 |
*value = ch->addr[0] & 0x0000ffff; |
| 509 |
break;
|
| 510 |
|
| 511 |
case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ |
| 512 |
*value = ch->addr[0] >> 16; |
| 513 |
break;
|
| 514 |
|
| 515 |
case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ |
| 516 |
*value = ch->addr[1] & 0x0000ffff; |
| 517 |
break;
|
| 518 |
|
| 519 |
case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ |
| 520 |
*value = ch->addr[1] >> 16; |
| 521 |
break;
|
| 522 |
|
| 523 |
case 0x10: /* SYS_DMA_CEN_CH0 */ |
| 524 |
*value = ch->elements; |
| 525 |
break;
|
| 526 |
|
| 527 |
case 0x12: /* SYS_DMA_CFN_CH0 */ |
| 528 |
*value = ch->frames; |
| 529 |
break;
|
| 530 |
|
| 531 |
case 0x14: /* SYS_DMA_CFI_CH0 */ |
| 532 |
*value = ch->frame_index[0];
|
| 533 |
break;
|
| 534 |
|
| 535 |
case 0x16: /* SYS_DMA_CEI_CH0 */ |
| 536 |
*value = ch->element_index[0];
|
| 537 |
break;
|
| 538 |
|
| 539 |
case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */ |
| 540 |
if (ch->omap_3_1_compatible_disable)
|
| 541 |
*value = ch->active_set.src & 0xffff; /* CSAC */ |
| 542 |
else
|
| 543 |
*value = ch->cpc; |
| 544 |
break;
|
| 545 |
|
| 546 |
case 0x1a: /* DMA_CDAC */ |
| 547 |
*value = ch->active_set.dest & 0xffff; /* CDAC */ |
| 548 |
break;
|
| 549 |
|
| 550 |
case 0x1c: /* DMA_CDEI */ |
| 551 |
*value = ch->element_index[1];
|
| 552 |
break;
|
| 553 |
|
| 554 |
case 0x1e: /* DMA_CDFI */ |
| 555 |
*value = ch->frame_index[1];
|
| 556 |
break;
|
| 557 |
|
| 558 |
case 0x20: /* DMA_COLOR_L */ |
| 559 |
*value = ch->color & 0xffff;
|
| 560 |
break;
|
| 561 |
|
| 562 |
case 0x22: /* DMA_COLOR_U */ |
| 563 |
*value = ch->color >> 16;
|
| 564 |
break;
|
| 565 |
|
| 566 |
case 0x24: /* DMA_CCR2 */ |
| 567 |
*value = (ch->bs << 2) |
|
| 568 |
(ch->transparent_copy << 1) |
|
| 569 |
ch->constant_fill; |
| 570 |
break;
|
| 571 |
|
| 572 |
case 0x28: /* DMA_CLNK_CTRL */ |
| 573 |
*value = (ch->link_enabled << 15) |
|
| 574 |
(ch->link_next_ch & 0xf);
|
| 575 |
break;
|
| 576 |
|
| 577 |
case 0x2a: /* DMA_LCH_CTRL */ |
| 578 |
*value = (ch->interleave_disabled << 15) |
|
| 579 |
ch->type; |
| 580 |
break;
|
| 581 |
|
| 582 |
default:
|
| 583 |
return 1; |
| 584 |
} |
| 585 |
return 0; |
| 586 |
} |
| 587 |
|
| 588 |
static int omap_dma_ch_reg_write(struct omap_dma_s *s, |
| 589 |
struct omap_dma_channel_s *ch, int reg, uint16_t value) |
| 590 |
{
|
| 591 |
switch (reg) {
|
| 592 |
case 0x00: /* SYS_DMA_CSDP_CH0 */ |
| 593 |
ch->burst[1] = (value & 0xc000) >> 14; |
| 594 |
ch->pack[1] = (value & 0x2000) >> 13; |
| 595 |
ch->port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9); |
| 596 |
ch->burst[0] = (value & 0x0180) >> 7; |
| 597 |
ch->pack[0] = (value & 0x0040) >> 6; |
| 598 |
ch->port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2); |
| 599 |
ch->data_type = (1 << (value & 3)); |
| 600 |
if (ch->port[0] >= omap_dma_port_last) |
| 601 |
printf("%s: invalid DMA port %i\n", __FUNCTION__,
|
| 602 |
ch->port[0]);
|
| 603 |
if (ch->port[1] >= omap_dma_port_last) |
| 604 |
printf("%s: invalid DMA port %i\n", __FUNCTION__,
|
| 605 |
ch->port[1]);
|
| 606 |
if ((value & 3) == 3) |
| 607 |
printf("%s: bad data_type for DMA channel\n", __FUNCTION__);
|
| 608 |
break;
|
| 609 |
|
| 610 |
case 0x02: /* SYS_DMA_CCR_CH0 */ |
| 611 |
ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14); |
| 612 |
ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12); |
| 613 |
ch->end_prog = (value & 0x0800) >> 11; |
| 614 |
if (s->model > omap_dma_3_1)
|
| 615 |
ch->omap_3_1_compatible_disable = (value >> 10) & 0x1; |
| 616 |
ch->repeat = (value & 0x0200) >> 9; |
| 617 |
ch->auto_init = (value & 0x0100) >> 8; |
| 618 |
ch->priority = (value & 0x0040) >> 6; |
| 619 |
ch->fs = (value & 0x0020) >> 5; |
| 620 |
ch->sync = value & 0x001f;
|
| 621 |
|
| 622 |
if (value & 0x0080) |
| 623 |
omap_dma_enable_channel(s, ch); |
| 624 |
else
|
| 625 |
omap_dma_disable_channel(s, ch); |
| 626 |
|
| 627 |
if (ch->end_prog)
|
| 628 |
omap_dma_channel_end_prog(s, ch); |
| 629 |
|
| 630 |
break;
|
| 631 |
|
| 632 |
case 0x04: /* SYS_DMA_CICR_CH0 */ |
| 633 |
ch->interrupts = value; |
| 634 |
break;
|
| 635 |
|
| 636 |
case 0x06: /* SYS_DMA_CSR_CH0 */ |
| 637 |
OMAP_RO_REG((target_phys_addr_t) reg); |
| 638 |
break;
|
| 639 |
|
| 640 |
case 0x08: /* SYS_DMA_CSSA_L_CH0 */ |
| 641 |
ch->addr[0] &= 0xffff0000; |
| 642 |
ch->addr[0] |= value;
|
| 643 |
break;
|
| 644 |
|
| 645 |
case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ |
| 646 |
ch->addr[0] &= 0x0000ffff; |
| 647 |
ch->addr[0] |= (uint32_t) value << 16; |
| 648 |
break;
|
| 649 |
|
| 650 |
case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ |
| 651 |
ch->addr[1] &= 0xffff0000; |
| 652 |
ch->addr[1] |= value;
|
| 653 |
break;
|
| 654 |
|
| 655 |
case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ |
| 656 |
ch->addr[1] &= 0x0000ffff; |
| 657 |
ch->addr[1] |= (uint32_t) value << 16; |
| 658 |
break;
|
| 659 |
|
| 660 |
case 0x10: /* SYS_DMA_CEN_CH0 */ |
| 661 |
ch->elements = value; |
| 662 |
break;
|
| 663 |
|
| 664 |
case 0x12: /* SYS_DMA_CFN_CH0 */ |
| 665 |
ch->frames = value; |
| 666 |
break;
|
| 667 |
|
| 668 |
case 0x14: /* SYS_DMA_CFI_CH0 */ |
| 669 |
ch->frame_index[0] = (int16_t) value;
|
| 670 |
break;
|
| 671 |
|
| 672 |
case 0x16: /* SYS_DMA_CEI_CH0 */ |
| 673 |
ch->element_index[0] = (int16_t) value;
|
| 674 |
break;
|
| 675 |
|
| 676 |
case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */ |
| 677 |
OMAP_RO_REG((target_phys_addr_t) reg); |
| 678 |
break;
|
| 679 |
|
| 680 |
case 0x1c: /* DMA_CDEI */ |
| 681 |
ch->element_index[1] = (int16_t) value;
|
| 682 |
break;
|
| 683 |
|
| 684 |
case 0x1e: /* DMA_CDFI */ |
| 685 |
ch->frame_index[1] = (int16_t) value;
|
| 686 |
break;
|
| 687 |
|
| 688 |
case 0x20: /* DMA_COLOR_L */ |
| 689 |
ch->color &= 0xffff0000;
|
| 690 |
ch->color |= value; |
| 691 |
break;
|
| 692 |
|
| 693 |
case 0x22: /* DMA_COLOR_U */ |
| 694 |
ch->color &= 0xffff;
|
| 695 |
ch->color |= value << 16;
|
| 696 |
break;
|
| 697 |
|
| 698 |
case 0x24: /* DMA_CCR2 */ |
| 699 |
ch->bs = (value >> 2) & 0x1; |
| 700 |
ch->transparent_copy = (value >> 1) & 0x1; |
| 701 |
ch->constant_fill = value & 0x1;
|
| 702 |
break;
|
| 703 |
|
| 704 |
case 0x28: /* DMA_CLNK_CTRL */ |
| 705 |
ch->link_enabled = (value >> 15) & 0x1; |
| 706 |
if (value & (1 << 14)) { /* Stop_Lnk */ |
| 707 |
ch->link_enabled = 0;
|
| 708 |
omap_dma_disable_channel(s, ch); |
| 709 |
} |
| 710 |
ch->link_next_ch = value & 0x1f;
|
| 711 |
break;
|
| 712 |
|
| 713 |
case 0x2a: /* DMA_LCH_CTRL */ |
| 714 |
ch->interleave_disabled = (value >> 15) & 0x1; |
| 715 |
ch->type = value & 0xf;
|
| 716 |
break;
|
| 717 |
|
| 718 |
default:
|
| 719 |
return 1; |
| 720 |
} |
| 721 |
return 0; |
| 722 |
} |
| 723 |
|
| 724 |
static int omap_dma_3_2_lcd_write(struct omap_dma_lcd_channel_s *s, int offset, |
| 725 |
uint16_t value) |
| 726 |
{
|
| 727 |
switch (offset) {
|
| 728 |
case 0xbc0: /* DMA_LCD_CSDP */ |
| 729 |
s->brust_f2 = (value >> 14) & 0x3; |
| 730 |
s->pack_f2 = (value >> 13) & 0x1; |
| 731 |
s->data_type_f2 = (1 << ((value >> 11) & 0x3)); |
| 732 |
s->brust_f1 = (value >> 7) & 0x3; |
| 733 |
s->pack_f1 = (value >> 6) & 0x1; |
| 734 |
s->data_type_f1 = (1 << ((value >> 0) & 0x3)); |
| 735 |
break;
|
| 736 |
|
| 737 |
case 0xbc2: /* DMA_LCD_CCR */ |
| 738 |
s->mode_f2 = (value >> 14) & 0x3; |
| 739 |
s->mode_f1 = (value >> 12) & 0x3; |
| 740 |
s->end_prog = (value >> 11) & 0x1; |
| 741 |
s->omap_3_1_compatible_disable = (value >> 10) & 0x1; |
| 742 |
s->repeat = (value >> 9) & 0x1; |
| 743 |
s->auto_init = (value >> 8) & 0x1; |
| 744 |
s->running = (value >> 7) & 0x1; |
| 745 |
s->priority = (value >> 6) & 0x1; |
| 746 |
s->bs = (value >> 4) & 0x1; |
| 747 |
break;
|
| 748 |
|
| 749 |
case 0xbc4: /* DMA_LCD_CTRL */ |
| 750 |
s->dst = (value >> 8) & 0x1; |
| 751 |
s->src = ((value >> 6) & 0x3) << 1; |
| 752 |
s->condition = 0;
|
| 753 |
/* Assume no bus errors and thus no BUS_ERROR irq bits. */
|
| 754 |
s->interrupts = (value >> 1) & 1; |
| 755 |
s->dual = value & 1;
|
| 756 |
break;
|
| 757 |
|
| 758 |
case 0xbc8: /* TOP_B1_L */ |
| 759 |
s->src_f1_top &= 0xffff0000;
|
| 760 |
s->src_f1_top |= 0x0000ffff & value;
|
| 761 |
break;
|
| 762 |
|
| 763 |
case 0xbca: /* TOP_B1_U */ |
| 764 |
s->src_f1_top &= 0x0000ffff;
|
| 765 |
s->src_f1_top |= value << 16;
|
| 766 |
break;
|
| 767 |
|
| 768 |
case 0xbcc: /* BOT_B1_L */ |
| 769 |
s->src_f1_bottom &= 0xffff0000;
|
| 770 |
s->src_f1_bottom |= 0x0000ffff & value;
|
| 771 |
break;
|
| 772 |
|
| 773 |
case 0xbce: /* BOT_B1_U */ |
| 774 |
s->src_f1_bottom &= 0x0000ffff;
|
| 775 |
s->src_f1_bottom |= (uint32_t) value << 16;
|
| 776 |
break;
|
| 777 |
|
| 778 |
case 0xbd0: /* TOP_B2_L */ |
| 779 |
s->src_f2_top &= 0xffff0000;
|
| 780 |
s->src_f2_top |= 0x0000ffff & value;
|
| 781 |
break;
|
| 782 |
|
| 783 |
case 0xbd2: /* TOP_B2_U */ |
| 784 |
s->src_f2_top &= 0x0000ffff;
|
| 785 |
s->src_f2_top |= (uint32_t) value << 16;
|
| 786 |
break;
|
| 787 |
|
| 788 |
case 0xbd4: /* BOT_B2_L */ |
| 789 |
s->src_f2_bottom &= 0xffff0000;
|
| 790 |
s->src_f2_bottom |= 0x0000ffff & value;
|
| 791 |
break;
|
| 792 |
|
| 793 |
case 0xbd6: /* BOT_B2_U */ |
| 794 |
s->src_f2_bottom &= 0x0000ffff;
|
| 795 |
s->src_f2_bottom |= (uint32_t) value << 16;
|
| 796 |
break;
|
| 797 |
|
| 798 |
case 0xbd8: /* DMA_LCD_SRC_EI_B1 */ |
| 799 |
s->element_index_f1 = value; |
| 800 |
break;
|
| 801 |
|
| 802 |
case 0xbda: /* DMA_LCD_SRC_FI_B1_L */ |
| 803 |
s->frame_index_f1 &= 0xffff0000;
|
| 804 |
s->frame_index_f1 |= 0x0000ffff & value;
|
| 805 |
break;
|
| 806 |
|
| 807 |
case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */ |
| 808 |
s->frame_index_f1 &= 0x0000ffff;
|
| 809 |
s->frame_index_f1 |= (uint32_t) value << 16;
|
| 810 |
break;
|
| 811 |
|
| 812 |
case 0xbdc: /* DMA_LCD_SRC_EI_B2 */ |
| 813 |
s->element_index_f2 = value; |
| 814 |
break;
|
| 815 |
|
| 816 |
case 0xbde: /* DMA_LCD_SRC_FI_B2_L */ |
| 817 |
s->frame_index_f2 &= 0xffff0000;
|
| 818 |
s->frame_index_f2 |= 0x0000ffff & value;
|
| 819 |
break;
|
| 820 |
|
| 821 |
case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */ |
| 822 |
s->frame_index_f2 &= 0x0000ffff;
|
| 823 |
s->frame_index_f2 |= (uint32_t) value << 16;
|
| 824 |
break;
|
| 825 |
|
| 826 |
case 0xbe0: /* DMA_LCD_SRC_EN_B1 */ |
| 827 |
s->elements_f1 = value; |
| 828 |
break;
|
| 829 |
|
| 830 |
case 0xbe4: /* DMA_LCD_SRC_FN_B1 */ |
| 831 |
s->frames_f1 = value; |
| 832 |
break;
|
| 833 |
|
| 834 |
case 0xbe2: /* DMA_LCD_SRC_EN_B2 */ |
| 835 |
s->elements_f2 = value; |
| 836 |
break;
|
| 837 |
|
| 838 |
case 0xbe6: /* DMA_LCD_SRC_FN_B2 */ |
| 839 |
s->frames_f2 = value; |
| 840 |
break;
|
| 841 |
|
| 842 |
case 0xbea: /* DMA_LCD_LCH_CTRL */ |
| 843 |
s->lch_type = value & 0xf;
|
| 844 |
break;
|
| 845 |
|
| 846 |
default:
|
| 847 |
return 1; |
| 848 |
} |
| 849 |
return 0; |
| 850 |
} |
| 851 |
|
| 852 |
static int omap_dma_3_2_lcd_read(struct omap_dma_lcd_channel_s *s, int offset, |
| 853 |
uint16_t *ret) |
| 854 |
{
|
| 855 |
switch (offset) {
|
| 856 |
case 0xbc0: /* DMA_LCD_CSDP */ |
| 857 |
*ret = (s->brust_f2 << 14) |
|
| 858 |
(s->pack_f2 << 13) |
|
| 859 |
((s->data_type_f2 >> 1) << 11) | |
| 860 |
(s->brust_f1 << 7) |
|
| 861 |
(s->pack_f1 << 6) |
|
| 862 |
((s->data_type_f1 >> 1) << 0); |
| 863 |
break;
|
| 864 |
|
| 865 |
case 0xbc2: /* DMA_LCD_CCR */ |
| 866 |
*ret = (s->mode_f2 << 14) |
|
| 867 |
(s->mode_f1 << 12) |
|
| 868 |
(s->end_prog << 11) |
|
| 869 |
(s->omap_3_1_compatible_disable << 10) |
|
| 870 |
(s->repeat << 9) |
|
| 871 |
(s->auto_init << 8) |
|
| 872 |
(s->running << 7) |
|
| 873 |
(s->priority << 6) |
|
| 874 |
(s->bs << 4);
|
| 875 |
break;
|
| 876 |
|
| 877 |
case 0xbc4: /* DMA_LCD_CTRL */ |
| 878 |
qemu_irq_lower(s->irq); |
| 879 |
*ret = (s->dst << 8) |
|
| 880 |
((s->src & 0x6) << 5) | |
| 881 |
(s->condition << 3) |
|
| 882 |
(s->interrupts << 1) |
|
| 883 |
s->dual; |
| 884 |
break;
|
| 885 |
|
| 886 |
case 0xbc8: /* TOP_B1_L */ |
| 887 |
*ret = s->src_f1_top & 0xffff;
|
| 888 |
break;
|
| 889 |
|
| 890 |
case 0xbca: /* TOP_B1_U */ |
| 891 |
*ret = s->src_f1_top >> 16;
|
| 892 |
break;
|
| 893 |
|
| 894 |
case 0xbcc: /* BOT_B1_L */ |
| 895 |
*ret = s->src_f1_bottom & 0xffff;
|
| 896 |
break;
|
| 897 |
|
| 898 |
case 0xbce: /* BOT_B1_U */ |
| 899 |
*ret = s->src_f1_bottom >> 16;
|
| 900 |
break;
|
| 901 |
|
| 902 |
case 0xbd0: /* TOP_B2_L */ |
| 903 |
*ret = s->src_f2_top & 0xffff;
|
| 904 |
break;
|
| 905 |
|
| 906 |
case 0xbd2: /* TOP_B2_U */ |
| 907 |
*ret = s->src_f2_top >> 16;
|
| 908 |
break;
|
| 909 |
|
| 910 |
case 0xbd4: /* BOT_B2_L */ |
| 911 |
*ret = s->src_f2_bottom & 0xffff;
|
| 912 |
break;
|
| 913 |
|
| 914 |
case 0xbd6: /* BOT_B2_U */ |
| 915 |
*ret = s->src_f2_bottom >> 16;
|
| 916 |
break;
|
| 917 |
|
| 918 |
case 0xbd8: /* DMA_LCD_SRC_EI_B1 */ |
| 919 |
*ret = s->element_index_f1; |
| 920 |
break;
|
| 921 |
|
| 922 |
case 0xbda: /* DMA_LCD_SRC_FI_B1_L */ |
| 923 |
*ret = s->frame_index_f1 & 0xffff;
|
| 924 |
break;
|
| 925 |
|
| 926 |
case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */ |
| 927 |
*ret = s->frame_index_f1 >> 16;
|
| 928 |
break;
|
| 929 |
|
| 930 |
case 0xbdc: /* DMA_LCD_SRC_EI_B2 */ |
| 931 |
*ret = s->element_index_f2; |
| 932 |
break;
|
| 933 |
|
| 934 |
case 0xbde: /* DMA_LCD_SRC_FI_B2_L */ |
| 935 |
*ret = s->frame_index_f2 & 0xffff;
|
| 936 |
break;
|
| 937 |
|
| 938 |
case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */ |
| 939 |
*ret = s->frame_index_f2 >> 16;
|
| 940 |
break;
|
| 941 |
|
| 942 |
case 0xbe0: /* DMA_LCD_SRC_EN_B1 */ |
| 943 |
*ret = s->elements_f1; |
| 944 |
break;
|
| 945 |
|
| 946 |
case 0xbe4: /* DMA_LCD_SRC_FN_B1 */ |
| 947 |
*ret = s->frames_f1; |
| 948 |
break;
|
| 949 |
|
| 950 |
case 0xbe2: /* DMA_LCD_SRC_EN_B2 */ |
| 951 |
*ret = s->elements_f2; |
| 952 |
break;
|
| 953 |
|
| 954 |
case 0xbe6: /* DMA_LCD_SRC_FN_B2 */ |
| 955 |
*ret = s->frames_f2; |
| 956 |
break;
|
| 957 |
|
| 958 |
case 0xbea: /* DMA_LCD_LCH_CTRL */ |
| 959 |
*ret = s->lch_type; |
| 960 |
break;
|
| 961 |
|
| 962 |
default:
|
| 963 |
return 1; |
| 964 |
} |
| 965 |
return 0; |
| 966 |
} |
| 967 |
|
| 968 |
static int omap_dma_3_1_lcd_write(struct omap_dma_lcd_channel_s *s, int offset, |
| 969 |
uint16_t value) |
| 970 |
{
|
| 971 |
switch (offset) {
|
| 972 |
case 0x300: /* SYS_DMA_LCD_CTRL */ |
| 973 |
s->src = (value & 0x40) ? imif : emiff;
|
| 974 |
s->condition = 0;
|
| 975 |
/* Assume no bus errors and thus no BUS_ERROR irq bits. */
|
| 976 |
s->interrupts = (value >> 1) & 1; |
| 977 |
s->dual = value & 1;
|
| 978 |
break;
|
| 979 |
|
| 980 |
case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ |
| 981 |
s->src_f1_top &= 0xffff0000;
|
| 982 |
s->src_f1_top |= 0x0000ffff & value;
|
| 983 |
break;
|
| 984 |
|
| 985 |
case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ |
| 986 |
s->src_f1_top &= 0x0000ffff;
|
| 987 |
s->src_f1_top |= value << 16;
|
| 988 |
break;
|
| 989 |
|
| 990 |
case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ |
| 991 |
s->src_f1_bottom &= 0xffff0000;
|
| 992 |
s->src_f1_bottom |= 0x0000ffff & value;
|
| 993 |
break;
|
| 994 |
|
| 995 |
case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ |
| 996 |
s->src_f1_bottom &= 0x0000ffff;
|
| 997 |
s->src_f1_bottom |= value << 16;
|
| 998 |
break;
|
| 999 |
|
| 1000 |
case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ |
| 1001 |
s->src_f2_top &= 0xffff0000;
|
| 1002 |
s->src_f2_top |= 0x0000ffff & value;
|
| 1003 |
break;
|
| 1004 |
|
| 1005 |
case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ |
| 1006 |
s->src_f2_top &= 0x0000ffff;
|
| 1007 |
s->src_f2_top |= value << 16;
|
| 1008 |
break;
|
| 1009 |
|
| 1010 |
case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ |
| 1011 |
s->src_f2_bottom &= 0xffff0000;
|
| 1012 |
s->src_f2_bottom |= 0x0000ffff & value;
|
| 1013 |
break;
|
| 1014 |
|
| 1015 |
case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ |
| 1016 |
s->src_f2_bottom &= 0x0000ffff;
|
| 1017 |
s->src_f2_bottom |= value << 16;
|
| 1018 |
break;
|
| 1019 |
|
| 1020 |
default:
|
| 1021 |
return 1; |
| 1022 |
} |
| 1023 |
return 0; |
| 1024 |
} |
| 1025 |
|
| 1026 |
static int omap_dma_3_1_lcd_read(struct omap_dma_lcd_channel_s *s, int offset, |
| 1027 |
uint16_t *ret) |
| 1028 |
{
|
| 1029 |
int i;
|
| 1030 |
|
| 1031 |
switch (offset) {
|
| 1032 |
case 0x300: /* SYS_DMA_LCD_CTRL */ |
| 1033 |
i = s->condition; |
| 1034 |
s->condition = 0;
|
| 1035 |
qemu_irq_lower(s->irq); |
| 1036 |
*ret = ((s->src == imif) << 6) | (i << 3) | |
| 1037 |
(s->interrupts << 1) | s->dual;
|
| 1038 |
break;
|
| 1039 |
|
| 1040 |
case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ |
| 1041 |
*ret = s->src_f1_top & 0xffff;
|
| 1042 |
break;
|
| 1043 |
|
| 1044 |
case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ |
| 1045 |
*ret = s->src_f1_top >> 16;
|
| 1046 |
break;
|
| 1047 |
|
| 1048 |
case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ |
| 1049 |
*ret = s->src_f1_bottom & 0xffff;
|
| 1050 |
break;
|
| 1051 |
|
| 1052 |
case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ |
| 1053 |
*ret = s->src_f1_bottom >> 16;
|
| 1054 |
break;
|
| 1055 |
|
| 1056 |
case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ |
| 1057 |
*ret = s->src_f2_top & 0xffff;
|
| 1058 |
break;
|
| 1059 |
|
| 1060 |
case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ |
| 1061 |
*ret = s->src_f2_top >> 16;
|
| 1062 |
break;
|
| 1063 |
|
| 1064 |
case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ |
| 1065 |
*ret = s->src_f2_bottom & 0xffff;
|
| 1066 |
break;
|
| 1067 |
|
| 1068 |
case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ |
| 1069 |
*ret = s->src_f2_bottom >> 16;
|
| 1070 |
break;
|
| 1071 |
|
| 1072 |
default:
|
| 1073 |
return 1; |
| 1074 |
} |
| 1075 |
return 0; |
| 1076 |
} |
| 1077 |
|
| 1078 |
static int omap_dma_sys_write(struct omap_dma_s *s, int offset, uint16_t value) |
| 1079 |
{
|
| 1080 |
switch (offset) {
|
| 1081 |
case 0x400: /* SYS_DMA_GCR */ |
| 1082 |
s->gcr = value; |
| 1083 |
break;
|
| 1084 |
|
| 1085 |
case 0x404: /* DMA_GSCR */ |
| 1086 |
if (value & 0x8) |
| 1087 |
omap_dma_disable_3_1_mapping(s); |
| 1088 |
else
|
| 1089 |
omap_dma_enable_3_1_mapping(s); |
| 1090 |
break;
|
| 1091 |
|
| 1092 |
case 0x408: /* DMA_GRST */ |
| 1093 |
if (value & 0x1) |
| 1094 |
omap_dma_reset(s); |
| 1095 |
break;
|
| 1096 |
|
| 1097 |
default:
|
| 1098 |
return 1; |
| 1099 |
} |
| 1100 |
return 0; |
| 1101 |
} |
| 1102 |
|
| 1103 |
static int omap_dma_sys_read(struct omap_dma_s *s, int offset, |
| 1104 |
uint16_t *ret) |
| 1105 |
{
|
| 1106 |
switch (offset) {
|
| 1107 |
case 0x400: /* SYS_DMA_GCR */ |
| 1108 |
*ret = s->gcr; |
| 1109 |
break;
|
| 1110 |
|
| 1111 |
case 0x404: /* DMA_GSCR */ |
| 1112 |
*ret = s->omap_3_1_mapping_disabled << 3;
|
| 1113 |
break;
|
| 1114 |
|
| 1115 |
case 0x408: /* DMA_GRST */ |
| 1116 |
*ret = 0;
|
| 1117 |
break;
|
| 1118 |
|
| 1119 |
case 0x442: /* DMA_HW_ID */ |
| 1120 |
case 0x444: /* DMA_PCh2_ID */ |
| 1121 |
case 0x446: /* DMA_PCh0_ID */ |
| 1122 |
case 0x448: /* DMA_PCh1_ID */ |
| 1123 |
case 0x44a: /* DMA_PChG_ID */ |
| 1124 |
case 0x44c: /* DMA_PChD_ID */ |
| 1125 |
*ret = 1;
|
| 1126 |
break;
|
| 1127 |
|
| 1128 |
case 0x44e: /* DMA_CAPS_0_U */ |
| 1129 |
*ret = (1 << 3) | /* Constant Fill Capacity */ |
| 1130 |
(1 << 2); /* Transparent BLT Capacity */ |
| 1131 |
break;
|
| 1132 |
|
| 1133 |
case 0x450: /* DMA_CAPS_0_L */ |
| 1134 |
case 0x452: /* DMA_CAPS_1_U */ |
| 1135 |
*ret = 0;
|
| 1136 |
break;
|
| 1137 |
|
| 1138 |
case 0x454: /* DMA_CAPS_1_L */ |
| 1139 |
*ret = (1 << 1); /* 1-bit palletized capability */ |
| 1140 |
break;
|
| 1141 |
|
| 1142 |
case 0x456: /* DMA_CAPS_2 */ |
| 1143 |
*ret = (1 << 8) | /* SSDIC */ |
| 1144 |
(1 << 7) | /* DDIAC */ |
| 1145 |
(1 << 6) | /* DSIAC */ |
| 1146 |
(1 << 5) | /* DPIAC */ |
| 1147 |
(1 << 4) | /* DCAC */ |
| 1148 |
(1 << 3) | /* SDIAC */ |
| 1149 |
(1 << 2) | /* SSIAC */ |
| 1150 |
(1 << 1) | /* SPIAC */ |
| 1151 |
1; /* SCAC */ |
| 1152 |
break;
|
| 1153 |
|
| 1154 |
case 0x458: /* DMA_CAPS_3 */ |
| 1155 |
*ret = (1 << 5) | /* CCC */ |
| 1156 |
(1 << 4) | /* IC */ |
| 1157 |
(1 << 3) | /* ARC */ |
| 1158 |
(1 << 2) | /* AEC */ |
| 1159 |
(1 << 1) | /* FSC */ |
| 1160 |
1; /* ESC */ |
| 1161 |
break;
|
| 1162 |
|
| 1163 |
case 0x45a: /* DMA_CAPS_4 */ |
| 1164 |
*ret = (1 << 6) | /* SSC */ |
| 1165 |
(1 << 5) | /* BIC */ |
| 1166 |
(1 << 4) | /* LFIC */ |
| 1167 |
(1 << 3) | /* FIC */ |
| 1168 |
(1 << 2) | /* HFIC */ |
| 1169 |
(1 << 1) | /* EDIC */ |
| 1170 |
1; /* TOIC */ |
| 1171 |
break;
|
| 1172 |
|
| 1173 |
case 0x460: /* DMA_PCh2_SR */ |
| 1174 |
case 0x480: /* DMA_PCh0_SR */ |
| 1175 |
case 0x482: /* DMA_PCh1_SR */ |
| 1176 |
case 0x4c0: /* DMA_PChD_SR_0 */ |
| 1177 |
printf("%s: Physical Channel Status Registers not implemented.\n",
|
| 1178 |
__FUNCTION__); |
| 1179 |
*ret = 0xff;
|
| 1180 |
break;
|
| 1181 |
|
| 1182 |
default:
|
| 1183 |
return 1; |
| 1184 |
} |
| 1185 |
return 0; |
| 1186 |
} |
| 1187 |
|
| 1188 |
static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr) |
| 1189 |
{
|
| 1190 |
struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
| 1191 |
int reg, ch, offset = addr - s->base;
|
| 1192 |
uint16_t ret; |
| 1193 |
|
| 1194 |
switch (offset) {
|
| 1195 |
case 0x300 ... 0x3fe: |
| 1196 |
if (s->model == omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
|
| 1197 |
if (omap_dma_3_1_lcd_read(&s->lcd_ch, offset, &ret))
|
| 1198 |
break;
|
| 1199 |
return ret;
|
| 1200 |
} |
| 1201 |
/* Fall through. */
|
| 1202 |
case 0x000 ... 0x2fe: |
| 1203 |
reg = offset & 0x3f;
|
| 1204 |
ch = (offset >> 6) & 0x0f; |
| 1205 |
if (omap_dma_ch_reg_read(s, &s->ch[ch], reg, &ret))
|
| 1206 |
break;
|
| 1207 |
return ret;
|
| 1208 |
|
| 1209 |
case 0x404 ... 0x4fe: |
| 1210 |
if (s->model == omap_dma_3_1)
|
| 1211 |
break;
|
| 1212 |
/* Fall through. */
|
| 1213 |
case 0x400: |
| 1214 |
if (omap_dma_sys_read(s, offset, &ret))
|
| 1215 |
break;
|
| 1216 |
return ret;
|
| 1217 |
|
| 1218 |
case 0xb00 ... 0xbfe: |
| 1219 |
if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
|
| 1220 |
if (omap_dma_3_2_lcd_read(&s->lcd_ch, offset, &ret))
|
| 1221 |
break;
|
| 1222 |
return ret;
|
| 1223 |
} |
| 1224 |
break;
|
| 1225 |
} |
| 1226 |
|
| 1227 |
OMAP_BAD_REG(addr); |
| 1228 |
return 0; |
| 1229 |
} |
| 1230 |
|
| 1231 |
static void omap_dma_write(void *opaque, target_phys_addr_t addr, |
| 1232 |
uint32_t value) |
| 1233 |
{
|
| 1234 |
struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
| 1235 |
int reg, ch, offset = addr - s->base;
|
| 1236 |
|
| 1237 |
switch (offset) {
|
| 1238 |
case 0x300 ... 0x3fe: |
| 1239 |
if (s->model == omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
|
| 1240 |
if (omap_dma_3_1_lcd_write(&s->lcd_ch, offset, value))
|
| 1241 |
break;
|
| 1242 |
return;
|
| 1243 |
} |
| 1244 |
/* Fall through. */
|
| 1245 |
case 0x000 ... 0x2fe: |
| 1246 |
reg = offset & 0x3f;
|
| 1247 |
ch = (offset >> 6) & 0x0f; |
| 1248 |
if (omap_dma_ch_reg_write(s, &s->ch[ch], reg, value))
|
| 1249 |
break;
|
| 1250 |
return;
|
| 1251 |
|
| 1252 |
case 0x404 ... 0x4fe: |
| 1253 |
if (s->model == omap_dma_3_1)
|
| 1254 |
break;
|
| 1255 |
case 0x400: |
| 1256 |
/* Fall through. */
|
| 1257 |
if (omap_dma_sys_write(s, offset, value))
|
| 1258 |
break;
|
| 1259 |
return;
|
| 1260 |
|
| 1261 |
case 0xb00 ... 0xbfe: |
| 1262 |
if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
|
| 1263 |
if (omap_dma_3_2_lcd_write(&s->lcd_ch, offset, value))
|
| 1264 |
break;
|
| 1265 |
return;
|
| 1266 |
} |
| 1267 |
break;
|
| 1268 |
} |
| 1269 |
|
| 1270 |
OMAP_BAD_REG(addr); |
| 1271 |
} |
| 1272 |
|
| 1273 |
static CPUReadMemoryFunc *omap_dma_readfn[] = {
|
| 1274 |
omap_badwidth_read16, |
| 1275 |
omap_dma_read, |
| 1276 |
omap_badwidth_read16, |
| 1277 |
}; |
| 1278 |
|
| 1279 |
static CPUWriteMemoryFunc *omap_dma_writefn[] = {
|
| 1280 |
omap_badwidth_write16, |
| 1281 |
omap_dma_write, |
| 1282 |
omap_badwidth_write16, |
| 1283 |
}; |
| 1284 |
|
| 1285 |
static void omap_dma_request(void *opaque, int drq, int req) |
| 1286 |
{
|
| 1287 |
struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
| 1288 |
/* The request pins are level triggered. */
|
| 1289 |
if (req) {
|
| 1290 |
if (~s->drq & (1 << drq)) { |
| 1291 |
s->drq |= 1 << drq;
|
| 1292 |
omap_dma_process_request(s, drq); |
| 1293 |
} |
| 1294 |
} else
|
| 1295 |
s->drq &= ~(1 << drq);
|
| 1296 |
} |
| 1297 |
|
| 1298 |
static void omap_dma_clk_update(void *opaque, int line, int on) |
| 1299 |
{
|
| 1300 |
struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
| 1301 |
|
| 1302 |
if (on) {
|
| 1303 |
/* TODO: make a clever calculation */
|
| 1304 |
s->delay = ticks_per_sec >> 8;
|
| 1305 |
if (s->run_count)
|
| 1306 |
qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay); |
| 1307 |
} else {
|
| 1308 |
s->delay = 0;
|
| 1309 |
qemu_del_timer(s->tm); |
| 1310 |
} |
| 1311 |
} |
| 1312 |
|
| 1313 |
struct omap_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
|
| 1314 |
qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
|
| 1315 |
enum omap_dma_model model)
|
| 1316 |
{
|
| 1317 |
int iomemtype, num_irqs, memsize, i;
|
| 1318 |
struct omap_dma_s *s = (struct omap_dma_s *) |
| 1319 |
qemu_mallocz(sizeof(struct omap_dma_s)); |
| 1320 |
|
| 1321 |
if (model == omap_dma_3_1) {
|
| 1322 |
num_irqs = 6;
|
| 1323 |
memsize = 0x800;
|
| 1324 |
} else {
|
| 1325 |
num_irqs = 16;
|
| 1326 |
memsize = 0xc00;
|
| 1327 |
} |
| 1328 |
s->base = base; |
| 1329 |
s->model = model; |
| 1330 |
s->mpu = mpu; |
| 1331 |
s->clk = clk; |
| 1332 |
s->lcd_ch.irq = lcd_irq; |
| 1333 |
s->lcd_ch.mpu = mpu; |
| 1334 |
while (num_irqs --)
|
| 1335 |
s->ch[num_irqs].irq = irqs[num_irqs]; |
| 1336 |
for (i = 0; i < 3; i ++) { |
| 1337 |
s->ch[i].sibling = &s->ch[i + 6];
|
| 1338 |
s->ch[i + 6].sibling = &s->ch[i];
|
| 1339 |
} |
| 1340 |
s->tm = qemu_new_timer(vm_clock, (QEMUTimerCB *) omap_dma_channel_run, s); |
| 1341 |
omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]); |
| 1342 |
mpu->drq = qemu_allocate_irqs(omap_dma_request, s, 32);
|
| 1343 |
omap_dma_reset(s); |
| 1344 |
omap_dma_clk_update(s, 0, 1); |
| 1345 |
|
| 1346 |
iomemtype = cpu_register_io_memory(0, omap_dma_readfn,
|
| 1347 |
omap_dma_writefn, s); |
| 1348 |
cpu_register_physical_memory(s->base, memsize, iomemtype); |
| 1349 |
|
| 1350 |
return s;
|
| 1351 |
} |
| 1352 |
|
| 1353 |
struct omap_dma_lcd_channel_s *omap_dma_get_lcdch(struct omap_dma_s *s) |
| 1354 |
{
|
| 1355 |
return &s->lcd_ch;
|
| 1356 |
} |