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target-arm: Drop success/fail return from cpreg read and write functions
All cpreg read and write functions now return 0, so we can clean uptheir prototypes: * write functions return void * read functions return the value rather than taking a pointer to write the value to...
target-arm: Convert generic timer reginfo to accessfn
Convert the reginfo structs for the generic timer registersto use access functions rather than returning EXCP_UDEF fromtheir read handlers. In some cases this allows us to removea read handler completely....
target-arm: Convert miscellaneous reginfo structs to accessfn
Convert the remaining miscellaneous cases of reginfo read/writefunctions returning EXCP_UDEF to use an accessfn instead:TEEHBR, and the ATS address-translation operations.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Stop underdecoding ARM946 PRBS registers
The ARM946 has 8 PRBS (protection region base and size) registers.Currently we implement these with a CP_ANY reginfo; however thisunderdecodes (since there are 16 possible values of CRm but only8 registers) and we catch the invalid values in the read and...
target-arm: Convert performance monitor reginfo to accessfn
Convert the performance monitor reginfo definitions to usean accessfn rather than returning EXCP_UDEF from read andwrite functions. This also allows us to fix a couple of XXXcases where we weren't imposing the access restrictions on...
target-arm: Define names for SCTLR bits
The SCTLR is full of bits for enabling or disabling various things, and sothere are many places in the code which check if certain bits are set.Define some named constants for the SCTLR bits so these checks are easier...
target-arm: Restrict check_ap() use of S and R bits to v6 and earlier
The SCTLR bits S and R (8 and 9) only exist in ARMv6 and earlier.In ARMv7 these bits RAZ, and in ARMv8 they are reassigned. Guardthe use of them in check_ap() so that we don't get incorrect results...
exec: Make stl_*_phys input an AddressSpace
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
exec: Make ldq/ldub_*_phys input an AddressSpace
exec: Make ldl_*_phys input an AddressSpace
target-arm: Add set_neon_rmode helper
This helper sets the rounding mode in the standard_fp_status word toallow NEON instructions to modify the rounding mode whilst using thestandard FPSCR values for everything else.
Signed-off-by: Will Newton <will.newton@linaro.org>...
target-arm: Move arm_rmode_to_sf to a shared location.
This function will be needed for AArch32 ARMv8 support, so move it tohelper.c where it can be used by both targets. Also moves the code outof line, but as it is quite a large function I don't believe this...
target-arm: A64: Add floating-point<->fixed-point instructions
This patch adds emulation for the instruction group labeled"Floating-point <-> fixed-point conversions" in the ARM ARM.
Namely this includes the instructions SCVTF, UCVTF, FCVTZS, FCVTZU(scalar, fixed-point)....
target-arm: A64: Add 1-source 32-to-32 and 64-to-64 FP instructions
This patch adds support for those instructions in the "Floating-pointdata-processing (1 source)" group which are simple 32-bit-to-32-bitor 64-bit-to-64-bit operations (ie everything except FCVT between...
target-arm: A64: Add support for FCVT between half, single and double
Add support for FCVT between half, single and double precision.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Richard Henderson <rth@twiddle.net>
target-arm: Prepare VFP_CONV_FIX helpers for A64 uses
Make the VFP_CONV_FIX helpers a little more flexible inpreparation for the A64 uses. This requires two changes: * use the correct softfloat conversion function based on itype rather than always the int32 one; this is possible now that...
target-arm: Rename A32 VFP conversion helpers
The VFP conversion helpers for A32 round to zero as this is the onlyrounding mode supported. Rename these helpers to make it clear thatthey round to zero and are not suitable for use in the AArch64 code.
target-arm: Ignore most exceptions from scalbn when doing fixpoint conversion
The VFP fixed point conversion helpers first call float_scalbn andthen convert the result to an integer. This scalbn operation mayset floating point exception flags for: * overflow & inexact (if it overflows to infinity)...
target-arm: A64: Add extra VFP fixed point conversion helpers
Define the full set of floating point to fixed point conversionhelpers required to support AArch64.
Signed-off-by: Will Newton <will.newton@linaro.org>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: Use VFP_BINOP macro for min, max, minnum, maxnum
Use the VFP_BINOP macro to provide helpers for min, max, minnumand maxnum, rather than hand-rolling them. (The float64 maxversion is not used by A32 but will be needed for A64.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: Give the FPSCR rounding modes names
When setting rounding modes we currently just hardcode the numeric valuesfor rounding modes in a big switch statement.
With AArch64 support coming, we will need to refer to these rounding modesat different places throughout the code though, so let's better give them...
target-arm: use c13_context field for CONTEXTIDR
Use c13_context field instead of c13_fcse for CONTEXTIDR registerdefinition.
Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com>Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: remove raw_read|write duplication
There is an inline duplication of the raw_read and raw_write functionbodies. Fix by just calling raw_read/raw_write instead.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: A64: Implement minimal set of EL0-visible sysregs
Implement an initial minimal set of EL0-visible system registers: * NZCV * FPCR * FPSR * CTR_EL0 * DCZID_EL0
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Richard Henderson <rth@twiddle.net>...
target-arm: Widen thread-local register state fields to 64 bits
The common pattern for system registers in a 64-bit capable ARMCPU is that when in AArch32 the cp15 register is a view of thebottom 32 bits of the 64-bit AArch64 system register; writes in...
target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoder
The cpregs APIs used by the decoder (get_arm_cp_reginfo() andcp_access_ok()) currently take either a CPUARMState* or an ARMCPU*.This is problematic for the A64 decoder, which doesn't pass the...
target-arm: Pull "add one cpreg to hashtable" into its own function
define_one_arm_cp_reg_with_opaque() has a set of nested loops whichinsert a cpreg entry into the hashtable for each of the possibleopc/crn/crm values allowed by wildcard specifications. We're about...
target-arm: Update generic cpreg code for AArch64
Update the generic cpreg support code to also handle AArch64:AArch64-visible registers coexist in the same hash table withAArch32-visible ones, with a bit in the hash key distinguishingthem.
target-arm: Support fp registers in gdb stub
Register the aarch64-fpu XML and implement the necessaryread/write handlers so we can support reading and writingof FP registers in the gdb stub.
target-arm: Define and use ARM_FEATURE_CBAR
Some processors (notably A9 within Highbank) define and use theCP15 configuration base address (CBAR). This is vendor specificso its best implemented as a CPU property (otherwise we would needvendor specific child classes for every ARM implementation)....
target-arm/helper.c: Allow cp15.c15 dummy override
The cp15.c15 space is implementation defined. Currently there is adummy placeholder register RAZing it. Allow overriding of this RAZso implementations of specific registers can take precedence.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>...
target-arm: Implement ARMv8 FP VMAXNM and VMINNM instructions.
This adds support for the ARMv8 floating point VMAXNM and VMINNMinstructions.
Signed-off-by: Will Newton <will.newton@linaro.org>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Message-id: 1386158099-9239-6-git-send-email-will.newton@linaro.org...
target-arm: fix TTBCR write masking
Current implementation is not accurate according to ARMv7-AR referencemanual. See "B4.1.153 TTBCR, Translation Table Base Control Register,VMSA | TTBCR format when using the Long-descriptor translation tableformat". When LPAE feature is supported, EAE, bit31 selects...
target-arm: Provide '-cpu host' when running KVM
Implement '-cpu host' for ARM when we're using KVM, broadlyin line with other KVM-supporting architectures.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>...
target-arm: Add CP15 VBAR support
Added Vector Base Address remapping on ARM v7.
Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com>Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>[PMM: removed spurious mask of value with 1<<31]Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: sort TCG cpreg list by KVM-style 64 bit ID number
Both KVM and TCG populate the cpreg_list with 64 bit register IDs,but in the TCG side the cpreg_list is sorted using the 32 bit IDversion while in the kvm side the 64 bit ID version is used. This...
cpu: Drop cpu_model_str from CPU_COMMON
Since this is only read in cpu_copy() and linux-user has a globalcpu_model, drop the field from generic code.
Signed-off-by: Andreas Färber <afaerber@suse.de>
target-arm: Implement qmp query-cpu-definitions
Libvirt uses this to introspect available CPU models.
Signed-off-by: Cole Robinson <crobinso@redhat.com>Reviewed-by: Andreas Färber <afaerber@suse.de>Message-id: c0bdcd6c7ea6a085a6902ccaa73180fd771c8267.1378303555.git.crobinso@redhat.com...
target-arm: Avoid "1 << 31" undefined behaviour
Avoid the undefined behaviour of "1 << 31" by using 1U to makethe shift be of an unsigned value rather than shifting into thesign bit of a signed integer. For consistency, we make all theCPSR_* constants unsigned, though the only one which triggers...
aio / timers: Switch entire codebase to the new timer API
This is an autogenerated patch using scripts/switch-timer-api.
Switch the entire code base to using the new timer API.
Note this patch may introduce some line length issues.
Signed-off-by: Alex Bligh <alex@alex.org.uk>...
target-arm: Allow raw_read() and raw_write() to handle 64 bit regs
Extend the raw_read() and raw_write() helper accessors so thatthey can be used for 64 bit registers as well as 32 bit registers.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>...
target-arm: Implement the generic timer
The ARMv7 architecture specifies a 'generic timer' which is implementedvia cp15 registers. Newer kernels will prefer to use this rather thana devboard-level timer. Implement the generic timer for TCG; for KVMwe will already use the hardware's virtualized timer for this....
target-arm: Implement 'int' loglevel
The 'int' loglevel for recording interrupts and exceptionsrequires support in the target-specific code. Implementit for ARM. This improves debug logging in some situationsthat were otherwise pretty opaque, such as when we fault...
misc: Use g_assert_not_reached for code which is expected to be unreachable
The macro g_assert_not_reached is a better self documenting replacementfor assert(0) or assert(false).
Signed-off-by: Stefan Weil <sw@weilnetz.de>Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
cpu: Turn cpu_get_phys_page_debug() into a CPUClass hook
Change breakpoint_invalidate() argument to CPUState alongside.
Since all targets now assign a softmmu-only field, we can drop helperscpu_class_set_{do_unassigned_access,vmsd}() and device_class_set_vmsd()....
gdbstub: Change gdb_register_coprocessor() argument to CPUState
target-arm/helper.c: OMAP/StrongARM cp15 crn=0 cleanup
The if block detecting OMAP/StrongARM modifies the id_cp_reginfo.access fields in place. So there is no need to replicate the callto define_arm_cp_reg(). Dropped, and let the OMAP case fall through...
target-arm/helper.c: Implement MIDR aliases
Unimplemented registers in the cp15, CRn=0, opc1=0, CRm=0 space defaultto aliasing the MIDR register. Set all registers in the space to accessMIDR by default.
target-arm/helper.c: Allow const opaques in arm CP
Allow for defining const opaque data in ARM CP register definitions bysetting .opaque = foo. If non null opaque is passed intodefine_one_arm_cp_reg_with_opaque then that opaque will takeprecedence, otherwise if null opaque is passed, the original opaque...
target-arm: avoid undefined behaviour when writing TTBCR
LPAE CPUs have more potentially valid bits in the TTBCR, and so thesimple masking out of invalid bits is no longer sufficient to obtainthe base address width field of the register, which is what we use to...
target-arm: Avoid g_hash_table_get_keys()
g_hash_table_get_keys() was only introduced in glib 2.14, and we'restill targeting a minimum version of 2.12. Rewrite the offendingcode (introduced in commit 721fae1) to use g_hash_table_foreach()to build the list of keys....
target-arm: Convert TCG to using (index,value) list for cp migration
Convert the TCG ARM target to using an (index,value) list for migratingcoprocessors. The primary benefit of the (index,value) list is forpassing state between KVM and QEMU, but it works for TCG-to-TCG...
target-arm: Add raw_readfn and raw_writefn to ARMCPRegInfo
For reading and writing register values from the kernel for KVM,we need to provide accessor functions which are guaranteed to succeedand don't impose access checks, mask out unwritable bits, etc....
target-arm: mark up cpregs for no-migrate or raw access
Mark up coprocessor register definitions to add raw accessfunctions or mark the register as non-migratable where necessary.
cpu: Move halted and interrupt_request fields to CPUState
Both fields are used in VMState, thus need to be moved together.Explicitly zero them on reset since they were located beforebreakpoints.
Pass PowerPCCPU to kvmppc_handle_halt().
cpu: Pass CPUState to cpu_interrupt()
Move it to qom/cpu.h to avoid issues with include order.
Change pc_acpi_smi_interrupt() opaque to X86CPU.
cpu: Replace do_interrupt() by CPUClass::do_interrupt method
This removes a global per-target function and thus takes us one stepcloser to compiling multiple targets into one executable.
It will also allow to override the interrupt handling for certain CPU...
target-arm: Override do_interrupt for ARMv7-M profile
Enable ARMCPUInfo to specify a custom class_init functions.Introduce arm_v7m_class_init() and use it for "cortex-m3" model.
Instead of forwarding from arm_cpu_do_interrupt() to do_interrupt_v7m(),override CPUClass::do_interrupt with arm_v7m_cpu_do_interrupt()...
ARM: KVM: Add support for KVM on ARM architecture
Add basic support for KVM on ARM architecture.
Signed-off-by: Christoffer Dall <cdall@cs.columbia.edu>[PMM: Minor tweaks and code cleanup, switch to ONE_REG]Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: Drop CPUARMState* argument from bank_number()
Drop the CPUARMState* argument from bank_number(), since we onlyuse it for passing to cpu_abort(). Use hw_error() instead.This avoids propagating further interfaces using env pointers.
In the long term this function's callers need auditing to fix...
target-arm: Use mul[us]2 and add2 in umlal et al
Cc: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-arm: Move TCG initialization to ARMCPU initfn
Ensures that a QOM-created ARMCPU is usable.
target-arm: Update ARMCPU to QOM realizefn
Turn arm_cpu_realize() into a QOM realize function, no longer calledvia cpu.h prototype. To maintain the semantics of cpu_init(), setrealized = true explicitly in cpu_arm_init().
Move GDB coprocessor registration, CPU reset and vCPU initialization...
target-arm: Rename CPU types
In the initial conversion of CPU models to QOM types, model names weremapped 1:1 to type names. As a side effect this gained us a type "any",which is now a device.
To avoid "-device any" silliness and to pave the way for compiling...
target-arm: Detect attempt to instantiate non-CPU type in cpu_init()
Consolidate model checking into a new arm_cpu_class_by_name().
If the name matches an existing type, also check whether that type isactually (a sub-type of) TYPE_ARM_CPU.
This fixes, e.g., -cpu tmp105 asserting....
cpu: Move cpu_index field to CPUState
Note that target-alpha accesses this field from TCG, now using anegative offset. Therefore the field is placed last in CPUState.
Pass PowerPCCPU to [kvm]ppc_fixup_cpu() to facilitate this change.
Move common parts of mips cpu_state_reset() to mips_cpu_reset()....
target-arm: Fix SWI (SVC) instruction in M profile.
When do_interrupt_v7m is called with EXCP_SWI, the PC alreadypoints to the next instruction. Don't modify it here.
Signed-off-by: Alex Rozenman <Alex_Rozenman@mentor.com>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Merge branch 'master' of git://git.qemu.org/qemu into qom-cpu
Adapt header include paths.
cpu: Introduce CPUListState struct
This generalizes {ARM,M68k,Alpha}CPUListState to avoid declaring it foreach target. Place it in cpu-common.h to avoid circular dependencies.
Signed-off-by: Andreas Färber <afaerber@suse.de>Reviewed-by: Igor Mammedov <imammedo@redhat.com>...
softmmu: move include files to include/sysemu/
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
misc: move include files to include/qemu/
exec: move include files to include/exec/
target-arm: Implement abs_i32 inline rather than as a helper
Implement abs_i32 inline (with movcond) rather than using a helperfunction.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Rename target_phys_addr_t to hwaddr
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes arereserved) and its purpose doesn't match the name (most target_phys_addr_taddresses are not target specific). Replace it with a finger-friendly,...
target-arm: final conversion to AREG0 free mode
Convert code load functions and switch to AREG0 free mode.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Fix potential buffer overflow
Report from smatch:
target-arm/helper.c:651 arm946_prbs_read(6) error: buffer overflow 'env->cp15.c6_region' 8 <= 8target-arm/helper.c:661 arm946_prbs_write(6) error: buffer overflow 'env->cp15.c6_region' 8 <= 8...
target-arm: Fix typos in comments
Fix a variety of typos in comments in target-arm files.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Peter Crosthwaite <peter.crosthwaite@petalogix.com>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
target-arm: Implement privileged-execute-never (PXN)
Implement the privileged-execute-never (PXN) translation table bit.It is implementation-defined whether this is implemented, so we giveit its own ARM_FEATURE_ flag. LPAE requires PXN, so add also anLPAE feature flag and the implication logic, as a placeholder...
target-arm: Add AMAIR0, AMAIR1 LPAE cp15 registers
Add implementations of the AMAIR0 and AMAIR1 LPAEAuxiliary Memory Attribute Indirection Registers.These are implementation defined and we choose toimplement them as RAZ/WI, matching the Cortex-A7and Cortex-A15....
target-arm: Add 64 bit variants of DBGDRAR and DBGDSAR for LPAE
LPAE extends the DBGDRAR and DBGDSAR debug registers to 64 bits; weonly implement these as dummy RAZ versions; provide dummies forthe 64 bit accesses as well.
target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAE
Under LPAE, the cp15 registers PAR, TTBR0 and TTBR1 are extendedto 64 bits, with a 64 bit (MRRC/MCRR) access path to read thefull width of the register. Add the state fields for the tophalf and the 64 bit access path. Actual use of the top half of...
target-arm: Use target_phys_addr_t in get_phys_addr()
In the implementation of get_phys_addr(), consistently usetarget_phys_addr_t to hold the physical address rather thanuint32_t.
target-arm: Implement long-descriptor PAR format
Implement the different format of the PAR when long descriptortranslation tables are in use. Note that we assume thatget_phys_addr() returns a long-descriptor format DFSR value onfailure if long descriptors are in use; this added subtlety tips...
target-arm: Implement TTBCR changes for LPAE
Implement the changes to the TTBCR register required for LPAE: * many fewer bits should be RAZ/WI * since TTBCR changes can result in a change of ASID, we must flush the TLB on writes to it
target-arm: Add support for long format translation table walks
Implement the actual table walk code for LPAE's long formattranslation tables.
target-arm: Fix typo that meant TTBR1 accesses went to TTBR0
Fix a copy-and-paste error in the register description for TTBR1that meant it was a duplicate of TTBR0 rather than affecting thecorrect bit of CPU state.
target-arm: Fix some copy-and-paste errors in cp register names
Fix a couple of cases where cp register names were copy-and-pasted.These are harmless since we don't use the name for anything (exceptdebugging convenience) but could be confusing.
target-arm: Remove remaining old cp15 infrastructure
There are now no uses of the old cp15 infrastructure,so it can be deleted.
target-arm: Move block cache ops to new cp15 framework
Move the v6 optional block cache ops to the new cp15 framework.This includes only providing them on the CPUs which implementedthem, rather than the previous blunderbuss approach of makingall MCRR instructions on all CPUs act as NOPs....
target-arm: Convert final ID registers
Convert the final ID registers to the new cp15 scheme.
target-arm: Convert MPIDR
Convert the MPIDR to the new cp15 register scheme.This includes giving it its own feature bit ratherthan doing a CPUID value check.
target-arm: Convert cp15 cache ID registers
Convert the cp15 cache ID registers to the new scheme.
target-arm: Convert cp15 crn=0 crm={1,2} feature registers
Convert the cp15 crn=0 crm={1,2} features registers tothe new cp reg framework.
target-arm: Convert cp15 crn=1 registers
Convert the cp15 crn=1 registers to the new scheme.
target-arm: Convert cp15 crn=9 registers
Convert cp15 crn=9 registers (mostly cache lockdown) to the new scheme.
Note that this change makes OMAPCP cores RAZ/WI the whole c9 space. This isa change from previous behaviour, but a return to the behaviour of commit...
target-arm: Convert cp15 crn=6 registers
Convert the cp15 crn=6 registers to the new scheme.Note that this includes some minor tidyup: drop an unnecessaryunderdecoding of op2 on OMAPCP cores, and only implement thepre-v6 c6,c0,0,1 IFAR on the 1026 and not on the other ARMv5...
target-arm: convert cp15 crn=7 registers
Convert the cp15 crn=7 registers to the new scheme.Note that to do this we have to distinguish some registersused on the ARM9 and ARM10 from some which are ARM1176only. This is because the old code returned a value of 0...
target-arm: Convert cp15 VA-PA translation registers
Convert the cp15 VA-PA translation registers (a subset ofthe crn=7 regs) to the new scheme.
target-arm: Convert cp15 MMU TLB control
Convert cp15 MMU TLB control (crn=8) to new scheme.
target-arm: Convert cp15 crn=15 registers
Convert the cp15 crn=15 (implementation specific) registersto the new scheme.