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1 | 420557e8 | bellard | /*
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2 | 420557e8 | bellard | * QEMU Sun4m System Emulator
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3 | 420557e8 | bellard | *
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4 | b81b3b10 | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
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5 | 420557e8 | bellard | *
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6 | 420557e8 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 420557e8 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 420557e8 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 420557e8 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 420557e8 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 420557e8 | bellard | * furnished to do so, subject to the following conditions:
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12 | 420557e8 | bellard | *
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13 | 420557e8 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 420557e8 | bellard | * all copies or substantial portions of the Software.
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15 | 420557e8 | bellard | *
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16 | 420557e8 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 420557e8 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 420557e8 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 420557e8 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 420557e8 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 420557e8 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 420557e8 | bellard | * THE SOFTWARE.
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23 | 420557e8 | bellard | */
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24 | 420557e8 | bellard | #include "vl.h" |
25 | 420557e8 | bellard | |
26 | 420557e8 | bellard | #define KERNEL_LOAD_ADDR 0x00004000 |
27 | b6f479d3 | bellard | #define CMDLINE_ADDR 0x007ff000 |
28 | 713c45fa | bellard | #define INITRD_LOAD_ADDR 0x00800000 |
29 | b3783731 | bellard | #define PROM_SIZE_MAX (256 * 1024) |
30 | e80cfcfc | bellard | #define PROM_ADDR 0xffd00000 |
31 | 0986ac3b | bellard | #define PROM_FILENAME "openbios-sparc32" |
32 | e80cfcfc | bellard | #define PHYS_JJ_EEPROM 0x71200000 /* m48t08 */ |
33 | 420557e8 | bellard | #define PHYS_JJ_IDPROM_OFF 0x1FD8 |
34 | 420557e8 | bellard | #define PHYS_JJ_EEPROM_SIZE 0x2000 |
35 | e80cfcfc | bellard | // IRQs are not PIL ones, but master interrupt controller register
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36 | e80cfcfc | bellard | // bits
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37 | e80cfcfc | bellard | #define PHYS_JJ_IOMMU 0x10000000 /* I/O MMU */ |
38 | 6f7e9aec | bellard | #define PHYS_JJ_TCX_FB 0x50000000 /* TCX frame buffer */ |
39 | 3475187d | bellard | #define PHYS_JJ_SLAVIO 0x70000000 /* Slavio base */ |
40 | 67e999be | bellard | #define PHYS_JJ_DMA 0x78400000 /* DMA controller */ |
41 | 6f7e9aec | bellard | #define PHYS_JJ_ESP 0x78800000 /* ESP SCSI */ |
42 | 6f7e9aec | bellard | #define PHYS_JJ_ESP_IRQ 18 |
43 | e80cfcfc | bellard | #define PHYS_JJ_LE 0x78C00000 /* Lance ethernet */ |
44 | e80cfcfc | bellard | #define PHYS_JJ_LE_IRQ 16 |
45 | e80cfcfc | bellard | #define PHYS_JJ_CLOCK 0x71D00000 /* Per-CPU timer/counter, L14 */ |
46 | e80cfcfc | bellard | #define PHYS_JJ_CLOCK_IRQ 7 |
47 | e80cfcfc | bellard | #define PHYS_JJ_CLOCK1 0x71D10000 /* System timer/counter, L10 */ |
48 | e80cfcfc | bellard | #define PHYS_JJ_CLOCK1_IRQ 19 |
49 | e80cfcfc | bellard | #define PHYS_JJ_INTR0 0x71E00000 /* Per-CPU interrupt control registers */ |
50 | 8d5f07fa | bellard | #define PHYS_JJ_INTR_G 0x71E10000 /* Master interrupt control registers */ |
51 | e80cfcfc | bellard | #define PHYS_JJ_MS_KBD 0x71000000 /* Mouse and keyboard */ |
52 | e80cfcfc | bellard | #define PHYS_JJ_MS_KBD_IRQ 14 |
53 | e80cfcfc | bellard | #define PHYS_JJ_SER 0x71100000 /* Serial */ |
54 | e80cfcfc | bellard | #define PHYS_JJ_SER_IRQ 15 |
55 | e80cfcfc | bellard | #define PHYS_JJ_FDC 0x71400000 /* Floppy */ |
56 | e80cfcfc | bellard | #define PHYS_JJ_FLOPPY_IRQ 22 |
57 | 3475187d | bellard | #define PHYS_JJ_ME_IRQ 30 /* Module error, power fail */ |
58 | b8174937 | bellard | #define PHYS_JJ_CS 0x6c000000 /* Crystal CS4231 */ |
59 | b8174937 | bellard | #define PHYS_JJ_CS_IRQ 5 |
60 | b8174937 | bellard | |
61 | ba3c64fb | bellard | #define MAX_CPUS 16 |
62 | 420557e8 | bellard | |
63 | 420557e8 | bellard | /* TSC handling */
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64 | 420557e8 | bellard | |
65 | 420557e8 | bellard | uint64_t cpu_get_tsc() |
66 | 420557e8 | bellard | { |
67 | 420557e8 | bellard | return qemu_get_clock(vm_clock);
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68 | 420557e8 | bellard | } |
69 | 420557e8 | bellard | |
70 | 6f7e9aec | bellard | int DMA_get_channel_mode (int nchan) |
71 | 6f7e9aec | bellard | { |
72 | 6f7e9aec | bellard | return 0; |
73 | 6f7e9aec | bellard | } |
74 | 6f7e9aec | bellard | int DMA_read_memory (int nchan, void *buf, int pos, int size) |
75 | 6f7e9aec | bellard | { |
76 | 6f7e9aec | bellard | return 0; |
77 | 6f7e9aec | bellard | } |
78 | 6f7e9aec | bellard | int DMA_write_memory (int nchan, void *buf, int pos, int size) |
79 | 6f7e9aec | bellard | { |
80 | 6f7e9aec | bellard | return 0; |
81 | 6f7e9aec | bellard | } |
82 | 6f7e9aec | bellard | void DMA_hold_DREQ (int nchan) {} |
83 | 6f7e9aec | bellard | void DMA_release_DREQ (int nchan) {} |
84 | 6f7e9aec | bellard | void DMA_schedule(int nchan) {} |
85 | 6f7e9aec | bellard | void DMA_run (void) {} |
86 | 6f7e9aec | bellard | void DMA_init (int high_page_enable) {} |
87 | 6f7e9aec | bellard | void DMA_register_channel (int nchan, |
88 | 6f7e9aec | bellard | DMA_transfer_handler transfer_handler, |
89 | 6f7e9aec | bellard | void *opaque)
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90 | 6f7e9aec | bellard | { |
91 | 6f7e9aec | bellard | } |
92 | 6f7e9aec | bellard | |
93 | 819385c5 | bellard | static void nvram_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value) |
94 | 6f7e9aec | bellard | { |
95 | 819385c5 | bellard | m48t59_write(nvram, addr++, (value >> 8) & 0xff); |
96 | 819385c5 | bellard | m48t59_write(nvram, addr++, value & 0xff);
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97 | 6f7e9aec | bellard | } |
98 | 6f7e9aec | bellard | |
99 | 819385c5 | bellard | static void nvram_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value) |
100 | 6f7e9aec | bellard | { |
101 | 819385c5 | bellard | m48t59_write(nvram, addr++, value >> 24);
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102 | 819385c5 | bellard | m48t59_write(nvram, addr++, (value >> 16) & 0xff); |
103 | 819385c5 | bellard | m48t59_write(nvram, addr++, (value >> 8) & 0xff); |
104 | 819385c5 | bellard | m48t59_write(nvram, addr++, value & 0xff);
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105 | 6f7e9aec | bellard | } |
106 | 6f7e9aec | bellard | |
107 | 819385c5 | bellard | static void nvram_set_string (m48t59_t *nvram, uint32_t addr, |
108 | 6f7e9aec | bellard | const unsigned char *str, uint32_t max) |
109 | 6f7e9aec | bellard | { |
110 | 6f7e9aec | bellard | unsigned int i; |
111 | 6f7e9aec | bellard | |
112 | 6f7e9aec | bellard | for (i = 0; i < max && str[i] != '\0'; i++) { |
113 | 819385c5 | bellard | m48t59_write(nvram, addr + i, str[i]); |
114 | 6f7e9aec | bellard | } |
115 | 819385c5 | bellard | m48t59_write(nvram, addr + max - 1, '\0'); |
116 | 6f7e9aec | bellard | } |
117 | 420557e8 | bellard | |
118 | 819385c5 | bellard | static m48t59_t *nvram;
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119 | 420557e8 | bellard | |
120 | 6f7e9aec | bellard | extern int nographic; |
121 | 6f7e9aec | bellard | |
122 | 819385c5 | bellard | static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline, |
123 | 6f7e9aec | bellard | int boot_device, uint32_t RAM_size,
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124 | 6f7e9aec | bellard | uint32_t kernel_size, |
125 | 6f7e9aec | bellard | int width, int height, int depth) |
126 | e80cfcfc | bellard | { |
127 | e80cfcfc | bellard | unsigned char tmp = 0; |
128 | e80cfcfc | bellard | int i, j;
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129 | e80cfcfc | bellard | |
130 | 6f7e9aec | bellard | // Try to match PPC NVRAM
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131 | 6f7e9aec | bellard | nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16); |
132 | 6f7e9aec | bellard | nvram_set_lword(nvram, 0x10, 0x00000001); /* structure v1 */ |
133 | 6f7e9aec | bellard | // NVRAM_size, arch not applicable
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134 | ba3c64fb | bellard | m48t59_write(nvram, 0x2D, smp_cpus & 0xff); |
135 | ba3c64fb | bellard | m48t59_write(nvram, 0x2E, 0); |
136 | 819385c5 | bellard | m48t59_write(nvram, 0x2F, nographic & 0xff); |
137 | 6f7e9aec | bellard | nvram_set_lword(nvram, 0x30, RAM_size);
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138 | 819385c5 | bellard | m48t59_write(nvram, 0x34, boot_device & 0xff); |
139 | 6f7e9aec | bellard | nvram_set_lword(nvram, 0x38, KERNEL_LOAD_ADDR);
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140 | 6f7e9aec | bellard | nvram_set_lword(nvram, 0x3C, kernel_size);
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141 | b6f479d3 | bellard | if (cmdline) {
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142 | b6f479d3 | bellard | strcpy(phys_ram_base + CMDLINE_ADDR, cmdline); |
143 | 6f7e9aec | bellard | nvram_set_lword(nvram, 0x40, CMDLINE_ADDR);
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144 | 6f7e9aec | bellard | nvram_set_lword(nvram, 0x44, strlen(cmdline));
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145 | b6f479d3 | bellard | } |
146 | 6f7e9aec | bellard | // initrd_image, initrd_size passed differently
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147 | 6f7e9aec | bellard | nvram_set_word(nvram, 0x54, width);
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148 | 6f7e9aec | bellard | nvram_set_word(nvram, 0x56, height);
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149 | 6f7e9aec | bellard | nvram_set_word(nvram, 0x58, depth);
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150 | b6f479d3 | bellard | |
151 | 6f7e9aec | bellard | // Sun4m specific use
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152 | e80cfcfc | bellard | i = 0x1fd8;
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153 | 819385c5 | bellard | m48t59_write(nvram, i++, 0x01);
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154 | 819385c5 | bellard | m48t59_write(nvram, i++, 0x80); /* Sun4m OBP */ |
155 | e80cfcfc | bellard | j = 0;
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156 | 819385c5 | bellard | m48t59_write(nvram, i++, macaddr[j++]); |
157 | 819385c5 | bellard | m48t59_write(nvram, i++, macaddr[j++]); |
158 | 819385c5 | bellard | m48t59_write(nvram, i++, macaddr[j++]); |
159 | 819385c5 | bellard | m48t59_write(nvram, i++, macaddr[j++]); |
160 | 819385c5 | bellard | m48t59_write(nvram, i++, macaddr[j++]); |
161 | 819385c5 | bellard | m48t59_write(nvram, i, macaddr[j]); |
162 | e80cfcfc | bellard | |
163 | e80cfcfc | bellard | /* Calculate checksum */
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164 | e80cfcfc | bellard | for (i = 0x1fd8; i < 0x1fe7; i++) { |
165 | 819385c5 | bellard | tmp ^= m48t59_read(nvram, i); |
166 | e80cfcfc | bellard | } |
167 | 819385c5 | bellard | m48t59_write(nvram, 0x1fe7, tmp);
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168 | e80cfcfc | bellard | } |
169 | e80cfcfc | bellard | |
170 | e80cfcfc | bellard | static void *slavio_intctl; |
171 | e80cfcfc | bellard | |
172 | e80cfcfc | bellard | void pic_info()
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173 | e80cfcfc | bellard | { |
174 | e80cfcfc | bellard | slavio_pic_info(slavio_intctl); |
175 | e80cfcfc | bellard | } |
176 | e80cfcfc | bellard | |
177 | e80cfcfc | bellard | void irq_info()
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178 | e80cfcfc | bellard | { |
179 | e80cfcfc | bellard | slavio_irq_info(slavio_intctl); |
180 | e80cfcfc | bellard | } |
181 | e80cfcfc | bellard | |
182 | e80cfcfc | bellard | void pic_set_irq(int irq, int level) |
183 | e80cfcfc | bellard | { |
184 | e80cfcfc | bellard | slavio_pic_set_irq(slavio_intctl, irq, level); |
185 | e80cfcfc | bellard | } |
186 | e80cfcfc | bellard | |
187 | 502a5395 | pbrook | void pic_set_irq_new(void *opaque, int irq, int level) |
188 | 502a5395 | pbrook | { |
189 | 502a5395 | pbrook | pic_set_irq(irq, level); |
190 | 502a5395 | pbrook | } |
191 | 502a5395 | pbrook | |
192 | ba3c64fb | bellard | void pic_set_irq_cpu(int irq, int level, unsigned int cpu) |
193 | ba3c64fb | bellard | { |
194 | ba3c64fb | bellard | slavio_pic_set_irq_cpu(slavio_intctl, irq, level, cpu); |
195 | ba3c64fb | bellard | } |
196 | ba3c64fb | bellard | |
197 | 3475187d | bellard | static void *slavio_misc; |
198 | 3475187d | bellard | |
199 | 3475187d | bellard | void qemu_system_powerdown(void) |
200 | 3475187d | bellard | { |
201 | 3475187d | bellard | slavio_set_power_fail(slavio_misc, 1);
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202 | 3475187d | bellard | } |
203 | 3475187d | bellard | |
204 | c68ea704 | bellard | static void main_cpu_reset(void *opaque) |
205 | c68ea704 | bellard | { |
206 | c68ea704 | bellard | CPUState *env = opaque; |
207 | c68ea704 | bellard | cpu_reset(env); |
208 | c68ea704 | bellard | } |
209 | c68ea704 | bellard | |
210 | 420557e8 | bellard | /* Sun4m hardware initialisation */
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211 | c0e564d5 | bellard | static void sun4m_init(int ram_size, int vga_ram_size, int boot_device, |
212 | c0e564d5 | bellard | DisplayState *ds, const char **fd_filename, int snapshot, |
213 | c0e564d5 | bellard | const char *kernel_filename, const char *kernel_cmdline, |
214 | c0e564d5 | bellard | const char *initrd_filename) |
215 | 420557e8 | bellard | { |
216 | ba3c64fb | bellard | CPUState *env, *envs[MAX_CPUS]; |
217 | 420557e8 | bellard | char buf[1024]; |
218 | 8d5f07fa | bellard | int ret, linux_boot;
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219 | 713c45fa | bellard | unsigned int i; |
220 | 6f7e9aec | bellard | long vram_size = 0x100000, prom_offset, initrd_size, kernel_size; |
221 | 67e999be | bellard | void *iommu, *dma, *main_esp, *main_lance = NULL; |
222 | 420557e8 | bellard | |
223 | 420557e8 | bellard | linux_boot = (kernel_filename != NULL);
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224 | 420557e8 | bellard | |
225 | ba3c64fb | bellard | /* init CPUs */
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226 | ba3c64fb | bellard | for(i = 0; i < smp_cpus; i++) { |
227 | ba3c64fb | bellard | env = cpu_init(); |
228 | ba3c64fb | bellard | envs[i] = env; |
229 | ba3c64fb | bellard | if (i != 0) |
230 | ba3c64fb | bellard | env->halted = 1;
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231 | ba3c64fb | bellard | register_savevm("cpu", i, 3, cpu_save, cpu_load, env); |
232 | ba3c64fb | bellard | qemu_register_reset(main_cpu_reset, env); |
233 | ba3c64fb | bellard | } |
234 | 420557e8 | bellard | /* allocate RAM */
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235 | 420557e8 | bellard | cpu_register_physical_memory(0, ram_size, 0); |
236 | 420557e8 | bellard | |
237 | e80cfcfc | bellard | iommu = iommu_init(PHYS_JJ_IOMMU); |
238 | e80cfcfc | bellard | slavio_intctl = slavio_intctl_init(PHYS_JJ_INTR0, PHYS_JJ_INTR_G); |
239 | ba3c64fb | bellard | for(i = 0; i < smp_cpus; i++) { |
240 | ba3c64fb | bellard | slavio_intctl_set_cpu(slavio_intctl, i, envs[i]); |
241 | ba3c64fb | bellard | } |
242 | 67e999be | bellard | dma = sparc32_dma_init(PHYS_JJ_DMA, PHYS_JJ_ESP_IRQ, PHYS_JJ_LE_IRQ, iommu, slavio_intctl); |
243 | ba3c64fb | bellard | |
244 | 95219897 | pbrook | tcx_init(ds, PHYS_JJ_TCX_FB, phys_ram_base + ram_size, ram_size, vram_size, graphic_width, graphic_height); |
245 | a41b2ff2 | pbrook | if (nd_table[0].vlan) { |
246 | a41b2ff2 | pbrook | if (nd_table[0].model == NULL |
247 | a41b2ff2 | pbrook | || strcmp(nd_table[0].model, "lance") == 0) { |
248 | 67e999be | bellard | main_lance = lance_init(&nd_table[0], PHYS_JJ_LE, dma);
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249 | a41b2ff2 | pbrook | } else {
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250 | a41b2ff2 | pbrook | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
251 | a41b2ff2 | pbrook | exit (1);
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252 | a41b2ff2 | pbrook | } |
253 | a41b2ff2 | pbrook | } |
254 | 819385c5 | bellard | nvram = m48t59_init(0, PHYS_JJ_EEPROM, 0, PHYS_JJ_EEPROM_SIZE, 8); |
255 | ba3c64fb | bellard | for (i = 0; i < MAX_CPUS; i++) { |
256 | ba3c64fb | bellard | slavio_timer_init(PHYS_JJ_CLOCK + i * TARGET_PAGE_SIZE, PHYS_JJ_CLOCK_IRQ, 0, i);
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257 | ba3c64fb | bellard | } |
258 | ba3c64fb | bellard | slavio_timer_init(PHYS_JJ_CLOCK1, PHYS_JJ_CLOCK1_IRQ, 2, (unsigned int)-1); |
259 | e80cfcfc | bellard | slavio_serial_ms_kbd_init(PHYS_JJ_MS_KBD, PHYS_JJ_MS_KBD_IRQ); |
260 | b81b3b10 | bellard | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
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261 | b81b3b10 | bellard | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
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262 | b81b3b10 | bellard | slavio_serial_init(PHYS_JJ_SER, PHYS_JJ_SER_IRQ, serial_hds[1], serial_hds[0]); |
263 | e80cfcfc | bellard | fdctrl_init(PHYS_JJ_FLOPPY_IRQ, 0, 1, PHYS_JJ_FDC, fd_table); |
264 | 67e999be | bellard | main_esp = esp_init(bs_table, PHYS_JJ_ESP, dma); |
265 | f1587550 | ths | |
266 | f1587550 | ths | for (i = 0; i < MAX_DISKS; i++) { |
267 | f1587550 | ths | if (bs_table[i]) {
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268 | f1587550 | ths | esp_scsi_attach(main_esp, bs_table[i], i); |
269 | f1587550 | ths | } |
270 | f1587550 | ths | } |
271 | f1587550 | ths | |
272 | 3475187d | bellard | slavio_misc = slavio_misc_init(PHYS_JJ_SLAVIO, PHYS_JJ_ME_IRQ); |
273 | b8174937 | bellard | cs_init(PHYS_JJ_CS, PHYS_JJ_CS_IRQ, slavio_intctl); |
274 | 67e999be | bellard | sparc32_dma_set_reset_data(dma, main_esp, main_lance); |
275 | 420557e8 | bellard | |
276 | e80cfcfc | bellard | prom_offset = ram_size + vram_size; |
277 | b3783731 | bellard | cpu_register_physical_memory(PROM_ADDR, |
278 | b3783731 | bellard | (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK,
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279 | b3783731 | bellard | prom_offset | IO_MEM_ROM); |
280 | e80cfcfc | bellard | |
281 | 0986ac3b | bellard | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAME); |
282 | 9ee3c029 | bellard | ret = load_elf(buf, 0, NULL); |
283 | e80cfcfc | bellard | if (ret < 0) { |
284 | e80cfcfc | bellard | fprintf(stderr, "qemu: could not load prom '%s'\n",
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285 | e80cfcfc | bellard | buf); |
286 | e80cfcfc | bellard | exit(1);
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287 | e80cfcfc | bellard | } |
288 | e80cfcfc | bellard | |
289 | 6f7e9aec | bellard | kernel_size = 0;
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290 | e80cfcfc | bellard | if (linux_boot) {
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291 | 9ee3c029 | bellard | kernel_size = load_elf(kernel_filename, -0xf0000000, NULL); |
292 | 6f7e9aec | bellard | if (kernel_size < 0) |
293 | 6f7e9aec | bellard | kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
294 | 6f7e9aec | bellard | if (kernel_size < 0) |
295 | 6f7e9aec | bellard | kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
296 | 6f7e9aec | bellard | if (kernel_size < 0) { |
297 | 420557e8 | bellard | fprintf(stderr, "qemu: could not load kernel '%s'\n",
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298 | e80cfcfc | bellard | kernel_filename); |
299 | e80cfcfc | bellard | exit(1);
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300 | 420557e8 | bellard | } |
301 | 713c45fa | bellard | |
302 | 713c45fa | bellard | /* load initrd */
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303 | 713c45fa | bellard | initrd_size = 0;
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304 | 713c45fa | bellard | if (initrd_filename) {
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305 | 713c45fa | bellard | initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR); |
306 | 713c45fa | bellard | if (initrd_size < 0) { |
307 | 713c45fa | bellard | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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308 | 713c45fa | bellard | initrd_filename); |
309 | 713c45fa | bellard | exit(1);
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310 | 713c45fa | bellard | } |
311 | 713c45fa | bellard | } |
312 | 713c45fa | bellard | if (initrd_size > 0) { |
313 | 713c45fa | bellard | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
314 | 713c45fa | bellard | if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
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315 | 713c45fa | bellard | == 0x48647253) { // HdrS |
316 | 713c45fa | bellard | stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
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317 | 713c45fa | bellard | stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
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318 | 713c45fa | bellard | break;
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319 | 713c45fa | bellard | } |
320 | 713c45fa | bellard | } |
321 | 713c45fa | bellard | } |
322 | 420557e8 | bellard | } |
323 | 6f7e9aec | bellard | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, boot_device, ram_size, kernel_size, graphic_width, graphic_height, graphic_depth);
|
324 | 420557e8 | bellard | } |
325 | c0e564d5 | bellard | |
326 | c0e564d5 | bellard | QEMUMachine sun4m_machine = { |
327 | c0e564d5 | bellard | "sun4m",
|
328 | c0e564d5 | bellard | "Sun4m platform",
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329 | c0e564d5 | bellard | sun4m_init, |
330 | c0e564d5 | bellard | }; |