Archipelago » qemu

target-ppc: fixes for gen_op_neg()

- Rename to gen_op_arith_neg for consistency with other functions.
- Correctly free TCG temp variable.
- Fix the return value in 64-bit mode in case of overflow.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5659 c046a42c-6fe2-441c-8c8c-71466251a162

target-ppc: optimize mullw and make the code more readable

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5657 c046a42c-6fe2-441c-8c8c-71466251a162

target-ppc: fix tcg fatal error on i386 host

It looks like the i386 runs out of registers for allocation due
to too many global registers allocated by the ppc target.

Here is a quick and dirty fix that seems to solve the problem.
This should be considered as temporary....

target-ppc: use the new rotr/rotri instructions

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5608 c046a42c-6fe2-441c-8c8c-71466251a162

target-ppc: simplify slw, srw, sld, srd

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5597 c046a42c-6fe2-441c-8c8c-71466251a162

target-ppc: fix srw on 64-bit targets

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5595 c046a42c-6fe2-441c-8c8c-71466251a162

target-ppc: convert arithmetic functions to TCG

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5590 c046a42c-6fe2-441c-8c8c-71466251a162

target-ppc: use consistent names for variables

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5557 c046a42c-6fe2-441c-8c8c-71466251a162

target-ppc: convert rotation instructions to TCG

Also fix rlwimi and rldimi for corner cases.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5555 c046a42c-6fe2-441c-8c8c-71466251a162

target-ppc: convert branch related instructions to TCG

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5508 c046a42c-6fe2-441c-8c8c-71466251a162

target-ppc: convert crf related instructions to TCG

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5505 c046a42c-6fe2-441c-8c8c-71466251a162

target-ppc: Convert XER accesses to TCG

Define XER bits as a single register and access them individually to
avoid defining 5 32-bit registers (TCG doesn't permit to map 8-bit
registers).

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5500 c046a42c-6fe2-441c-8c8c-71466251a162

PPC: convert SPE logical instructions to TCG

(Nathan Froyd)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5494 c046a42c-6fe2-441c-8c8c-71466251a162

target-ppc: fix a TCG local variable creation

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5492 c046a42c-6fe2-441c-8c8c-71466251a162

PPC: convert effective address computation to TCG

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5490 c046a42c-6fe2-441c-8c8c-71466251a162

Add concat_i32_i64 op.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5280 c046a42c-6fe2-441c-8c8c-71466251a162

ppc: Convert op_andi to TCG

Replace op_andi_... with tcg_gen_andi_tl.

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5218 c046a42c-6fe2-441c-8c8c-71466251a162

ppc: Convert op_subf to TCG

Replace op_subf with tcg_gen_sub_tl.

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5168 c046a42c-6fe2-441c-8c8c-71466251a162

ppc: replace op_set_FT0 with tcg_gen_movi_i64

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5162 c046a42c-6fe2-441c-8c8c-71466251a162

ppc: remove unused code

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5159 c046a42c-6fe2-441c-8c8c-71466251a162

ppc: fix fpr TCG registers creation

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5157 c046a42c-6fe2-441c-8c8c-71466251a162

ppc: Convert Altivec register moves to TCG

Replace op_{load,store}_avr with helpers gen_{load,store}_avr.
Introduce two sets of i64 TCG variables, cpu_avr{h,l}[0..31], and
cpu_AVR{h,l}[0..2].

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...

ppc: Convert GPR moves to TCG

Replace op_load_gpr_{T0,T1,T2} and op_store_{T0,T1,T2} with tcg_gen_mov_tl.
Introduce TCG variables cpu_gpr[0..31].

For the SPE extension, assure that ppc_gpr_t is only uint64_t for ppc64.
Introduce TCG variables cpu_gprh[0..31] for upper 32 bits on ppc and helpers...

[ppc] Convert op_reset_T0, op_set_{T0, T1} to TCG

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5142 c046a42c-6fe2-441c-8c8c-71466251a162

[ppc] Convert gen_set_{T0,T1} to TCG

The attached patch replaces gen_set_T0 and gen_set_T1 with
tcg_gen_movi_tl.

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5136 c046a42c-6fe2-441c-8c8c-71466251a162

PPC: Init TCG variables

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5093 c046a42c-6fe2-441c-8c8c-71466251a162

PPC: Switch a few instructions to TCG

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5083 c046a42c-6fe2-441c-8c8c-71466251a162

Fix encoding of efsctsiz (powerpc spe), by Tristan Gingold.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4999 c046a42c-6fe2-441c-8c8c-71466251a162

Add missing static qualifiers.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4801 c046a42c-6fe2-441c-8c8c-71466251a162

PPC: fix mtfsfi

(Tristan Gingold)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4748 c046a42c-6fe2-441c-8c8c-71466251a162

Fix broken PPC user space single stepping

(Jason Wessel)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4421 c046a42c-6fe2-441c-8c8c-71466251a162

Factorize code in translate.c

(Glauber Costa)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4274 c046a42c-6fe2-441c-8c8c-71466251a162

use the TCG code generator

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3944 c046a42c-6fe2-441c-8c8c-71466251a162

Add new sane low-level memory accessors for PowerPC that do proper
size or zero extension, with homogenous names.
Fix load & store strings: those are now endian-sensitive, by definition.
Fix dcbz: must always align the target address to a cache line boundary....

Fix another collision in PowerPC instructions definitions.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3702 c046a42c-6fe2-441c-8c8c-71466251a162

Fix collision in PowerPC instructions definitions.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3668 c046a42c-6fe2-441c-8c8c-71466251a162

Fix invalid PowerPC 64 rldimi optimized case.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3638 c046a42c-6fe2-441c-8c8c-71466251a162

PowerPC SPE extension fix: must always preserve GPR high bits when
running in 32 bits mode.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3631 c046a42c-6fe2-441c-8c8c-71466251a162

Fix usage of the -1 constant in the PowerPC target code:
fix invalid size casts and/or sign-extensions.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3626 c046a42c-6fe2-441c-8c8c-71466251a162

PowerPC 601 need specific callbacks for its BATs setup.
Implement PowerPC 601 HID0 register, needed for little-endian mode support.
As a consequence, we need to merge hflags coming from MSR with other ones.
Use little-endian mode from hflags instead of MSR during code translation....

Don't print any message when a priviledge exception occurs on mfpvr
as the Linux allows applications to read this register.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3510 c046a42c-6fe2-441c-8c8c-71466251a162

PowerPC coding style and inlining fixes.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3461 c046a42c-6fe2-441c-8c8c-71466251a162

Bugfix in PowerPC dcbi instruction:
we must do a load before the store, or we'll store random data.
Update cache instructions comments.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3448 c046a42c-6fe2-441c-8c8c-71466251a162

Gprof prooved the PowerPC emulation spent too much time in MSR load and store
routines. Coming back to a raw MSR storage model then speed-up the emulation.
Improve fast MSR updates (wrtee wrteei and mtriee cases).
Share rfi family instructions helpers code to avoid bug in duplicated code....

Work-around C89 and/or "old" gcc unspecified behavior (#if in macro calls).

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3350 c046a42c-6fe2-441c-8c8c-71466251a162

PowerPC target coding style fixes.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3348 c046a42c-6fe2-441c-8c8c-71466251a162

Reorganize the CPUPPCState structure to group features.
Add #ifdef to avoid compiling not relevant resources:
- MMU related stuff for user-mode only targets
- PowerPC 64 only resources for PowerPC 32 targets
- embedded PowerPC extensions for non-ppcemb targets....

Full implementation of PowerPC 64 MMU, just missing support for 1 TB
memory segments.
Remove the PowerPC 64 "bridge" MMU model and implement segment registers
emulation using SLB entries instead.
Make SLB area size implementation dependant.
Improve TLB & SLB search debug traces....

Code provision for hypervisor mode memory accesses.
Add comments in load & store tables to ease code reading.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3313 c046a42c-6fe2-441c-8c8c-71466251a162

Handle all MMU models in switches, even if it's just to abort because of lack
of supporting code.
Implement 74xx software TLB model.
Keep 74xx with software TLB disabled, as Linux is not able to handle TLB miss
on those processors.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3307 c046a42c-6fe2-441c-8c8c-71466251a162