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# Date Author Comment
ecdffbcc 11/19/2012 08:22 pm malc

tcg/ppc: Remove unused s_bits variable

Thanks to Alexander Graf for heads up.

Signed-off-by: malc <>
c878da3b 11/06/2012 02:37 am malc

tcg/ppc32: Use trampolines to trim the code size for mmu slow path accessors

mmu access looks something like:

<check tlb>
if miss goto slow_path
<fast path>
done:
...

; end of the TB
slow_path:

 mr r3, r27         ; move areg0 to r3
                    ; (r3 holds the first argument for all the PPC32 ABIs)...
ed224a56 11/03/2012 06:17 pm malc

tcg/ppc: ld/st optimization

Signed-off-by: malc <>
0aed257f 10/06/2012 07:48 pm Richard Henderson

tcg: Add TCG_COND_NEVER, TCG_COND_ALWAYS

There are several cases that can be handled easier inside both
translators and code generators if we have out-of-band values
for conditions. It's easy enough to handle ALWAYS and NEVER in
the natural way inside the tcg middle-end....
626cd050 10/06/2012 07:47 pm Aurelien Jarno

tcg: remove obsolete jmp op

The TCG jmp operation doesn't really make sense in the QEMU context, it
is unused, it is not implemented by some targets, and it is wrongly
implemented by some others.

This patch simply removes it.

Reviewed-by: Richard Henderson <>...
23f3ff26 09/22/2012 06:16 pm malc

tcg/ppc32: Implement movcond32

Thanks to Richard Henderson

Signed-off-by: malc <>
6e17d0c5 09/22/2012 05:52 pm Stefan Weil

tcg: Remove tcg_target_get_call_iarg_regs_count

The TCG targets no longer need individual implementations.

Since commit 6a18ae2d2947532d5c26439548afa0481c4529f9,
'flags' is no longer used in tcg_target_get_call_iarg_regs_count.

The remaining tcg_target_get_call_iarg_regs_count is trivial and only...
89c33337 09/15/2012 08:51 pm Blue Swirl

Remove unused CONFIG_TCG_PASS_AREG0 and dead code

Now that CONFIG_TCG_PASS_AREG0 is enabled for all targets,
remove dead code and support for !CONFIG_TCG_PASS_AREG0 case.

Remove dyngen-exec.h and all references to it. Although included by
hw/spapr_hcall.c, it does not seem to use it....
affe5189 06/24/2012 01:54 am Alexander Graf

TCG: Fix compile breakage in tcg_dump_ops

Commit eeacee4d865 changed the syntax of tcg_dump_ops, but didn't convert
all users (notably missing the ppc ones) to it. Fix them to the new syntax.

Signed-off-by: Alexander Graf <>
Signed-off-by: malc <>
24f50d7e 05/27/2012 08:52 pm Andreas Färber

tcg/ppc: Handle _CALL_DARWIN being undefined on Darwin

powerpc-apple-darwin9-gcc-4.2.1 (GCC) 4.2.1 (Apple Inc. build 5577)
does not define _CALL_DARWIN, leading to unexpected behavior w.r.t.
register clobbering and stack frame layout.

Since _CALL_DARWIN is a reserved identifier, define a custom...
d831fdb0 05/09/2012 09:59 pm Andreas Färber

tcg/ppc: Don't hardcode register numbers

Also assure i64 alignment where necessary.

Alignment code optimization suggested by malc.

Signed-off-by: Andreas Färber <>
Acked-by: Alexander Graf <>
Signed-off-by: Anthony Liguori <>
a082615b 05/09/2012 09:59 pm Andreas Färber

tcg/ppc: Clobber r5 for 64-bit qemu_ld

This accounts for the additional addr_reg2 register.

Signed-off-by: Andreas Färber <>
Acked-by: Alexander Graf <>
Signed-off-by: Anthony Liguori <>
1b3e76eb 05/09/2012 09:59 pm Andreas Färber

tcg/ppc: Fix CONFIG_TCG_PASS_AREG0 mode

Adjust the tcg_out_qemu_{ld,st}() slow paths to pass AREG0 in r3,
based on patches by malc.

Also adjust the registers clobbered, based on patch by Alex.

Signed-off-by: Andreas Färber <>
Acked-by: Alexander Graf <>...
c1696d94 05/09/2012 09:59 pm Andreas Färber

tcg/ppc: Do not overwrite lower address word on Darwin and AIX

For targets where TARGET_LONG_BITS != 32, i.e. 64-bit guests,
addr_reg is moved to r4. For hosts without TCG_TARGET_CALL_ALIGN_ARGS
either data_reg2 or data_reg or a masked version thereof would overwrite...
f05ae537 05/03/2012 02:48 pm malc

Bail out if CONFIG_TCG_PASS_AREG0 is defined

Signed-off-by: malc <>
e141ab52 03/18/2012 02:21 pm Blue Swirl

softmmu templates: optionally pass CPUState to memory access functions

Optionally, make memory access helpers take a parameter for CPUState
instead of relying on global env.

On most targets, perform simple moves to reorder registers. On i386,
switch from regparm(3) calling convention to standard stack-based...
9349b4f9 03/14/2012 11:20 pm Andreas Färber

Rename CPUState -> CPUArchState

Scripted conversion:
for file in .[hc] hw/.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do
sed -i "s/CPUState/CPUArchState/g" $file
done...
2a534aff 11/14/2011 06:47 pm Richard Henderson

tcg: Use TCGReg for standard tcg-target entry points.

Including tcg_out_ld, tcg_out_st, tcg_out_mov, tcg_out_movi.

Signed-off-by: Richard Henderson <>
Reviewed-by: Andreas Färber <>
Reviewed-by: Stefan Weil <>...
70d705fd 09/01/2011 08:20 pm Peter Maydell

tcg/ppc/tcg-target.c: Avoid 'set but not used' gcc warnings

Move the declaration and initialisation of some variables in
tcg_out_qemu_ld and tcg_out_qemu_st inside CONFIG_SOFTMMU, to
avoid the "variable set but not used" warning of gcc 4.6.

Signed-off-by: Peter Maydell <>...
350dba6c 08/22/2011 01:39 pm malc

tcg/ppc32: implement deposit_i32

Signed-off-by: malc <>
136a0b5a 06/28/2011 01:49 am Blue Swirl

TCG/PPC: use stack for TCG temps

Use stack instead of temp_buf array in CPUState for TCG temps.

Signed-off-by: Blue Swirl <>
Signed-off-by: malc <>
1a2eb162 06/28/2011 01:26 am malc

tcg/ppc: Remove tcg_out_addi

The only user (within tcg.c) was removed

Signed-off-by: malc <>
614f104d 06/26/2011 09:25 pm Blue Swirl

Delegate setup of TCG temporaries to targets

Delegate TCG temp_buf setup to targets, so that they can use a stack
frame later instead.

Signed-off-by: Blue Swirl <>
cea5f9a2 06/26/2011 09:25 pm Blue Swirl

cpu-exec.c: avoid AREG0 use

Make functions take a parameter for CPUState instead of relying
on global env. Pass CPUState pointer to TCG prologue, which moves
it to AREG0.

Thanks to Peter Maydell and Laurent Desnogues for the ARM prologue
change.

Revert the hacks to avoid AREG0 use on Sparc hosts....
b9e946c7 06/29/2010 10:30 pm Richard Henderson

tcg-ppc: Conditionally reserve TCG_GUEST_BASE_REG.

We need not reserve the register unless we're going to use it.

Signed-off-by: Richard Henderson <>
Signed-off-by: malc <>
e4d58b41 06/09/2010 12:18 pm Richard Henderson

tcg: Make some tcg-target.c routines static.

Both tcg_target_init and tcg_target_qemu_prologue
are unused outside of tcg.c.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
3b6dac34 06/09/2010 12:18 pm Richard Henderson

tcg: Add TYPE parameter to tcg_out_mov.

Mirror tcg_out_movi in having a TYPE parameter. This allows x86_64
to perform the move at the proper width, which may elide a REX prefix.

Introduce a TCG_TYPE_REG enumerator to represent the "native width"
of the host register, and to distinguish the usage from "pointer data"...
606257c6 04/18/2010 07:46 am malc

tcg/ppc: Remove redundant comparison from brcond2

Signed-off-by: malc <>
efe72c8d 04/17/2010 07:00 am malc

tcg/ppc: Fix signed versions of brcond2

Thanks to: Alexander Graff, Thomas Gleixner and Andreas Faerber.

Signed-off-by: malc <>
f7e2aca8 04/06/2010 02:10 am malc

tcg/ppc: Fix typo

Signed-off-by: malc <>
a884dcb8 04/06/2010 01:54 am malc

tcg/ppc: Implment bswap16/32

Signed-off-by: malc <>
aa77bebd 04/05/2010 03:09 pm malc

tcg/ppc: Implement eqv, nand and nor

Signed-off-by: malc <>
355b1943 04/05/2010 02:28 am Paul Brook

Split TLB addend and target_phys_addr_t

Historically the qemu tlb "addend" field was used for both RAM and IO accesses,
so needed to be able to hold both host addresses (unsigned long) and guest
physical addresses (target_phys_addr_t). However since the introduction of...
36368cf0 04/04/2010 07:36 pm malc

tcg/ppc: Fix not_i32

Thanks to Alexander Graf for bug report and a good reproducible test
case.

Signed-off-by: malc <>
86feb1c8 03/27/2010 12:01 am Richard Henderson

tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.

Some targets (e.g. Alpha and MIPS64) need to keep 32-bit operands
sign-extended in 64-bit registers (regardless of the "real" sign
of the operand). For that, we need to be able to distinguish
between a 32-bit load with a 32-bit result and a 32-bit load with...
8a56e840 03/26/2010 10:29 pm Richard Henderson

tcg: Use TCGCond where appropriate.

Use the TCGCond enumeration type in the brcond and setcond
related prototypes in tcg-op.h and each code generator.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
a9751609 03/26/2010 10:28 pm Richard Henderson

tcg: Name the opcode enumeration.

Give the enumeration formed from tcg-opc.h a name: TCGOpcode.
Use that enumeration type instead of "int" whereever appropriate.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
35f6b599 03/12/2010 11:27 pm malc

tcg/ppc64: Only define addend load helpers in softmmu case

Signed-off-by: malc <>
d616cf1d 02/27/2010 01:00 am malc

tcg/ppc: Fix right rotation

Signed-off-by: malc <>
98b8d951 02/22/2010 11:50 pm malc

tcg/ppc: Fix typo

Signed-off-by: malc <>
65fe043e 02/22/2010 08:50 pm malc

tcg/ppc: Implement some of the optional ops

Signed-off-by: malc <>
30c0c76c 02/22/2010 06:38 pm Jay Foad

tcg: fix build on 32-bit hppa, ppc and sparc hosts

The qemu_ld32s op is only defined if TCG_TARGET_REG_BITS == 64.

Signed-off-by: Jay Foad <>
Signed-off-by: malc <>
6ec85236 02/20/2010 12:47 am malc

tcg/ppc: Consistently use calling convention selection macros

Signed-off-by: malc <>
27a7797b 02/07/2010 01:48 am malc

tcg/ppc32: proper setcond implementation

Signed-off-by: malc <>
b0809bf7 02/07/2010 01:18 am malc

tcg/ppc32: implement setcond2

Signed-off-by: malc <>
d9370327 09/27/2009 01:41 pm malc

tcg/ppc: always use tcg_out_call

Signed-off-by: malc <>
c45851c4 09/06/2009 06:24 am malc

When targeting PPU use rlwinm instead of andi. if possible

andi. is microcoded and slow there.

Signed-off-by: malc <>
a71836de 07/20/2009 12:15 am malc

Fix rbase initialization

Signed-off-by: malc <>
f6548c0a 07/18/2009 12:16 pm malc

PPC 32/64 GUEST_BASE support

Signed-off-by: malc <>
4f4a67ae 07/18/2009 12:16 pm malc

Fix LHZX opcode value

Signed-off-by: malc <>
9de187a0 04/11/2009 10:39 am malc

Whack [LS]MW

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7081 c046a42c-6fe2-441c-8c8c-71466251a162
e23f2f36 04/11/2009 10:38 am malc

Remove reserved registers from tcg_target_reg_alloc_order

Noticed by Andreas Faerber

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7080 c046a42c-6fe2-441c-8c8c-71466251a162
eb2eb1dc 02/11/2009 08:51 pm malc

Add missing r24..r26 to calle save registers

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6612 c046a42c-6fe2-441c-8c8c-71466251a162
5db3ee79 01/26/2009 08:21 pm malc

R13 is reserved for small data area pointer by SVR4 PPC ABI

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6450 c046a42c-6fe2-441c-8c8c-71466251a162
b1503cda 12/22/2008 10:33 pm malc

Use the ARRAY_SIZE() macro where appropriate.

Change from v1:
Avoid changing the existing coding style in certain files.

Signed-off-by: Stuart Brady <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6120 c046a42c-6fe2-441c-8c8c-71466251a162
b29fe3ed 11/18/2008 03:42 am malc

Preliminary AIX support

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5732 c046a42c-6fe2-441c-8c8c-71466251a162
2946898b 11/12/2008 10:36 pm malc

Rename misnamed BACK_CHAIN_OFFSET to LR_OFFSET

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5711 c046a42c-6fe2-441c-8c8c-71466251a162
d4a9eb1f 10/05/2008 12:59 pm blueswir1

Add some missing static and const qualifiers, reg_names only used if NDEBUG set

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5421 c046a42c-6fe2-441c-8c8c-71466251a162
f8edcbaa 09/22/2008 04:08 am malc

Avoid clobbering input register in qemu_ld64+bswap+useronly case

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5287 c046a42c-6fe2-441c-8c8c-71466251a162
79383c9c 08/30/2008 12:51 pm blueswir1

Fix some warnings that would be generated by gcc -Wredundant-decls

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162
70fa887c 08/21/2008 04:14 am malc

Relax qemu_ld/st constraints for !SOFTMMU case

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5038 c046a42c-6fe2-441c-8c8c-71466251a162
bf6bca52 08/03/2008 10:04 pm malc

Account for MacOS X ABI reserved space in linkage area (Andreas Faerber)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4985 c046a42c-6fe2-441c-8c8c-71466251a162
f9bf2987 08/03/2008 10:04 pm malc

Preliminary MacOS X on PPC32 support

Big thanks to BlueSwirl for Sparc failure analysis.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4984 c046a42c-6fe2-441c-8c8c-71466251a162
52781543 07/29/2008 11:08 pm malc

On ppc32 make tb_set_jmp_target1 behave like it does on a ppc64

Avoids nasty warnings about flush_icache_range from gcc4 and inability
to compile [cpu-]exec.c with gcc3 and -O, also the function is much
too large to be candidate for inlining anyway.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4974 c046a42c-6fe2-441c-8c8c-71466251a162
000a2d86 07/29/2008 02:46 am malc

Do not try handle "special" arguments of and/or/xor/shl/shr, upper level does it

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4961 c046a42c-6fe2-441c-8c8c-71466251a162
e46b9681 07/23/2008 11:01 pm malc

Provide extNs_M instructions

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4934 c046a42c-6fe2-441c-8c8c-71466251a162
e924c485 07/04/2008 02:49 am malc

Fuse EQ and NE handling in tcg_out_brcond2

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4845 c046a42c-6fe2-441c-8c8c-71466251a162
8c5e95d8 07/03/2008 09:51 pm malc

Mask LL portion of B to 24 bits in tcg_out_b (Thanks to Thiemo Seufer)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4841 c046a42c-6fe2-441c-8c8c-71466251a162
ca88500f 06/23/2008 08:47 am malc

According to gcc-4.3.0/gcc/config/rs6000/crtsavres.asm R13 is volatile

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4779 c046a42c-6fe2-441c-8c8c-71466251a162
a35e86c5 06/23/2008 08:47 am malc

Shuffle contents of tcg_target_reg_alloc_order

Move reserved/volatile registers down. Currently qemu_ld/stXX are
marked with TCG_OPF_CALL_CLOBBER and since memory accesses are
frequent and R3 through R12 are volatile moving this down results in
less spills and tighter generated code....
17ca26e7 06/18/2008 04:58 am malc

Save LR into proper place on callers stack frame

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4745 c046a42c-6fe2-441c-8c8c-71466251a162
c596defd 06/12/2008 03:33 pm malc

Reimplement brcond2 and refactor brcond

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4738 c046a42c-6fe2-441c-8c8c-71466251a162
0d5bd363 06/10/2008 04:47 am malc

Remove stray variable

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4725 c046a42c-6fe2-441c-8c8c-71466251a162
77b73de6 06/10/2008 02:44 am malc

Use rem/div[u]_i32 drop div[u]2_i32

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4722 c046a42c-6fe2-441c-8c8c-71466251a162
fa4fbfb9 06/09/2008 10:57 pm malc

Emit trampolines manually in prologue

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4715 c046a42c-6fe2-441c-8c8c-71466251a162
5d794885 06/09/2008 10:57 pm malc

Fix test for signed div fast path

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4714 c046a42c-6fe2-441c-8c8c-71466251a162
398ce98e 06/09/2008 09:06 am malc

Fix div[u]2.

Previous code assummed 32 by 32 bit divmod operation, and survived
x86_64 test only by sheer luck. MIPS wasn't so forgiving.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4705 c046a42c-6fe2-441c-8c8c-71466251a162
0a878c47 06/07/2008 11:31 pm malc

PPC TCG Fixes

  • Fix typo in aliased div2
  • "Optimize" aliased div2/divu2
  • Fix two remaining branch retranslation problems
    (Kudos to Andrzej Zaborowski)
  • Rework goto_tb and set_jmp_target1
  • Use correct size when flushing icache
  • Use correct register selection for ORI...
932a6909 05/30/2008 11:56 pm bellard

support of long calls for PPC (malc)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4629 c046a42c-6fe2-441c-8c8c-71466251a162
f3f478a7 05/26/2008 10:11 pm bellard

Fix signed/unsigned issues of immediate version of brcond (malc)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4588 c046a42c-6fe2-441c-8c8c-71466251a162
2662e13f 05/25/2008 09:59 pm bellard

ppc TCG target (malc)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4584 c046a42c-6fe2-441c-8c8c-71466251a162